JPS6423132U - - Google Patents

Info

Publication number
JPS6423132U
JPS6423132U JP11894587U JP11894587U JPS6423132U JP S6423132 U JPS6423132 U JP S6423132U JP 11894587 U JP11894587 U JP 11894587U JP 11894587 U JP11894587 U JP 11894587U JP S6423132 U JPS6423132 U JP S6423132U
Authority
JP
Japan
Prior art keywords
frequency
input tuning
control signal
synthesizer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11894587U
Other languages
Japanese (ja)
Other versions
JPH0438587Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11894587U priority Critical patent/JPH0438587Y2/ja
Publication of JPS6423132U publication Critical patent/JPS6423132U/ja
Application granted granted Critical
Publication of JPH0438587Y2 publication Critical patent/JPH0438587Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Superheterodyne Receivers (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係るシンセサイザ受信機の
要部の一例を示す接続図、第2図は従来のシンセ
サイザ受信機の接続図である。 1……シンセサイザ受信機、10……シンセサ
イザチユーナ、12……可変発振器、13……周
波数制御部、17……マイクロコンピユータ、2
0……入力同調回路、30……発振回路、35…
…同調部。
FIG. 1 is a connection diagram showing an example of essential parts of a synthesizer receiver according to this invention, and FIG. 2 is a connection diagram of a conventional synthesizer receiver. DESCRIPTION OF SYMBOLS 1... Synthesizer receiver, 10... Synthesizer tuner, 12... Variable oscillator, 13... Frequency control section, 17... Microcomputer, 2
0...Input tuning circuit, 30...Oscillation circuit, 35...
...Synchronization department.

Claims (1)

【実用新案登録請求の範囲】 高周波増幅器に設けられた入力同調回路と、 シンセサイザチユーナと、 入力同調周波数と同一の周波数を発振するPL
L構成の発振回路とを有し、 この発振回路の同調部に供給される周波数制御
信号が入力同調回路に同じく周波数制御信号とし
て供給されるようになされたことを特徴とするシ
ンセサイザ受信機。
[Claims for Utility Model Registration] An input tuning circuit provided in a high frequency amplifier, a synthesizer tuner, and a PL that oscillates at the same frequency as the input tuning frequency.
1. A synthesizer receiver comprising: an oscillation circuit having an L configuration, wherein a frequency control signal supplied to a tuning section of the oscillation circuit is also supplied to an input tuning circuit as a frequency control signal.
JP11894587U 1987-08-03 1987-08-03 Expired JPH0438587Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11894587U JPH0438587Y2 (en) 1987-08-03 1987-08-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11894587U JPH0438587Y2 (en) 1987-08-03 1987-08-03

Publications (2)

Publication Number Publication Date
JPS6423132U true JPS6423132U (en) 1989-02-07
JPH0438587Y2 JPH0438587Y2 (en) 1992-09-09

Family

ID=31363740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11894587U Expired JPH0438587Y2 (en) 1987-08-03 1987-08-03

Country Status (1)

Country Link
JP (1) JPH0438587Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007141932A1 (en) * 2006-06-02 2007-12-13 Neuro Solution Corp. Antenna input tuning circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007141932A1 (en) * 2006-06-02 2007-12-13 Neuro Solution Corp. Antenna input tuning circuit

Also Published As

Publication number Publication date
JPH0438587Y2 (en) 1992-09-09

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