JPS63169724U - - Google Patents

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Publication number
JPS63169724U
JPS63169724U JP6186487U JP6186487U JPS63169724U JP S63169724 U JPS63169724 U JP S63169724U JP 6186487 U JP6186487 U JP 6186487U JP 6186487 U JP6186487 U JP 6186487U JP S63169724 U JPS63169724 U JP S63169724U
Authority
JP
Japan
Prior art keywords
input
local oscillator
circuit
frequency
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6186487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6186487U priority Critical patent/JPS63169724U/ja
Publication of JPS63169724U publication Critical patent/JPS63169724U/ja
Pending legal-status Critical Current

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  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案にかかるPLLシンセサイザ式
受信機の要部ブロツク図、第2図は局部発振部の
回路例、第3図は従来のPLLシンセサイザ式受
信機を説明するためのブロツク図、第4図はPL
L回路のブロツク図である。 1……アンテナ、2……高周波増幅器、3……
局部発振部、3a……局部発振器、3b……周波
数逓倍回路、4……混合器、7……PLL回路。
FIG. 1 is a block diagram of the main parts of a PLL synthesizer type receiver according to the present invention, FIG. 2 is a circuit example of a local oscillator, and FIG. 3 is a block diagram for explaining a conventional PLL synthesizer type receiver. Figure 4 is PL
FIG. 3 is a block diagram of an L circuit. 1...Antenna, 2...High frequency amplifier, 3...
Local oscillator, 3a... Local oscillator, 3b... Frequency multiplier circuit, 4... Mixer, 7... PLL circuit.

Claims (1)

【実用新案登録請求の範囲】 フロントエンドにおける電圧制御型の局部発振
器と混合器の間に周波数逓倍回路を設け、 該局部発振器の出力をPLL回路に直接入力す
ると共に、周波数をN逓倍して混合器に入力する
ことを特徴とするPLLシンセサイザ式受信機。
[Claims for Utility Model Registration] A frequency multiplier circuit is provided between the voltage-controlled local oscillator and the mixer in the front end, and the output of the local oscillator is directly input to the PLL circuit, and the frequency is multiplied by N and mixed. A PLL synthesizer type receiver characterized in that input is input to a receiver.
JP6186487U 1987-04-23 1987-04-23 Pending JPS63169724U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6186487U JPS63169724U (en) 1987-04-23 1987-04-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6186487U JPS63169724U (en) 1987-04-23 1987-04-23

Publications (1)

Publication Number Publication Date
JPS63169724U true JPS63169724U (en) 1988-11-04

Family

ID=30895594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6186487U Pending JPS63169724U (en) 1987-04-23 1987-04-23

Country Status (1)

Country Link
JP (1) JPS63169724U (en)

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