JPS58123632U - Transmitter using PLL circuit - Google Patents
Transmitter using PLL circuitInfo
- Publication number
- JPS58123632U JPS58123632U JP1937582U JP1937582U JPS58123632U JP S58123632 U JPS58123632 U JP S58123632U JP 1937582 U JP1937582 U JP 1937582U JP 1937582 U JP1937582 U JP 1937582U JP S58123632 U JPS58123632 U JP S58123632U
- Authority
- JP
- Japan
- Prior art keywords
- output
- mixer
- transmitter
- pll circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Transmitters (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案を実施した送信機の構成何区である。
１・・・・・・電圧制御発振器、２・・・・・・分周器
１．３・・・・・・位相検出器、４，７・・・・・・緩
衝増幅器、５・・・・・・混合器、６・・・・・・局部
発振器、８・・・・・・高周波電力増幅器、９・・・・
・・出力電力、１０・・・・・・送信オン−オフキーイ
ング信号。The drawing shows the configuration of a transmitter implementing the present invention. 1... Voltage controlled oscillator, 2... Frequency divider 1.3... Phase detector, 4, 7... Buffer amplifier, 5... ...Mixer, 6...Local oscillator, 8...High frequency power amplifier, 9...
...Output power, 10...Transmission on-off keying signal.
Claims (1)
に設けた局部発振器の出力を混合する混合器と、この混
合器よりの入力を外部よりの送信オン−オフ信号によっ
てキーイングし、所要の電力を出力する高周波電力増幅
回路とを備えた送信機の電圧制御発振器の出力と、混合
器入力の間および混合器出力と高周波電力増幅器間にそ
れ尋°れ緩衝用増幅器を界在させて後段の変動が前段の
特性に影響を及ぼすことを防止したことを特徴とするＰ
ＬＬ回路を用いた送信機。The voltage controlled oscillator of the PLL circuit, a mixer that mixes its oscillation output and the output of a separately provided local oscillator, and the input from this mixer is keyed by an external transmission on-off signal to output the required power. A buffer amplifier is interposed between the output of the voltage-controlled oscillator of the transmitter equipped with a high-frequency power amplification circuit and the mixer input, and between the mixer output and the high-frequency power amplifier to prevent fluctuations in the subsequent stage. P characterized in that it is prevented from affecting the characteristics of the previous stage.
Transmitter using LL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1937582U JPS58123632U (en) | 1982-02-16 | 1982-02-16 | Transmitter using PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1937582U JPS58123632U (en) | 1982-02-16 | 1982-02-16 | Transmitter using PLL circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58123632U true JPS58123632U (en) | 1983-08-23 |
Family
ID=30031590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1937582U Pending JPS58123632U (en) | 1982-02-16 | 1982-02-16 | Transmitter using PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123632U (en) |
-
1982
- 1982-02-16 JP JP1937582U patent/JPS58123632U/en active Pending
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