JPH02111937U - - Google Patents
Info
- Publication number
- JPH02111937U JPH02111937U JP1916089U JP1916089U JPH02111937U JP H02111937 U JPH02111937 U JP H02111937U JP 1916089 U JP1916089 U JP 1916089U JP 1916089 U JP1916089 U JP 1916089U JP H02111937 U JPH02111937 U JP H02111937U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- circuit
- output signal
- output
- controlled oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000001914 filtration Methods 0.000 claims 1
- 230000010355 oscillation Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 7
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図はこの考案の一実施例を示すPLL発振
器の構成図、第2図はこの考案の一実施例を示す
PLL発振器に用いられているループフイルタの
回路図、第3図は従来のPLL発振器の構成図、
第4図は従来のPLL発振器に用いられているル
ープフイルタの回路図、第5図は基準信号源とV
COの出力信号の位相雑音特性図、第6図はルー
プフイルタの利得特性図である。
図において、1は基準信号源、2はVCO、3
は位相検波器、4はスイープ回路、5は帯域通過
フイルタ、6は信号レベル検出器、7はロツク判
定回路、8はループフイルタ、9は演算増幅器、
10,11,12,13,16は抵抗、14はコ
ンデンサ、15はアナログスイツチ、17はルー
プフイルタ、イは出力端子、ロは入力端子、ハは
出力端子、ニは論理入力端子である。なお、図中
同一符号は同一または相当部分を示す。
Fig. 1 is a block diagram of a PLL oscillator showing an embodiment of this invention, Fig. 2 is a circuit diagram of a loop filter used in a PLL oscillator showing an embodiment of this invention, and Fig. 3 is a diagram of a conventional PLL oscillator. Oscillator configuration diagram,
Figure 4 is a circuit diagram of a loop filter used in a conventional PLL oscillator, and Figure 5 is a reference signal source and V
FIG. 6 is a phase noise characteristic diagram of the output signal of the CO, and FIG. 6 is a gain characteristic diagram of the loop filter. In the figure, 1 is the reference signal source, 2 is the VCO, and 3
is a phase detector, 4 is a sweep circuit, 5 is a band pass filter, 6 is a signal level detector, 7 is a lock determination circuit, 8 is a loop filter, 9 is an operational amplifier,
10, 11, 12, 13, and 16 are resistors, 14 is a capacitor, 15 is an analog switch, 17 is a loop filter, A is an output terminal, B is an input terminal, C is an output terminal, and D is a logic input terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
が変化する電圧制御発振器と、上記基準信号源と
上記電圧制御発振器の出力信号の位相を比較し、
誤差電圧を出力する位相検波器と、上記電圧制御
発振器の出力信号が上記基準信号源の出力信号に
位相同期していない時スイープ動作するスイープ
回路と、上記電圧制御発振器の出力信号の一部を
取り出し帯域ろ波する帯域通過フイルタと上記帯
域通過フイルタの出力信号のレベルを検出する信
号レベル検出器からなり、上記電圧制御発振器の
出力信号が上記基準信号源の出力信号に位相同期
しているかどうかを判定し、その結果を表示する
ロツク判定回路と、演算増幅器の非反転入力端子
と接地点の間に抵抗を、反転入力端子と出力端子
の間に抵抗とコンデンサの直列回路と、それと並
列に抵抗を、反転入力端子にアナログスイツチと
抵抗を並列接続したものに更に直列に抵抗を接続
した回路をその一端を開放して有し、上記ロツク
判定回路の出力により伝達特性が変化するループ
フイルタとで構成したことを特徴とするPLL(
Phase−Locked Loop)発振器。 comparing a reference signal source, a voltage controlled oscillator whose oscillation frequency changes in response to a control voltage, and phases of output signals of the reference signal source and the voltage controlled oscillator;
a phase detector that outputs an error voltage; a sweep circuit that sweeps when the output signal of the voltage controlled oscillator is not phase synchronized with the output signal of the reference signal source; It consists of a bandpass filter that performs bandpass filtering and a signal level detector that detects the level of the output signal of the bandpass filter, and determines whether the output signal of the voltage controlled oscillator is phase-locked with the output signal of the reference signal source. A lock judgment circuit that judges and displays the result, a resistor between the non-inverting input terminal of the operational amplifier and the ground point, a series circuit of a resistor and a capacitor between the inverting input terminal and the output terminal, and a series circuit of a resistor and a capacitor in parallel. A loop filter has a circuit in which an analog switch and a resistor are connected in parallel to the inverting input terminal, and a resistor is further connected in series, with one end open, and the transfer characteristic changes according to the output of the lock determination circuit. A PLL (
Phase-Locked Loop) oscillator.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1916089U JPH02111937U (en) | 1989-02-21 | 1989-02-21 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1916089U JPH02111937U (en) | 1989-02-21 | 1989-02-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02111937U true JPH02111937U (en) | 1990-09-07 |
Family
ID=31234426
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1916089U Pending JPH02111937U (en) | 1989-02-21 | 1989-02-21 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02111937U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010200383A (en) * | 1998-08-07 | 2010-09-09 | Thomson Consumer Electronics Inc | Horizontal frequency signal generator,synchronous circuit, and video display device |
-
1989
- 1989-02-21 JP JP1916089U patent/JPH02111937U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010200383A (en) * | 1998-08-07 | 2010-09-09 | Thomson Consumer Electronics Inc | Horizontal frequency signal generator,synchronous circuit, and video display device |
JP2010233248A (en) * | 1998-08-07 | 2010-10-14 | Thomson Consumer Electronics Inc | Horizontal frequency signal generator, synchronization circuit, and video display device |