JPH02113441U

JPH02113441U -

Info

Publication number: JPH02113441U
Application number: JP2229489U
Authority: JP
Priority date: 1989-02-28
Filing date: 1989-02-28
Publication date: 1990-09-11

Description

[Brief explanation of the drawing]

第１図は本考案に係る位相同期ループ回路の一
実施例を示す構成ブロツク図、第２図は位相同期
ループ回路の従来例を示す構成ブロツク図、第３
図は第２図装置の出力周波数範囲を示す図である
。２……第１の位相比較部、４，１２……第１の
スイツチ手段、５……演算増幅器、６……電圧制
御発振器、１０……第２の位相比較部、１３……
第１のオフセツト電圧回路、１４……第１の比較
手段、１５……第２のオフセツト電圧回路、１６
……第２の比較手段、１７，１８……第２のスイ
ツチ手段、２０……第３のスイツチ手段、Ｃ……
積分用キヤパシタ、Ｓ_１……第１の基準信号、Ｓ
_３……第２の基準信号、ｆ_０……出力周波数、Ｖ
Ｒ……上限設定値、−ＶＲ……下限設定値、ＳＲ
……ロツク外れ信号。 FIG. 1 is a configuration block diagram showing one embodiment of a phase-locked loop circuit according to the present invention, FIG. 2 is a configuration block diagram showing a conventional example of a phase-locked loop circuit, and FIG.
The figure is a diagram showing the output frequency range of the apparatus of FIG. 2. 2...First phase comparison section, 4, 12...First switching means, 5...Operation amplifier, 6...Voltage controlled oscillator, 10...Second phase comparison section, 13...
First offset voltage circuit, 14...First comparison means, 15...Second offset voltage circuit, 16
...Second comparison means, 17, 18...Second switch means, 20...Third switch means, C...
Integral capacitor, S ₁ ...first reference signal, S
₃ ...Second reference signal, _f0 ...Output frequency, V
R... Upper limit set value, -VR... Lower limit set value, SR
...Out-of-lock signal.

Claims

[Scope of utility model registration request]

A first phase comparison section detects a phase difference between a signal based on the output of the voltage controlled oscillator and a first reference signal, and the output of the first phase comparison section is input to the voltage controlled oscillator via an integrator. A feedback main loop circuit, a signal based on the output of the voltage controlled oscillator, and a second
A second phase comparator detects the phase difference between the reference signal and the reference signal, and the output of the second phase comparator is fed back to the input of the voltage controlled oscillator via the integrator to obtain a capture range larger than that of the main loop circuit. and a pre-tune loop circuit having a pre-tune loop circuit, when an out-of-lock signal is generated, the pre-tune loop circuit and the main loop circuit are switched between the pre-tune loop circuit and the main loop circuit, thereby changing the output frequency of the voltage controlled oscillator to the main loop circuit. In a phase-locked loop circuit that locks to a frequency within the loop's capture range,
A first offset voltage circuit that outputs a negative voltage, a second offset voltage circuit that outputs a positive voltage, and either the output voltage of the first or second offset voltage circuit is input to the integrator. Second to do
a first comparing means for comparing the output of the integrator with an upper limit set value, and a second comparing means for comparing the output of the integrator with a lower limit set value, the output of the voltage controlled oscillator The second one corresponds to the frequency.
1. A phase-locked loop circuit characterized in that the circuit is configured to control the switch means and output an out-of-lock signal from the second or third comparison means.