JPH03107812U - - Google Patents
Info
- Publication number
- JPH03107812U JPH03107812U JP1536690U JP1536690U JPH03107812U JP H03107812 U JPH03107812 U JP H03107812U JP 1536690 U JP1536690 U JP 1536690U JP 1536690 U JP1536690 U JP 1536690U JP H03107812 U JPH03107812 U JP H03107812U
- Authority
- JP
- Japan
- Prior art keywords
- vco
- output
- loop
- reference signal
- phase comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000004904 shortening Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第1図は、本考案の一実施例に係るフエーズロ
ツクループ回路の構成を示す構成図、第2図は、
この実施例におけるアンロツク検出器の説明図で
あつて、第2図aはアンロツク検出器の構成図、
第2図bはアンロツク検出器の動作を示すタイミ
ングチヤート図、第3図は、本考案の他の実施例
に係るフエーズロツクループ回路の構成を示す構
成図、第4図は、従来のフエーズロツクループ回
路の一例の構成を示す構成図である。
10……VCO、12……基準信号発生回路、
16……位相比較器、18,28……ループフイ
ルタ、20……プリエンフアシス回路、22……
スプラツタフイルタ、24……アナログスイツチ
、26……アンロツク検出器。
FIG. 1 is a block diagram showing the configuration of a phase lock loop circuit according to an embodiment of the present invention, and FIG.
FIG. 2a is an explanatory diagram of the unlock detector in this embodiment, and FIG. 2a is a configuration diagram of the unlock detector;
FIG. 2b is a timing chart showing the operation of the unlock detector, FIG. 3 is a block diagram showing the configuration of a phase lock loop circuit according to another embodiment of the present invention, and FIG. 4 is a conventional phase lock loop circuit diagram. FIG. 2 is a configuration diagram showing the configuration of an example of an air lock loop circuit. 10...VCO, 12...Reference signal generation circuit,
16... Phase comparator, 18, 28... Loop filter, 20... Pre-emphasis circuit, 22...
Splatter filter, 24...analog switch, 26...unlock detector.
Claims (1)
所定周波数の基準信号を発生させる基準信号発生
回路と、基準信号とVCOの出力とを取り込んで
位相を比較して比較結果を出力する位相比較器と
、位相比較器の出力をVCOに入力電圧として供
給し、VCOと位相比較器を含むループを所定時
定数で保持するループフイルタと、VCOに変調
信号を供給しVCOの出力に変調を施す変調信号
入力部と、を有するフエーズロツクループ回路に
おいて、 VCOの出力に基づきループがアンロツク状態
にあるかどうかを検出するアンロツク検出器と、 アンロツク検出器においてアンロツク状態が検
出されたときに、ループフイルタの時定数を小さ
くする応答短縮手段と、 を備えることを特徴とするフエーズロツクループ
回路。[Scope of claim for utility model registration] A VCO that oscillates at a frequency according to input voltage,
A reference signal generation circuit that generates a reference signal of a predetermined frequency, a phase comparator that takes in the reference signal and the output of the VCO, compares the phases, and outputs the comparison result, and outputs the output of the phase comparator to the VCO as an input voltage. A phase-locked loop circuit having a loop filter that supplies a modulation signal to the VCO and holds a loop including a VCO and a phase comparator with a predetermined time constant, and a modulation signal input section that supplies a modulation signal to the VCO and modulates the output of the VCO. , an unlock detector that detects whether the loop is in an unlock state based on the output of the VCO, and response shortening means that reduces the time constant of the loop filter when the unlock detector detects the unlock state. A phase lock loop circuit characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1536690U JPH03107812U (en) | 1990-02-19 | 1990-02-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1536690U JPH03107812U (en) | 1990-02-19 | 1990-02-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03107812U true JPH03107812U (en) | 1991-11-06 |
Family
ID=31518675
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1536690U Pending JPH03107812U (en) | 1990-02-19 | 1990-02-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03107812U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59156029A (en) * | 1983-02-25 | 1984-09-05 | Fujitsu Ltd | Phase locked loop |
-
1990
- 1990-02-19 JP JP1536690U patent/JPH03107812U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59156029A (en) * | 1983-02-25 | 1984-09-05 | Fujitsu Ltd | Phase locked loop |
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