JPH01162674U - - Google Patents
Info
- Publication number
- JPH01162674U JPH01162674U JP5748588U JP5748588U JPH01162674U JP H01162674 U JPH01162674 U JP H01162674U JP 5748588 U JP5748588 U JP 5748588U JP 5748588 U JP5748588 U JP 5748588U JP H01162674 U JPH01162674 U JP H01162674U
- Authority
- JP
- Japan
- Prior art keywords
- threshold voltage
- circuit
- input pulse
- clock
- comparators
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Manipulation Of Pulses (AREA)
Description
第１図は本考案のパルスマスク判定回路の一実
施例の構成図、第２図はクロツクジエネレータの
クロツク波形図、第３図はオープンコレクタ出力
のコンパレータのスレツシヨルド電圧である。
Ｓ１，Ｓ２……アナログスイツチ、２……クロ
ツクジエネレータ、Ｃ１，Ｃ２……オープンコレ
クタ出力のコンパレータ、４……ＥＸ―ＮＯＲ回
路、５……ＲＳ―フリツプフロツプ回路、６……
ＮＡＮＤ回路、７……ＡＮＤ回路、８……ツエナ
ーダイオード、９……ヒステリシス付コンパレー
タ、１０……ＰＬＬ回路。
FIG. 1 is a block diagram of one embodiment of the pulse mask determination circuit of the present invention, FIG. 2 is a clock waveform diagram of a clock generator, and FIG. 3 is a threshold voltage of an open collector output comparator. S1 , S2 ...Analog switch, 2...Clock generator, C1 , C2 ...Open collector output comparator, 4...EX-NOR circuit, 5...RS-flip-flop circuit, 6...
NAND circuit, 7...AND circuit, 8...Zener diode, 9...comparator with hysteresis, 10...PLL circuit.
Claims (1)
より駆動するアナログスイツチでスレツシヨルド
電圧を変化させ、そのスレツシヨルド電圧の変化
が時定数を有し、入力パルスとそのスレツシヨル
ド電圧を比較する２群のコンパレータと、 これら２群のコンパレータの出力を比較して入
力パルスがパルスマスクの範囲内にあるか否かを
判定する排他的ＮＯＲ回路と、 この排他的ＮＯＲ回路の判定結果を保持するホ
ールド回路と、 入力パルスとクロツクジエネレータのクロツク
の位相と周波数を同期させる位相ロツクループ回
路とを有するパルスマスク判定回路。[Claims for Utility Model Registration] The threshold voltage is changed by an analog switch driven by a clock output from a clock generator, the change in the threshold voltage has a time constant, and the input pulse and the threshold voltage are compared 2 a group of comparators, an exclusive NOR circuit that compares the outputs of these two groups of comparators to determine whether the input pulse is within the range of the pulse mask, and a hold that holds the determination result of this exclusive NOR circuit. and a phase lock loop circuit for synchronizing the phase and frequency of a clock of a clock generator with an input pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5748588U JPH01162674U (en) | 1988-04-28 | 1988-04-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5748588U JPH01162674U (en) | 1988-04-28 | 1988-04-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01162674U true JPH01162674U (en) | 1989-11-13 |
Family
ID=31283340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5748588U Pending JPH01162674U (en) | 1988-04-28 | 1988-04-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01162674U (en) |
-
1988
- 1988-04-28 JP JP5748588U patent/JPH01162674U/ja active Pending
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