JPH02133761U - - Google Patents
Info
- Publication number
- JPH02133761U JPH02133761U JP4019589U JP4019589U JPH02133761U JP H02133761 U JPH02133761 U JP H02133761U JP 4019589 U JP4019589 U JP 4019589U JP 4019589 U JP4019589 U JP 4019589U JP H02133761 U JPH02133761 U JP H02133761U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- timer
- trigger signal
- time
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007423 decrease Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は本考案の一実施例を示す構成ブロツク
図、第２図はステツプ信号Ｖｉｎと外部印加電源
Ｖｔの波形図、第３図はＶＣＳの動作説明図、第
４図及び第５図は第１図の装置の波形図である。
第６図はタイマ回路の動作波形図、第７図はタイ
マ回路をデイジタル回路で構成した場合の波形図
である。
１０……トリガ信号発生手段、２０……電圧保
持手段、３０……電圧調整手段、４０……コンパ
レータ、Ｃ……コンデンサ、Ｖｉｎ……ステツプ
信号、Ｖｔ……外部印加電源。
FIG. 1 is a configuration block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of the step signal Vin and externally applied power supply Vt, FIG. 3 is an explanatory diagram of the operation of the VCS, and FIGS. 4 and 5 are 2 is a waveform diagram of the device of FIG. 1; FIG.
FIG. 6 is an operational waveform diagram of the timer circuit, and FIG. 7 is a waveform diagram when the timer circuit is constructed from a digital circuit. 10...Trigger signal generation means, 20...Voltage holding means, 30...Voltage adjustment means, 40...Comparator, C...Capacitor, Vin...Step signal, Vt...Externally applied power source.
Claims (1)
信号発生手段と、 このトリガ信号で与えられた時点の外部印加電
圧を保持する手段と、 この電圧保持手段に蓄えられた電圧に対し、時
間の経過と共に当該電圧を増加又は減少させる電
圧調整手段と、 この電圧調整手段で調整した電圧としきい値電
圧とを比較するコンパレータと、 を備え、このコンパレータの出力電圧が変化した
時点を当該タイマのタイムアツプとすることを特
徴とするタイマ回路のアナログ回路シミユレータ
。[Claims for Utility Model Registration] Trigger signal generating means for giving timing to start a timer, means for holding an externally applied voltage at the time given by this trigger signal, and a voltage stored in this voltage holding means. , a voltage adjustment means that increases or decreases the voltage as time passes, and a comparator that compares the voltage adjusted by the voltage adjustment means with a threshold voltage, and detects the point at which the output voltage of the comparator changes. An analog circuit simulator for a timer circuit characterized by a timer time-up.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019589U JPH02133761U (en) | 1989-04-05 | 1989-04-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4019589U JPH02133761U (en) | 1989-04-05 | 1989-04-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02133761U true JPH02133761U (en) | 1990-11-06 |
Family
ID=31549772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4019589U Pending JPH02133761U (en) | 1989-04-05 | 1989-04-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02133761U (en) |
-
1989
- 1989-04-05 JP JP4019589U patent/JPH02133761U/ja active Pending
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