JPH02100348U - - Google Patents
Info
- Publication number
- JPH02100348U JPH02100348U JP788389U JP788389U JPH02100348U JP H02100348 U JPH02100348 U JP H02100348U JP 788389 U JP788389 U JP 788389U JP 788389 U JP788389 U JP 788389U JP H02100348 U JPH02100348 U JP H02100348U
- Authority
- JP
- Japan
- Prior art keywords
- phase
- sweep voltage
- down counter
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の一実施例の全体回路図、第２
図はスイープ電圧発生器の構成を詳細に示す位相
同期回路の回路図、第３図はＤ／Ａコンバータの
出力電圧特性を示す図である。
１…位相検波器、２…ループフイルタ、３…Ｖ
ＣＯ、４…電圧加算器、５…同期判定器、６…ス
イープ電圧発生器、７…クロツク発生器、８…ア
ツプダウンカウンタ、９…ラツチ回路、１０…デ
イジタルコンパレータ、１１…Ｄ／Ａコンバータ
。
Figure 1 is an overall circuit diagram of one embodiment of the present invention, Figure 2
The figure is a circuit diagram of a phase locked loop showing the configuration of the sweep voltage generator in detail, and FIG. 3 is a diagram showing the output voltage characteristics of the D/A converter. 1... Phase detector, 2... Loop filter, 3... V
CO, 4... Voltage adder, 5... Synchronization determiner, 6... Sweep voltage generator, 7... Clock generator, 8... Up/down counter, 9... Latch circuit, 10... Digital comparator, 11... D/A converter.
Claims (1)
ープ電圧発生器からのスイープ電圧を加算して電
圧制御発振器に供給する位相同期回路において、
前記スイープ電圧発生器は、クロツク信号を発生
するクロツク発生器と、このクロツク信号を計数
するアツプダウンカウンタと、このアツプダウン
カウンタの計数方向を制御するデイジタルコンパ
レータと、前記アツプダウンカウンタの出力を位
相同期時に通過させ、位相同期時にラツチするラ
ツチ回路と、このラツチ回路の出力をＤ／Ａ変換
して前記スイープ電圧とするＤ／Ａコンバータと
を備えることを特徴とする位相同期回路。 In a phase locked circuit that adds the sweep voltage from the sweep voltage generator to the phase error signal output from the phase detector and supplies it to the voltage controlled oscillator,
The sweep voltage generator includes a clock generator that generates a clock signal, an up-down counter that counts the clock signal, a digital comparator that controls the counting direction of the up-down counter, and a phase difference between the output of the up-down counter. 1. A phase synchronized circuit comprising: a latch circuit that passes through during synchronization and latches during phase synchronization; and a D/A converter that converts the output of the latch circuit into a D/A converter to obtain the sweep voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP788389U JPH02100348U (en) | 1989-01-26 | 1989-01-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP788389U JPH02100348U (en) | 1989-01-26 | 1989-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02100348U true JPH02100348U (en) | 1990-08-09 |
Family
ID=31213281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP788389U Pending JPH02100348U (en) | 1989-01-26 | 1989-01-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02100348U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846510A (en) * | 1994-07-01 | 1996-02-16 | Sgs Thomson Microelettronica Spa | Fuzzy-controlled phase locking circuit and control method therefor |
-
1989
- 1989-01-26 JP JP788389U patent/JPH02100348U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0846510A (en) * | 1994-07-01 | 1996-02-16 | Sgs Thomson Microelettronica Spa | Fuzzy-controlled phase locking circuit and control method therefor |