JPS62167426U - - Google Patents
Info
- Publication number
- JPS62167426U JPS62167426U JP5424586U JP5424586U JPS62167426U JP S62167426 U JPS62167426 U JP S62167426U JP 5424586 U JP5424586 U JP 5424586U JP 5424586 U JP5424586 U JP 5424586U JP S62167426 U JPS62167426 U JP S62167426U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- intermediate frequency
- output
- comparator
- phase lock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Description
第１図は、本考案のＡＦＣ回路の一実施例のブ
ロツク回路図であり、第２図は、従来のＡＦＣ回
路を示すブロツク回路図である。
３：局部発振器、４：混合器、７：復調器、１
３，１９：ローパスフイルタ、１４：電圧比較器
、１５：基準発振器、１６：可変分周器、１７：
分周器、１８：位相比較器、２１：基準電圧。
FIG. 1 is a block circuit diagram of an embodiment of the AFC circuit of the present invention, and FIG. 2 is a block circuit diagram of a conventional AFC circuit. 3: Local oscillator, 4: Mixer, 7: Demodulator, 1
3, 19: Low pass filter, 14: Voltage comparator, 15: Reference oscillator, 16: Variable frequency divider, 17:
Frequency divider, 18: Phase comparator, 21: Reference voltage.
Claims (1)
発振器の出力を混合器に入力して受信信号を中間
周波数の中間周波信号に変換し、この中間周波信
号を復調器で検波し、この検波出力を電圧比較器
で任意に設定できる基準電圧と比較し、この電圧
比較器の出力を前記フエーズロツクループの基準
発振器に入力して基準発振周波数を制御すること
により前記中間周波数を制御することを特徴とす
る自動周波数制御回路。 The output of the local oscillator controlled by the phase lock loop is input to a mixer to convert the received signal into an intermediate frequency signal of an intermediate frequency, this intermediate frequency signal is detected by a demodulator, and the detected output is converted into a voltage. The intermediate frequency is controlled by comparing the voltage with a reference voltage that can be arbitrarily set using a comparator, and inputting the output of the voltage comparator to a reference oscillator of the phase lock loop to control the reference oscillation frequency. automatic frequency control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5424586U JPS62167426U (en) | 1986-04-11 | 1986-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5424586U JPS62167426U (en) | 1986-04-11 | 1986-04-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62167426U true JPS62167426U (en) | 1987-10-23 |
Family
ID=30881056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5424586U Pending JPS62167426U (en) | 1986-04-11 | 1986-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62167426U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55124320A (en) * | 1979-03-19 | 1980-09-25 | Pioneer Electronic Corp | Afc reference voltage correction circuit of receiver |
-
1986
- 1986-04-11 JP JP5424586U patent/JPS62167426U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55124320A (en) * | 1979-03-19 | 1980-09-25 | Pioneer Electronic Corp | Afc reference voltage correction circuit of receiver |