JPS6157718U - - Google Patents

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Publication number
JPS6157718U
JPS6157718U JP14263484U JP14263484U JPS6157718U JP S6157718 U JPS6157718 U JP S6157718U JP 14263484 U JP14263484 U JP 14263484U JP 14263484 U JP14263484 U JP 14263484U JP S6157718 U JPS6157718 U JP S6157718U
Authority
JP
Japan
Prior art keywords
voltage
controlled variable
variable oscillator
circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14263484U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14263484U priority Critical patent/JPS6157718U/ja
Publication of JPS6157718U publication Critical patent/JPS6157718U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案になるPLL回路の一実施例を
示す図、第2図は従来のPLL回路の一例を示す
図、第3図は本考案になるPLL回路の具体的回
路例を示す図である。 10…入力端子、11…位相比較器、12…演
算増幅器、13…直流基準電圧源、14…ボルテ
ージフオロア、15…電圧制御型可変発振器(V
CO)、16…出力端子。
FIG. 1 is a diagram showing an example of the PLL circuit according to the present invention, FIG. 2 is a diagram showing an example of a conventional PLL circuit, and FIG. 3 is a diagram showing a specific circuit example of the PLL circuit according to the present invention. It is. 10... Input terminal, 11... Phase comparator, 12... Operational amplifier, 13... DC reference voltage source, 14... Voltage follower, 15... Voltage controlled variable oscillator (V
CO), 16...Output terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力信号と電圧制御型可変発振器信号を位相比
較し、その位相差に応じた出力がローパスフイル
タを経由して前記電圧制御型可変発振器を制御し
、入力信号に同期させるPLL回路において、P
LL回路ループ内の制御を交流的に行ない、前記
電圧制御型可変発振器を制御する直流基準電圧源
を、前記電圧制御型可変発振器とともに集積回路
内に設けるよう構成したことを特徴とするPLL
回路。
In a PLL circuit that compares the phases of an input signal and a voltage-controlled variable oscillator signal, and outputs an output corresponding to the phase difference via a low-pass filter to control the voltage-controlled variable oscillator and synchronize it with the input signal,
A PLL characterized in that the LL circuit loop is controlled in an alternating current manner, and a DC reference voltage source for controlling the voltage-controlled variable oscillator is provided in an integrated circuit together with the voltage-controlled variable oscillator.
circuit.
JP14263484U 1984-09-20 1984-09-20 Pending JPS6157718U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14263484U JPS6157718U (en) 1984-09-20 1984-09-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14263484U JPS6157718U (en) 1984-09-20 1984-09-20

Publications (1)

Publication Number Publication Date
JPS6157718U true JPS6157718U (en) 1986-04-18

Family

ID=30700949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14263484U Pending JPS6157718U (en) 1984-09-20 1984-09-20

Country Status (1)

Country Link
JP (1) JPS6157718U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922446A (en) * 1982-07-29 1984-02-04 Mitsubishi Electric Corp Phase locked circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922446A (en) * 1982-07-29 1984-02-04 Mitsubishi Electric Corp Phase locked circuit

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