JPS63129335U - - Google Patents

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Publication number
JPS63129335U
JPS63129335U JP2132887U JP2132887U JPS63129335U JP S63129335 U JPS63129335 U JP S63129335U JP 2132887 U JP2132887 U JP 2132887U JP 2132887 U JP2132887 U JP 2132887U JP S63129335 U JPS63129335 U JP S63129335U
Authority
JP
Japan
Prior art keywords
phase
locked loop
loop circuit
circuit
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2132887U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2132887U priority Critical patent/JPS63129335U/ja
Publication of JPS63129335U publication Critical patent/JPS63129335U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るPLL回路の一実施例、
第2図は従来例である。 20:同調回路、9:可変分周器制御回路、1
0:DA変換器、11:時定数回路、21:スイ
ツチ、22:同調コイル、23:電圧制御可変容
量ダイオード、91:可変分周器制御信号、92
:同調回路制御信号、61:アンロツク対応信号
FIG. 1 shows an example of a PLL circuit according to the present invention.
FIG. 2 shows a conventional example. 20: Tuning circuit, 9: Variable frequency divider control circuit, 1
0: DA converter, 11: Time constant circuit, 21: Switch, 22: Tuning coil, 23: Voltage controlled variable capacitance diode, 91: Variable frequency divider control signal, 92
: Tuned circuit control signal, 61: Unlock compatible signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ミキサ段を含むフエーズロツクドループ回路に
おいて、上記ミキサ段の出力側に接続された同調
回路と、上記同調回路に使用される電圧制御可変
容量ダイオードと、上記フエーズロツクドループ
回路の可変分周器に与えられるデータ、またはそ
れに関連するデータを入力するDA変換器と、上
記DA変換器の出力を上記電圧制御可変容量ダイ
オードに供給する手段と、前記同調回路を上記フ
エーズロツクドループ回路から切り離すスイツチ
手段を有してなるフエーズロツクドループ回路。
In a phase-locked loop circuit including a mixer stage, a tuning circuit connected to the output side of the mixer stage, a voltage-controlled variable capacitance diode used in the tuning circuit, and a variable frequency divider of the phase-locked loop circuit. a DA converter for inputting data given to or data related thereto; means for supplying the output of the DA converter to the voltage-controlled variable capacitance diode; and a switch for separating the tuning circuit from the phase-locked loop circuit. A phase locked loop circuit comprising means.
JP2132887U 1987-02-18 1987-02-18 Pending JPS63129335U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2132887U JPS63129335U (en) 1987-02-18 1987-02-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2132887U JPS63129335U (en) 1987-02-18 1987-02-18

Publications (1)

Publication Number Publication Date
JPS63129335U true JPS63129335U (en) 1988-08-24

Family

ID=30817672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2132887U Pending JPS63129335U (en) 1987-02-18 1987-02-18

Country Status (1)

Country Link
JP (1) JPS63129335U (en)

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