JPH0449292B2 - - Google Patents

Info

Publication number
JPH0449292B2
JPH0449292B2 JP57224734A JP22473482A JPH0449292B2 JP H0449292 B2 JPH0449292 B2 JP H0449292B2 JP 57224734 A JP57224734 A JP 57224734A JP 22473482 A JP22473482 A JP 22473482A JP H0449292 B2 JPH0449292 B2 JP H0449292B2
Authority
JP
Japan
Prior art keywords
frequency
signal
frequency divider
division ratio
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57224734A
Other languages
Japanese (ja)
Other versions
JPS59114927A (en
Inventor
Eisuke Ooi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP57224734A priority Critical patent/JPS59114927A/en
Publication of JPS59114927A publication Critical patent/JPS59114927A/en
Publication of JPH0449292B2 publication Critical patent/JPH0449292B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Circuits Of Receivers In General (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、例えば広帯域に亘る受信が可能なラ
ジオ受信機の局部発振回路に適用して好適な可変
周波数発振回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a variable frequency oscillation circuit suitable for application to, for example, a local oscillation circuit of a radio receiver capable of receiving over a wide band.

背景技術とその問題点 例えばラジオ受信機において、広帯域に亘つて
安定した受信を可能にするためには、局部発振回
路として、広帯域に亘つて微少ステツプでその発
振周波数を安定に可変することができるものが必
要である。BACKGROUND TECHNOLOGY AND PROBLEMS For example, in a radio receiver, in order to enable stable reception over a wide band, the oscillation frequency can be stably varied in minute steps over a wide band as a local oscillation circuit. something is needed.

発明の目的 本発明は斯る点に鑑みてなされたもので、広帯
域に亘つて微少ステツプでその周波数を安定に可
変することができる可変周波数発振回路を提案せ
んとするものである。OBJECTS OF THE INVENTION The present invention has been made in view of the above points, and it is an object of the present invention to propose a variable frequency oscillation circuit that can stably vary its frequency in minute steps over a wide band.

発明の概要 本発明は上記目的を達成するため、第１の基準
信号が第１の分周器を有する第１のPLL回路に
供給され、第１の分周器の分周比倍に逓倍された
周波数信号のこの第１のPLL回路の出力が第２
の分周器を介して第２の基準信号に関連する信号
と混合され、この混合された信号が第３の分周器
を介して第４の分周器を有する第２のPLL回路
に供給され、第２の分周器の分周比倍に逓倍され
たこの第２のPLL回路より周波数信号が出力さ
れ、第２及び第４の分周器の分周比は等しくさ
れ、上記第３の分周器の分周比はそれと第１の基
準信号に対応する信号との積が最少可変ステツプ
となるように選ばれ、上記第１、第２及び第４の
分周器の分周比が制御されることで、周波数信号
の周波数が可変されるようにしたものである。Summary of the Invention In order to achieve the above object, the present invention provides a first reference signal that is supplied to a first PLL circuit having a first frequency divider, and is multiplied by the frequency division ratio of the first frequency divider. The output of this first PLL circuit of the frequency signal
is mixed with a signal related to the second reference signal through a frequency divider, and this mixed signal is fed through a third frequency divider to a second PLL circuit having a fourth frequency divider. The frequency signal is output from this second PLL circuit multiplied by the frequency division ratio of the second frequency divider, the frequency division ratios of the second and fourth frequency dividers are made equal, and the frequency signal is multiplied by the frequency division ratio of the second frequency divider. The division ratio of the frequency divider is selected such that the product of it and the signal corresponding to the first reference signal is the least variable step, and the division ratio of the first, second and fourth frequency dividers is controlled so that the frequency of the frequency signal is varied.

本発明はこのように構成され、広帯域に亘つて
微少ステツプでその周波数が安定に可変される周
波数信号を得ることができる。 The present invention is configured as described above, and it is possible to obtain a frequency signal whose frequency is stably varied in minute steps over a wide band.

実施例 以下、第１図を参照しながら本発明の一実施例
について説明しよう。Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG.

第１図において、端子１には、基準信号発振器
（図示せず）より周波数f1を有する基準信号S1が
供給される。この基準信号S1はPLL回路（フエ
ーズロツクドループ回路）２を構成する位相比較
器２ａに供給される。この位相比較器２ａからの
比較誤差信号は電圧制御型可変周波数発振器２ｂ
に制御電圧として供給される。そして、この発振
器２ｂからの発振信号は可変分周器２ｃにて分周
された後位相比較器２ａに供給される。この可変
分周器２ｃの分周比を１／N2とすると、発振器
２ｂからは、周波数N2×1の信号が得られる。 In FIG. 1, terminal 1 is supplied with a reference signal S 1 having a frequency f 1 from a reference signal oscillator (not shown). This reference signal S1 is supplied to a phase comparator 2a constituting a PLL circuit (phase locked loop circuit) 2. The comparison error signal from this phase comparator 2a is transmitted to the voltage controlled variable frequency oscillator 2b.
is supplied as a control voltage. The oscillation signal from the oscillator 2b is frequency-divided by the variable frequency divider 2c and then supplied to the phase comparator 2a. If the frequency division ratio of the variable frequency divider 2c is 1/ N2 , a signal with a frequency of N2 × 1 is obtained from the oscillator 2b.

この発振器２ｂからの信号は可変分周器３に供
給されて分周される。この可変分周器３の分周比
を１／N1２とするとこの可変分周器３からは周
波数N2×1×１／N1の信号が得られる。 The signal from this oscillator 2b is supplied to a variable frequency divider 3 and frequency-divided. If the frequency division ratio of this variable frequency divider 3 is 1/N 1 2, a signal with a frequency of N 2 × 1 × 1/N 1 is obtained from this variable frequency divider 3.

この可変分周器３からの信号はミキサ回路を構
成する掛算器４に供給される。また、端子５には
基準信号発振器（図示せず）により周波数2を有
する基準信号S2が供給され、これが掛算器４に供
給される。この掛算器４においては、可変分周器
３からの信号と基準信号S2とが掛算され、この掛
算器４からは周波数2＋N2×1×１／N1の信号が得 られる。 The signal from the variable frequency divider 3 is supplied to a multiplier 4 constituting a mixer circuit. Further, a reference signal S 2 having a frequency of 2 is supplied to the terminal 5 by a reference signal oscillator (not shown), and this is supplied to the multiplier 4 . In this multiplier 4, the signal from the variable frequency divider 3 is multiplied by the reference signal S2 , and a signal with a frequency of 2 + N2 × 1 ×1/ N1 is obtained from the multiplier 4.

この掛算器４からの信号は１／N3の分周比を
有する分周器６に供給され、この分周器６より周
波数（2＋N2×1×１／N1） １／N3）の信号が得られる。 The signal from this multiplier 4 is supplied to a frequency divider 6 having a division ratio of 1/N 3 , and from this frequency divider 6 the frequency is ( 2 + N 2 × 1 × 1/N 1 ) 1/N 3 ) signal is obtained.

この分周器６の分周比１／N3は、これと基準
信号S1の周波数1との積、即ち１／N3×f1が必要と する最小ステツプとなるように選ばれる。 The frequency division ratio 1/N 3 of this frequency divider 6 is chosen such that the product of this and the frequency 1 of the reference signal S 1 , ie 1/N 3 ×f 1, is the minimum step required.

この分周器６からの信号はPLL回路７を構成
する位相比較器７ａに供給される。この位相比較
器７ａからの比較誤差信号は電圧制御型可変周波
数発振器７ｂに制御電圧として供給される。この
発振器７ｂからの信号は可変分周器７ｃにて分周
された後位相比較器７ａに供給される。この可変
分周器７ｃの分周比は上述した可変分周器３の分
周比と等しく可変制御される。上述したように可
変分周器３の分周比を１／N1とすると、この可
変分周器７ｃの分周比も１／N1とされる。従つ
て、発振器７ｂからは、周波数（2＋N2×1×
１／N1）１／N3×N1の信号が得られ、これが周波数信 号Sputとして出力端子８に供給される。 The signal from this frequency divider 6 is supplied to a phase comparator 7a forming a PLL circuit 7. The comparison error signal from the phase comparator 7a is supplied as a control voltage to the voltage controlled variable frequency oscillator 7b. The signal from this oscillator 7b is frequency-divided by a variable frequency divider 7c and then supplied to a phase comparator 7a. The frequency division ratio of this variable frequency divider 7c is variably controlled to be equal to the frequency division ratio of the variable frequency divider 3 described above. As mentioned above, when the frequency division ratio of the variable frequency divider 3 is set to 1/ N1 , the frequency division ratio of the variable frequency divider 7c is also set to 1/ N1 . Therefore, from the oscillator 7b, the frequency ( 2 +N 2 × 1 ×
A signal of 1/N 1 ) 1/N 3 ×N 1 is obtained, and this is supplied to the output terminal 8 as a frequency signal Sput .

本例はこのように構成され、上述したように出
力端子８には周波数putが put＝（2＋N2×1×１／N1） １／N3×N1 ……(1) と表わせる周波数信号Sputが得られる。 This example is configured in this way, and as mentioned above, the frequency put at the output terminal 8 can be expressed as put = ( 2 + N 2 × 1 × 1/N 1 ) 1/N 3 × N 1 ...(1) A frequency signal S put is obtained.

ここで、例えば基準信号S1の周波数1が5kHz、
基準信号S2の周波数2が50MHz、そして分周器６
の分周比１／N3が１／50とされれば、(1)式は、 put＝（50MHz＋N2×5kHz×１／N1） ×１／50×N1 ＝1MHz×N1＋100Hz×N2 ……(2) と表わせる。この場合、周波数putは、可変分周
器２ｃの分周比１／N2が制御されることで、100
Hz（5kHz×１／50）の微少可変ステツプで可変させ られ、また可変分周器３及び７ｃの分周比１／
N1が制御されることで1MHzのステツプで大きく
可変させられる。 Here, for example, if the frequency 1 of the reference signal S 1 is 5kHz,
Frequency 2 of reference signal S 2 is 50MHz, and frequency divider 6
If the frequency division ratio 1/N 3 is 1/50, then formula (1) is put = (50MHz + N 2 × 5kHz × 1/N 1 ) × 1/50 × N 1 = 1MHz × N 1 + 100Hz × It can be expressed as N 2 ……(2). In this case, the frequency put is 100 by controlling the frequency division ratio 1/N 2 of the variable frequency divider 2c.
It can be varied in minute variable steps of Hz (5kHz x 1/50), and the frequency division ratio of variable frequency dividers 3 and 7c is 1/50.
By controlling N1 , it can be greatly varied in 1MHz steps.

このように本例によれば、出力端子８には、広
帯域に亘つて微少ステツプ、例えば100Hzでその
周波数putが安定に可変される周波数信号Sputを
得ることができる。 As described above, according to this example, it is possible to obtain at the output terminal 8 the frequency signal S put whose frequency put is stably varied in minute steps over a wide band, for example, 100 Hz.

次に、第２図は本発明の他の実施例を示すもの
である。この第２図において第１図と対応する部
分には同一符号を付し、その詳細説明は省略す
る。 Next, FIG. 2 shows another embodiment of the present invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

この第２図において、可変分周器３からの信号
はミキサ回路を構成するPLL回路９の位相比較
器９ａに供給される。この位相比較器９ａからの
比較誤差信号は電圧制御型可変周波数発振器９ｂ
に制御電圧として供給される。そして、この発振
器９ｂからの発振信号は掛算器９ｃに供給され
る。またこの掛算器９ｃには端子５より基準信号
S2が供給される。この掛算器９ｃからの信号は
１／N4の分周比を有する分周器９ｄで分周され
た後位相比較器９ａに供給される。従つて、発振
器９ｂからは周波数2−1×N4×N2×１／N1の信 号が得られる。この発振器９ｂからの信号は１／
N3′の分周比を有する分周器１０に供給され、こ
の分周器１０より周波数（2−1×N4×N2×
１／N1）１／N3′の信号が得られる。 In FIG. 2, the signal from the variable frequency divider 3 is supplied to a phase comparator 9a of a PLL circuit 9 constituting a mixer circuit. The comparison error signal from this phase comparator 9a is transmitted to a voltage controlled variable frequency oscillator 9b.
is supplied as a control voltage. The oscillation signal from this oscillator 9b is then supplied to a multiplier 9c. Also, this multiplier 9c receives a reference signal from terminal 5.
S2 is supplied. The signal from the multiplier 9c is frequency-divided by a frequency divider 9d having a frequency division ratio of 1/ N4 , and then supplied to the phase comparator 9a. Therefore, a signal with a frequency of 2 −1 ×N 4 ×N 2 ×1/N 1 is obtained from the oscillator 9b. The signal from this oscillator 9b is 1/
It is supplied to a frequency divider 10 having a division ratio of N 3 ', and from this frequency divider 10 the frequency ( 2 − 1 ×N 4 ×N 2 ×
A signal of 1/N 1 )1/N 3 ' is obtained.

この分周器１０の分周比１／N3′は、これと基
準信号S1の周波数1と、分周器９ｄの分周比１／
N4の逆数との積、即ち１／N3′×1×N4が必要とす る最小ステツプとなるように選ばれる。 The frequency division ratio 1/N 3 ' of this frequency divider 10 is the frequency division ratio 1/N 3 ' of this frequency divider 10, the frequency 1 of the reference signal S 1 , and the frequency division ratio 1/N 3 ' of the frequency divider 9d.
The product with the reciprocal of N 4 , ie 1/N 3 '× 1 ×N 4 , is chosen to be the minimum step required.

この分周器１０からの信号はPLL回路７を構
成する位相比較器７ａに供給される。従つて、発
振器７ｂからは、周波数（2−1×N4×N2×
１／N1）１／N3′×N1の信号が得られ、これが出力端 子８に供給される。 The signal from this frequency divider 10 is supplied to a phase comparator 7a forming a PLL circuit 7. Therefore, from the oscillator 7b, the frequency ( 2 − 1 ×N 4 ×N 2 ×
A signal of 1/N 1 ) 1/N 3 '×N 1 is obtained and supplied to the output terminal 8.

第２図例はこのように構成され、出力端子８に
は周波数putが、 put＝（2−1×N4×N2 ×１／N1）１／N3′×N1 ……(3) と表わせる周波数信号Sputが得られる。 The example in Fig. 2 is configured like this, and the output terminal 8 has the frequency put , put = ( 2 - 1 ×N 4 ×N 2 × 1/N 1 ) 1/N 3 ′ × N 1 ……(3 ) A frequency signal S put can be obtained.

ここで、例えば周波数putを55MHz〜300MHz程
度に可変させる場合には、基準信号S1の周波数1
が5kHz、基準信号S2の周波数2が56.3MHz、分周
器９ｄの分周比１／N4が１／４、そして分周器
１０の分周比１／N3′が１／200とされる。この
場合、上述(3)式は、 put＝56.3MHz−5kHz×４×N2×１／N1） ×１／200×N1 ＝281.5kHz×N1−100Hz×N2 ……(4) と表わせる。この周波数putは、可変分周器２ｃ
の分周比１／N2が制御されることで、100Hz（5k
Hz×４×１／200）の微少可変ステツプで可変させら れ、また可変分周器３及び７ｃの分周比１／N1
が制御されることで、281.5kHzのステツプで大き
く可変させられる。 Here, for example, when changing the frequency put from about 55MHz to 300MHz, the frequency 1 of the reference signal S1
is 5kHz, the frequency 2 of the reference signal S2 is 56.3MHz, the division ratio 1/N 4 of the frequency divider 9d is 1/4, and the division ratio 1/N 3 ' of the frequency divider 10 is 1/200. be done. In this case, the above equation (3) is put = 56.3MHz - 5kHz x 4 x N 2 x 1/N 1 ) x 1/200 x N 1 = 281.5kHz x N 1 -100Hz x N 2 ...(4) It can be expressed as This frequency put is the variable frequency divider 2c
By controlling the frequency division ratio 1/N 2 of 100Hz (5k
The frequency division ratio of variable frequency dividers 3 and 7c is 1/N 1.
By controlling the frequency, it can be greatly varied in steps of 281.5kHz.

このように第２図例においても、第１図例同様
の作用効果を得ることができる。 In this way, in the example shown in FIG. 2, the same effects as in the example shown in FIG. 1 can be obtained.

発明の効果 以上述べた実施例からも明らかなように本発明
によれば、広帯域に亘つて微少ステツプでその周
波数が安定に可変される周波数信号を得ることが
できる。従つて、広帯域に亘る受信が可能なラジ
オ受信機の局部発振回路に適用して好適なものと
なる。Effects of the Invention As is clear from the embodiments described above, according to the present invention, it is possible to obtain a frequency signal whose frequency is stably varied in minute steps over a wide band. Therefore, it is suitable for application to a local oscillation circuit of a radio receiver capable of receiving over a wide band.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す構成図、第２
図は本発明の他の実施例を示す構成図である。 ２及び７は夫々PLL回路、２ｃ，３及び７ｃ
は夫々可変分周器、６は分周器、８は出力端子で
ある。 FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
The figure is a configuration diagram showing another embodiment of the present invention. 2 and 7 are PLL circuits, 2c, 3 and 7c, respectively.
are variable frequency dividers, 6 is a frequency divider, and 8 is an output terminal.

Claims (1)

【特許請求の範囲】[Claims] １ 第１の基準信号が第１の分周器を有する第１
のPLL回路に供給され、上記第１の分周器の分
周比倍に逓倍された周波数信号の該第１のPLL
回路の出力が第２の分周器を介して第２の基準信
号に関連する信号と混合され、この混合された信
号が第３の分周器を介して第４の分周器を有する
第２のPLL回路に供給され、上記第２の分周器
の分周比倍に逓倍された該第２のPLL回路より
周波数信号が出力され、上記第２及び第４の分周
器の分周比は等しくされ、上記第３の分周器の分
周比はそれと上記第１の基準信号に対応する信号
との積が最小可変ステツプとなるように選ばれ、
上記第１、第２及び第４の分周器の分周比が制御
されることで、上記周波数信号の周波数が可変さ
れることを特徴とする可変周波数発振回路。1 The first reference signal has a first frequency divider.
of the frequency signal supplied to the PLL circuit of the first PLL circuit and multiplied by the frequency division ratio of the first frequency divider.
The output of the circuit is mixed through a second frequency divider with a signal related to the second reference signal, and this mixed signal is mixed through a third frequency divider with a fourth frequency divider. The frequency signal is supplied to the second PLL circuit, and the frequency signal is multiplied by the frequency division ratio of the second frequency divider. the ratios are equal, and the division ratio of the third frequency divider is chosen such that the product of it and the signal corresponding to the first reference signal is the smallest variable step;
A variable frequency oscillation circuit characterized in that the frequency of the frequency signal is varied by controlling the frequency division ratios of the first, second, and fourth frequency dividers.
JP57224734A 1982-12-21 1982-12-21 Oscillating circuit of variable frequency Granted JPS59114927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57224734A JPS59114927A (en) 1982-12-21 1982-12-21 Oscillating circuit of variable frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57224734A JPS59114927A (en) 1982-12-21 1982-12-21 Oscillating circuit of variable frequency

Publications (2)

Publication Number Publication Date
JPS59114927A JPS59114927A (en) 1984-07-03
JPH0449292B2 true JPH0449292B2 (en) 1992-08-11

Family

ID=16818400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57224734A Granted JPS59114927A (en) 1982-12-21 1982-12-21 Oscillating circuit of variable frequency

Country Status (1)

Country Link
JP (1) JPS59114927A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02213225A (en) * 1989-02-13 1990-08-24 Nec Corp Variable frequency synthesis circuit
JPH0349320A (en) * 1989-07-17 1991-03-04 Nec Corp Frequency synthesizer

Also Published As

Publication number Publication date
JPS59114927A (en) 1984-07-03

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