JPS59114927A - Oscillating circuit of variable frequency - Google Patents

Abstract

PURPOSE:To obtain a variable frequency suitable for a local oscillator of a radio receiver through a simple constitution by varying stably a frequency into a variable frequency in minute steps over a wide range of band. CONSTITUTION:A reference signal S1 of a frequency f1 is applied to an input terminal 1 from a reference signal oscillator and then to a phase comparator 2a of a PLL circuit 2. The phase difference signal fed from the comparator 2a is applied to a VCO2b as a control signal. A variable divider 2c of the circuit 2 converts the output signal of the circuit 2 into a signal of a frequency N2Xf1 and supplies it to a 1/N divider 3. The frequency of the output signal of the divider 3 is set at N2Xf1X1/N1 and supplied to a multiplier 4 to be mixed with a reference signal S2 of a frequency f2 which is given from the reference signal oscillator through a terminal 5. Furthermore the output of the multiplier 4 is divided into 1/N3 by a 1/N3 divider 6 and supplied to a phase comparator 7a of a PLL circuit 7. Then the frequency of the output signal is set at (f2+N2X f1X1/N1)1/N3XN1 by a variable frequency divider 7c and a VCO7b of the circuit 7 and then delivered to an output terminal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a variable frequency oscillation circuit suitable for application to, for example, a local oscillation circuit of a radio receiver capable of receiving over a wide band. In order to enable stable reception over a wide band in a radio receiver, a local oscillation circuit that can stably vary its oscillation frequency in minute steps over a wide band is required.

OBJECTS OF THE INVENTION The present invention has been made in view of the above, and an object thereof is to propose a variable frequency oscillation circuit that can stably vary its frequency in minute steps over a wide band.

SUMMARY OF THE INVENTION In order to achieve the above objects, the present invention provides a first reference signal that is supplied to a $1 PLL circuit having a first divider, and the output of the first PLL circuit is supplied to a second frequency divider. The second
This mixed signal is supplied to a 20th PLL circuit having a fourth frequency divider via a $3 frequency divider, and a frequency signal is output from this second PLL circuit. , the frequency division ratios of the second and fourth dividers are made equal, and the frequency division ratio of the third divider is set such that the product of this and the signal corresponding to the first reference signal is the minimum variable step. The frequency of the frequency signal is varied by controlling the division ratios of the first, second, and fortieth frequency dividers.

With this configuration, the present invention can obtain a frequency signal whose frequency is stably varied in minute steps over a wide band.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

In FIG. 1, a terminal (1) K is supplied with a reference signal Sl having a frequency f1 from a reference signal oscillator (not shown). This reference signal S□ is supplied to a phase comparator (2a) forming a PLL circuit (phase locked loop circuit) (2). The comparison error signal from this phase comparator (2a) is supplied as a K control voltage to a voltage controlled variable frequency oscillator (2b). The oscillation signal from this oscillator (2b) is frequency-divided by a variable divider (2C) and then supplied to a phase comparator (2a). From this point on, frequency N2×
A signal from f-engine can be obtained.

The signal from this oscillator (2b) is supplied to a variable frequency divider (3) and frequency-divided. Frequency division ratio of this variable division divider (3) The signal from this variable division divider (3) is supplied to a multiplier (4) constituting a mixer circuit. Further, the terminal (5) K is supplied with a reference signal S2 having a frequency f2 from a reference signal oscillator (not shown), and this is supplied to the multiplier (4).

In this multiplier (4), the signal from the variable frequency divider (3) and the reference signal S2 are multiplied by 753, and the result is expressed as follows.

The signal is supplied to a frequency divider (6), which is selected such that the frequency is a small step.

The signal from this frequency divider (6) is supplied to a phase comparator (7a) forming a PLL circuit (7). The comparison error signal from this phase comparator (7a) is supplied as a control voltage to a voltage controlled variable frequency oscillator (7b). The signal from this oscillator (7b) is frequency-divided by a variable frequency divider (7C) and then supplied to a phase comparator (7a). The frequency division ratio of this variable frequency divider (7C) is variably controlled to be equal to the division ratio of the variable frequency divider (3) described above. Power terminal (8) as mentioned above
It is supplied to ゛.

This example is configured in this way, and the output terminal (
8) has a frequency f. A frequency signal S where ut can be expressed as . ut is obtained.

Here, for example, if the frequency f□ of the reference signal S□ is 5kHz2,
=IMH2XNl+100H2XN2...
It can be expressed as (2). In this case, the frequency fout is controlled by the variable amount and is largely varied in steps of IMH2.

As described above, according to this example, the output terminal (8) receives a frequency signal S whose frequency fout is stably varied in minute steps, for example, 100H2, over a wide band. You can get ut.

Next, FIG. 2 shows another embodiment of the present invention and is essential ◇
In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 2, the signal from the variable frequency divider (3) is transmitted to the phase comparator (9) of the PLL circuit (9) constituting the mixer circuit.
a). The comparison error signal from the phase comparator (9a) is supplied as a control voltage to the voltage controlled variable frequency oscillator (9b). The oscillation signal from this oscillator (9b) is then supplied to the Hino-1 calculator (9C).

Also, this multiplier (9C) is connected to the terminal (5) and the reference signal S.
After being frequency-divided by a frequency divider (9d) having a frequency division ratio of 2, the signal is supplied to a phase comparator (9a). Therefore, the oscillator (9b)
The signal is supplied to a frequency divider (10), and the frequency step is selected from this frequency divider UO+.

The signal from this branching unit 001 is supplied to a phase comparator (7a) forming a PLL circuit (7). The signal of the oscillator Nl is thus obtained and is supplied to the output terminal (8).

The example in FIG. 2 is constructed in this way, and the output terminal (8) has a frequency fout, and a frequency signal S which can be expressed as follows. ut is obtained.

Here, for example, set the frequency foLIt to 55MH2~3oo
When changing the frequency to about MH2, the frequency f1 of the reference signal s1 is 5 kHz, the frequency f2 of the reference signal 82 is 56.3 MH2, = 281.5 kHz2xN1-100H2xN2
It can be expressed as -・------f41. This frequency f
. ut becomes 281.5 by using the variable frequency divider (2c).
It can be greatly varied in kHz steps.

In this way, the example shown in FIG. 2 can also achieve the same effects as the example shown in FIG.

Effects of the Invention As is clear from the embodiments described above, according to the present invention, it is possible to obtain a frequency signal whose frequency is stably varied in minute steps over a wide band. Therefore, reception over a wide band is possible. The present invention is suitable for application to a local oscillation circuit of a radio receiver.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. (2) and (7) are PLL circuits, (2C) f3+ and (7c) are variable frequency dividers, (6) are frequency dividers, (8)
is the output terminal.

Claims (1)

[Claims] a first reference signal is supplied to a first PLL circuit having a first frequency divider, the output of the first PLL circuit is mixed with a second reference signal through a 20th frequency divider; This mixed signal is supplied to a 20th PLL circuit having a fourth frequency divider via a third frequency divider, and a frequency signal is output from this second PLL circuit. The division ratios of the frequency dividers are made equal, and the division ratio of the third frequency divider is chosen such that the product of it and the signal corresponding to the first reference signal is the minimum variable step; 4. A variable frequency oscillation circuit characterized in that the frequency of the frequency signal is varied by controlling the division ratios of the second and fourth frequency dividers.