GB2098419A - Electrical frequency adjusting arrangements - Google Patents
Electrical frequency adjusting arrangements Download PDFInfo
- Publication number
- GB2098419A GB2098419A GB8114039A GB8114039A GB2098419A GB 2098419 A GB2098419 A GB 2098419A GB 8114039 A GB8114039 A GB 8114039A GB 8114039 A GB8114039 A GB 8114039A GB 2098419 A GB2098419 A GB 2098419A
- Authority
- GB
- United Kingdom
- Prior art keywords
- output
- frequency
- phase
- mixer
- vco
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 235000014366 other mixer Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
A circuit arrangement for producing an output Fo is in the form of two phase-locked loops 5 and 6 fed with a common reference frequency Fr. In order to provide very fast lock- up, Fr is high, 2.5 MHz say. The use of the two loops, interconnected via divider 24 and mixer 10, enables Fo to be adjusted in relatively small steps in spite of the high value of Fr. Mixer 10 is in the form of a quadrature demodulator (Fig. 2) and is therefore able to select the lower sideband output without the need for a filter, thus avoiding the problems which would be caused, if such a filter were used, by the closeness of the two sidebands at the frequency used. <IMAGE>
Description
SPECIFICATION
Improvements in and relating to electrical frequency adjusting arrangements
The invention relates to electrical circuit arrangements and more particularly to electrical circuit arrangements for adjusting an output frequency. Such circuit arrangements may form part of a frequency synthesizer.
Various novel features of the invention will be apparent from the following description, given by way of example only, of a frequency adjusting circuit embodying the invention, and which may be part of a frequency synthesizer, reference being made to the accompanying diagrammatic drawings in which:
Figure 1 is a block circuit diagram of the circuit; and
Figure 2 is a block circuit diagram of a mixer used in the circuit of Figure 1.
More specifically to be described below is an electrical circuit arrangement for producing an adjustable frequency output, comprising two phase-locked loops each fed with a relatively high reference frequency, each phase-locked loop incorporating a respective adjustable oscillator and a respective phase comparator connected to compare the reference frequency with a control frequency derived from the oscillator via an adjustable divider, the output frequency (or an output derived therefrom) of the oscillator of one of the loops being mixed in a mixer with the output frequency (or an output derived therefrom) of the oscillator of the other loop so that a particular one of the two sideband outputs produces the control frequency of that loop via the respective divider, the said mixer being an arrangement which produces a single sideband output directly without the use of a filter.For example, the arrangement may be one which produces a single sideband output directly by combination of signals having a predetermined phase difference, such as, for example, by combining the product of the two mixer inputs with the product of the two mixer inputs after they have been quadrature-shifted as in a quadrature demodulator.
The use of a high value reference frequency for each loop is advantageous because it reduces lock-up time, and the use of such an arrangement as the mixer removes the need for a filter to select the said particular sideband.
Advantageously, each phase-locked loop is fed with the same reference frequency.
Preferably, the output of the adjustable oscillator of the said one phase-locked loop is fed toithe mixer through a further divider.
In a more specific sense, there will be described in more detail below an electrical circuit arrangement comprising first and second phaselocked loops fed with a common reference frequency, the first loop comprising a first voltage controlled oscillator (VCO) feeding its output through a first divider to provide one input of a first phase comparator whose other input is the
reference frequency, whereby the phase
comparator produces a control output which
adjusts the VCO in a sense so as to reduce the
phase difference towards zero, the second phase
locked loop comprising a second VCO feeding its
output into one input of a quadrature
demodulator whose other input receives the
output of the first VCO via a fixed divider, the
difference frequency output of the quadrature
demodulator being fed through a second
adjustable divider to one input of a second phase
comparator whose other input is the reference
frequency, whereby the second phase comparator
produces a control output in response to any
phase difference which it detects, this control
signal adjusting the second VCO in a direction tending to reduce the said difference to zero, the
output of the second VCO constituting the output frequency of the circuit arrangement.
The foregoing are exemplary of and not
exhaustive of the various features of the circuit
now to be more specifically described.
The circuit arrangement is in the form of two interconnected phase-locked loops, loop 5 and
loop 6. Loop 5 includes a voltage controlled
oscillator (VCO) 8 which produces the output frequency F0 of the circuit arrangement. The
output F0 is also fed into a mixer 10 (to be
described below). The mixer output F1 is fed into a
divider 12 having an adjustable division factor of
N1 and the output F1/N1 provides one input of a
phase comparator 14 whose other input receives
a reference frequency F, on a line 1 6.
The phase comparator 14 therefore detects
any phase difference between the two inputs and
produces a control signal on line 1 8 which adjusts
the output frequency F0 of the VCO 8 in such a
direction as to bring the two inputs to the phase
comparator 14 into phase equality.
The second loop 6 includes a VCO 22 whose
output frequency F2 is fed through a fixed divider
24 (having a division factor of, say, 100), and the
resultant output, F3, is fed to the second input of
the mixer 10 on a line 26. The output F2 of the
VCO 22 is also fed through a divider 28, having
an adjustable division factor of N2, and the
resultant output, FN2, feeds one input of a phase
comparator 30. The second input of the phase
comparator 30 is fed with the reference signal F,.
The phase comparator 30 produces a control
signal on a line 22 in dependence on the phase
difference, if any, between its two inputs, and this
control signal adjusts the frequency F2 of the VCO
22 so as to reduce the phase difference to zero.
Mixer 10, to be described in more detail below,
is arranged so that its output, F1, is the lower
sideband output.
Therefore, from loop 5, F1/M1=F, (1)
but, F1=F0-F3 (2)
and F3=F1 00 (3)
Therefore, substituting Equations (2) and (3) in Equation (1),
(FoF2/1 OO/N1=F, (4) In loop 6, F2/N2=F, (5)
Substituting Equation (5) in Equation (4), (F0-N2 F,/1 00)/N1=F" or Fo-N2 . F/i 00=N1 Fr.
Therefore, Fo=N1 +N2. F,/100 (6)
Equation (6) therefore shows how the output frequency is related to the reference frequency F, and may be varied in steps by unit adjustments of the division factors N1 and N2, each such unit adjustment of N2 having 1 OOth of the effect of a unit adjustment of N1.
In certain applications, it is highly desirable that such a circuit arrangement can lock very rapidly indeed to a new frequency when one or other, or both, of the dividers is adjusted. For example, the circuit arrangement described may be controlling the tuning of a radio receiver which is employed in monitoring transmissions at a number of different wavelengths.
The speed at which the circuit will lock up to a new frequency is a function of the value of the reference frequency Fr, being of the order of, say, 30 oscillations of the reference frequency.
Therefore, for fast lock-up (e.g. 12 sec), the reference frequency F, needs to be as high as is practicable, 2.5 MHz, say. If the circuit
arrangement embodies only a single phase-locked loop, then it would only be possible to adjust the output frequency F0 in very large steps, each equal to the value of F,. The double arrangement
of loops shown avoids this disadvantage. Equation (6) shows that the minimum step size is now reduced by a factor of 100. However, the double loop arrangement shown involves a mixer, the mixer 10, for combining the outputs of the two
VCOs. Means must therefore be provided to select one, only, of the two sideband outputs of the mixer.Because the frequency on line 26 is very much smailer than F,, the sidebands only vary slightly from the carrier frequency F,, and this makes it not feasible to use a conventional mixer followed by a filter to select the upper or lower sidebands-because the bandwidth of the filter would have to be very critical in order to be able to select only the correct sideband and this bandwidth would of course vary according to the settings of the circuit.
In accordance with a feature of the circuit, therefore, the mixer 10 is in the form of a quadrature demodulator. The use of a quadrature demodulator as the mixer is highiy advantageous because it selects the lower sideband output inherently, that is, without the use of the filter.
Figure 2 shows the circuit diagram of a suitable arrangement of quadrature demodulator.
The signal F0 is fed into one input of a mixing circuit 40 whose second-input receives the signal
F3. A second mixing circuit 42 receives F0 and F3 after they have been phase-shifted by 900 in phase-shifting circuits 44 and 45. Each mixing circuit produces upper and lower sidebands and these are summed in an adder 46 to produce the required lower sideband output F1=F0-F3. The upper sidebands are cancelled at the output of the adder.
Let FO=sin wot and
F3=sin co3t The output of mixer 40 is therefore
F4=sin wot sin 03t and the output of mixer 42 is therefore Fs=sin (o,t+900) > sin (a)3t+900) =cos wot cos w3t.
Thus the output of adder 46 is given by x where
x=cos wot cos w3t+sin wot sin w3t cos (co0+w3)t -F0-F3=F1 Therefore only the lower sideband is present.
In general, the quadrature networks (lag or lead) can be placed in other mixer inputs or outputs, with similar results using an adding or subtracting combining circuit as required (so as to produce only the lower or the upper sideband as required).
Claims (7)
1. An electrical circuit arrangement for producing an adjustable frequency output comprising two phase-locked loops each fed with a relatively high reference frequency, each phaseiocked loop incorporating a respective adjustable oscillator and a respective phase comparator connected to compare the reference frequency with a control frequency derived from the oscillator via an adjustable divider, the output frequency (or an output derived therefrom) of the oscillator of one of the loops being mixed in a mixer with the output frequency (or an output derived therefrom) of the oscillator of the other loop so that a particular one of the two sideband outputs produces the control frequency of that loop via the respective divider, the said mixer being an arrangement which produces a single sideband output directly without the use of a filter.
2. An arrangement according to claim 1, in which the mixer produces a single sideband output directly by combination of signals having a ,predetermined phase difference.
3. An arrangement according to claim 2, in which the mixer produces the single sideband
output by combining the product of the two mixer
inputs with the product of the two mixer inputs
after they have been quadrature-shifted as in a
quadrature demodulator.
4. An arrangement according to any preceding claim, in which each phase-locked loop is fed with the same reference frequency.
5. An arrangement according to any preceding claim, in which the output of the adjustable oscillator of the said one phase-locked loop is fed to the mixer through a further divider.
6. An electrical circuit arrangement,
comprising first and second phase-locked loops fed with a common reference frequency, the first
loop comprising a first voltage controlled
oscillator (VCO) feeding its output through a first divider to provide one input of a first phase comparator whose other input is the reference frequency, whereby the phase comparator produces a control output which adjusts the VCO in a sense so as to reduce the phase difference towards zero, the second phase-locked loop comprising a second VCO feeding its output into one input of a quadrature demodulator whose other input receives the output of the first VCO via a fixed divider, the difference frequency output of the quadrature demodulator being fed through a second adjustable divider to one input of a second phase comparator whose other input is the reference frequency, whereby the second phase comparator produces a control output in response to any phase difference which it detects, this control signal adjusting the second VCO in a direction tending to reduce the said difference to zero, the output of the second VCO constituting the output frequency of the circuit arrangement.
7. An electrical circuit arrangement substantially as described with reference to the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8114039A GB2098419A (en) | 1981-05-07 | 1981-05-07 | Electrical frequency adjusting arrangements |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8114039A GB2098419A (en) | 1981-05-07 | 1981-05-07 | Electrical frequency adjusting arrangements |
Publications (1)
Publication Number | Publication Date |
---|---|
GB2098419A true GB2098419A (en) | 1982-11-17 |
Family
ID=10521650
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8114039A Withdrawn GB2098419A (en) | 1981-05-07 | 1981-05-07 | Electrical frequency adjusting arrangements |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2098419A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2135544A (en) * | 1983-02-23 | 1984-08-30 | Mcmichael Ltd | Radio communications systems |
EP0409127A2 (en) * | 1989-07-17 | 1991-01-23 | Nec Corporation | Phase-locked loop type frequency synthesizer having improved loop response |
GB2245441A (en) * | 1990-06-13 | 1992-01-02 | Motorola Israel Ltd | Fine-tune frequency adjuster |
EP0593642A1 (en) * | 1991-07-08 | 1994-04-27 | Motorola, Inc. | Multi-loop synthesizer |
GB2354383A (en) * | 1999-09-17 | 2001-03-21 | Sony Uk Ltd | Dual loop phase-locked loop |
US6647247B2 (en) | 1994-12-15 | 2003-11-11 | Nokia Mobile Phones Ltd. | Method for producing transmission frequency |
EP1383244A1 (en) * | 2002-07-16 | 2004-01-21 | Hitachi, Ltd. | Multiple PLL oscillator and multiple CW radar using such an oscillator |
-
1981
- 1981-05-07 GB GB8114039A patent/GB2098419A/en not_active Withdrawn
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2135544A (en) * | 1983-02-23 | 1984-08-30 | Mcmichael Ltd | Radio communications systems |
EP0409127A2 (en) * | 1989-07-17 | 1991-01-23 | Nec Corporation | Phase-locked loop type frequency synthesizer having improved loop response |
EP0409127A3 (en) * | 1989-07-17 | 1991-04-10 | Nec Corporation | Phase-locked loop type frequency synthesizer having improved loop response |
GB2245441A (en) * | 1990-06-13 | 1992-01-02 | Motorola Israel Ltd | Fine-tune frequency adjuster |
GB2245441B (en) * | 1990-06-13 | 1994-04-06 | Motorola Israel Ltd | Fine-tune frequency adjustor |
EP0593642A1 (en) * | 1991-07-08 | 1994-04-27 | Motorola, Inc. | Multi-loop synthesizer |
EP0593642A4 (en) * | 1991-07-08 | 1994-06-15 | Motorola Inc | Multi-loop synthesizer |
US6647247B2 (en) | 1994-12-15 | 2003-11-11 | Nokia Mobile Phones Ltd. | Method for producing transmission frequency |
GB2354383A (en) * | 1999-09-17 | 2001-03-21 | Sony Uk Ltd | Dual loop phase-locked loop |
EP1383244A1 (en) * | 2002-07-16 | 2004-01-21 | Hitachi, Ltd. | Multiple PLL oscillator and multiple CW radar using such an oscillator |
US6747488B2 (en) | 2002-07-16 | 2004-06-08 | Hitachi, Ltd. | Multiple PLL oscillator and multiple CW radar used therefore |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |