JP2000270300A - Pll circuit and video signal processing circuit using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output a picture with high quality by eliminating occurrence of a distorted image at the start of a display picture and coping with jitter. SOLUTION: A PLL circuit 12 (14) includes a synchronizing separator circuit 50 and an oscillated frequency of a VCO 56 is controlled by a comparator 52, an LPF 56, an oscillation circuit (VCO) 56 and a frequency divider 58 on the basis of a H-sync outputted from the synchronizing separator circuit 50. Furthermore, the H-sync is given to a terminal D of a DQ-FF 54 and an output signal (reference signal) of the frequency divider 58 is given to a clock(CLK) terminal of the DQ-FF 54. The DQ-FF 54 discriminates a lock state or an unlock state of the PLL circuit 12 (14) on the basis of the two signals. When the unlock state is discriminated, a high level signal is outputted from the terminal D to close a switch SW 1. That is, the time constant is set smaller in the unlock state that in the lock state and the lock state is set in a short time, no bent head picture is produced on a screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit for controlling an oscillation frequency based on, for example, a horizontal synchronizing signal.

[0002]

2. Description of the Related Art In a conventional PLL circuit 1 shown in FIG. 5, an oscillator (VCO) 3 oscillates according to a control voltage from a low-pass filter (LPF) 2 and synchronizes with a horizontal synchronization signal (H-sync) from the VCO 3. For example, an oscillation signal multiplied by 1820 times is output. The oscillation signal output from the VCO 3 is supplied to a signal processing circuit (not shown) and a frequency divider 5 at a subsequent stage. In the frequency divider 4, the oscillation signal is divided into 1/1820 by the counter 4 a and the decoder 4 b, and the divided signal (divided signal) is supplied to the comparator 5. The comparator 5 receives the H-sync output from the sync separation circuit 6. That is, the comparator 5 compares the two signals and outputs a high-level or low-level signal based on the comparison result. The LPF 2 generates a control voltage based on the output signal from the comparator 5, and the VCO 3 controls the oscillation frequency according to the control voltage.

[0003]

However, in this prior art, once the PLL circuit 1 is completely unlocked, the output of the comparator 5 is saturated at a high level or a low level, and the VCO 3 outputs the signal from the LPF 2 to the low level. It took a long time to pull the output control voltage into the pull-in range. In other words, a bend has occurred on the display screen.
On the other hand, if the band of the LPF 2 is widened to prevent head bending, there is a problem that small jitter cannot be dealt with and the image is disturbed.

[0004] Therefore, a main object of the present invention is to provide a PLL circuit capable of outputting a high quality image.

[0005]

According to a first aspect of the present invention, there is provided an oscillating means for generating a frequency signal corresponding to a control voltage, a comparing means for comparing the phase of a frequency signal with a horizontal synchronizing signal, A filter means for generating a control voltage by removing the signal, a discriminating means for discriminating whether or not the frequency signal is locked, and a switching means for switching a time constant of the filter means in accordance with the discrimination result of the discriminating means.
This is an L circuit.

According to a second aspect of the present invention, there is provided a video signal processing circuit using the PLL circuit according to the first aspect of the present invention, wherein image data is written into the memory with a frequency signal of a predetermined clock rate output from the memory and the PLL circuit. Means for reading image data from a memory at a clock rate twice as high as a predetermined clock rate.

[0007]

According to the first aspect, the oscillating means generates a frequency signal corresponding to the control voltage. The comparing means compares the phase of the frequency signal with the phase of the horizontal synchronizing signal. The filter means removes the high frequency component of the output of the comparing means to generate a control voltage. Thus, the PLL circuit is configured. The determination means determines whether or not the frequency is locked, and the switching means switches the time constant of the filter means according to the determination result of the determination means. That is, since the time constant of the filter means is switched,
Even if you lose the lock, you can quickly pull into the pull-in range.

In one aspect of the present invention, the determining means includes a detecting means and a lock determining means. The detecting means detects the horizontal synchronizing signal at the fall of the frequency signal. The lock determining means determines whether or not the lock is performed according to the detection result of the detecting means. In this way, it is determined whether the frequency signal is locked.

In one embodiment of the present invention, when the unlocking is determined by the determining means, the switching means reduces the time constant of the filter means. Therefore, it can be pulled into the pull-in range in a short time.

[0010] In the second invention, the video signal processing circuit comprises the first video signal processing circuit.
The present invention is configured using the PLL circuit of the invention. Writing means is P
The image data is written to the memory with a frequency signal of a predetermined clock rate output from the LL circuit. On the other hand, the reading means reads the image data from the memory at a clock rate twice the predetermined clock rate. As described above, by increasing the readout rate, the aspect ratio of the displayed image can be changed.

[0011]

According to the present invention, the pull-in range is pulled in a short time by switching the time constant of the filter means, so that no bend occurs on the display screen. Further, since the time constant of the filter means is switched, it is possible to cope with jitter. Therefore, a high-quality image can be output.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0013]

Referring to FIG. 1, a video signal processing circuit 10 of this embodiment includes PLL circuits 12 and 14. The PLL circuit 12 supplies a write clock CKW to the time axis control circuit 16, and the PLL circuit 14 supplies a read clock CKR to the time axis control circuit 16. The time axis control circuit 16 uses a PLL
The image data is written into the field memory 18 using the write clock CKW provided from the circuit 12, and the image data is read from the field memory 18 at a clock rate twice as high as the read clock CKR provided from the PLL circuit 14.

The video signal processing circuit 10 includes a decoder 2
0, the decoder 20 performs processing such as color separation and color demodulation on the input video signal (composite video signal), and generates generated signals (Y signal, BY signal and R-signal).
(Y signal) are output to the LPFs 22 to 26, respectively. LP
In F22 to F26, the high frequency components of the Y signal, the BY signal, and the RY signal are removed. The respective signals from which the high-frequency components have been removed are converted into digital data by A / D converters 28 to 32 and supplied to the time axis control circuit 16. A
Digital data (image data) of Y signal, BY signal and RY signal output from / D converters 28 to 32
Is written into the field memory 18 according to the instruction of the time axis control circuit 16. That is, at the timing of the write clock CKW output via the signal line a, the image data is transmitted via the signal line c based on the write control signal output via the signal line b. It is written to a predetermined address in the memory 18.

The image data written in the field memory 18 is read out according to an instruction from the time axis control circuit 16. That is, the image data passes through the signal line f based on the read control signal output through the signal line e at a clock rate twice as high as the read clock CKR output through the signal line d. From the field memory 18.

In the video signal processing circuit 10, the composite video signal input from the input terminal S1 adopts an interlaced system and is output to a cathode ray tube (CRT) (not shown) by a progressive scan system. Is used to convert the system. That is,
The image data is written to the feed memory 18 in an interlaced manner, and is read from the feed memory 18 in a progressive scan manner. As described above, the read clock of the field memory 18 is the read clock CK.
The clock rate is twice the clock rate of R, so that an image having an aspect ratio of 16: 9 can be displayed on the CRT.

The image data (2Y signal, 2B-Y signal and 2R-Y signal) read from the field memory 18 is applied to corresponding D / A converters 34 to 38, respectively. The 2Y signal, 2B-Y signal, and 2R-Y signal converted into analog data by the D / A converters 34 to 38 are subjected to LPFs 40 to 44 to remove aliasing noise, and sent to a subsequent signal processing circuit (not shown). Is output. Further, the time axis control circuit 16 uses V-Sync given from the PLLs 12 and 14 to double V-sync (2V-s).
ync). Further, the time axis control circuit 16
Generate twice the H-sync (2H-sync). 2
V-sync and 2H-sync are used in a signal processing circuit such as a subsequent deflection circuit (not shown).

The PLL circuits 12 and 14 will be described in detail. The PLL circuits 12 and 14 are shown in FIG. The input composite video signal is supplied to a sync separation circuit 50, where it is separated into V-sync and H-sync. H-sy output from the synchronization separation circuit 50
nc is supplied to one input terminal of the comparator 52 and to a D terminal of a DQ-flip-flop (DQ-FF) 54. The V-sync output from the synchronization separation circuit 50 is directly supplied to the time axis control circuit 16. The reference signal (REF) output from the frequency divider 62 is applied to the other input terminal of the comparator 52. Therefore, the comparator 52 compares the reference signal with the horizontal synchronization signal and outputs a voltage corresponding to the comparison result. I do. The reference signal from the frequency divider 62 is supplied to a clock (CLK) terminal of the DQ-FF 54. The voltage output from the comparator 52 is provided to a low-pass filter (LPF) 56.

The LPF 56 includes a resistor R1, and the resistor R1 is connected in parallel with a series circuit in which a resistor R2 and a switch SW1 are connected in series. One end of a capacitor C1 is connected to a connection point between the resistor R1 and the switch SW1, and the other end of the capacitor C1 is connected to a ground plane. The resistance R1
One end of a resistor R3 is connected to a connection point between the switch R1 and the switch SW1, and the other end of the resistor R3 is connected to a ground plane via a capacitor C2. In the LPF 56, the switch SW1 is switched based on the output signal from the Q terminal of the DQ-FF 54, and accordingly, the time constant τ of the LPF 56 is changed according to the switching of the switch SW1. The output voltage via LPF 56 is applied to oscillation circuit 58.

The switching of the switch SW1 will be described in detail. In the DQ-FF 54, the input (H-sync) of the D terminal is latched at the falling edge of the reference signal.
A signal as shown in (C) is output from the Q terminal. That is, in the locked state, when the horizontal synchronization signal is latched at the falling edge of the reference signal, a low-level signal is output from the Q terminal. At this time, the switch SW1 is turned off.
On the other hand, in the unlocked state, H-
The state where the frequency of sync is low and the state where the frequency is high are considered. In any state, when the H-sync input to the D terminal is latched at the fall of the reference signal, the output from the Q terminal becomes high level at the fall of the clock. For this reason, the switch SW1 is turned on,
A high-level signal is output from the Q terminal until the locked state.

The oscillation circuit 58 includes an amplifier 60. One end of a varicap capacitor C3 and one end of a capacitor C4 are connected to an input terminal of the amplifier 60.
One end of the coil L1 is connected. The other end of the amplifier 60 is connected to the other end of the coil L1 and to the capacitor C5. The other end of the varicap capacitor C3, the other end of the capacitor C4 and the capacitor C5
Is connected to a ground plane. The connection point between the amplifier 60 and the coil L1 is connected to the frequency divider 62,
It is connected to the time axis control circuit 16.

The oscillation frequency of the oscillation circuit 58 is determined based on the voltage (control voltage) output from the LPF 56.
Oscillates at the determined oscillation frequency. The output signal (oscillation frequency signal) from the oscillation circuit 58 is supplied to the frequency divider 62 and also to the time axis control circuit 16. In this embodiment, the oscillation circuit 58 uses the horizontal frequency f _H (15.73).
An oscillation signal of 1820 times the frequency of 4 kHz is generated. In the frequency divider 62, the oscillation signal is frequency-divided by 1/1820 by the counter 62a and the decoder 62b, and the frequency-divided oscillation signal (reference signal) is output. In this way,
The PLL circuits 12 and 14 are provided with a reference signal and an H-sync.
Are driven so that the difference from

For example, when a composite video signal as shown in FIG. 4A is input, the horizontal synchronizing signal (H-sync) and reference signal (REF) are
It is changed as shown in (B) and (C). Switching of the switch SW1 with respect to time (switch period) is shown in FIG.
As shown in (D), when the PLL circuit 12 (14) is in the locked state, the switch period becomes low level,
The switch SW1 is turned off. On the other hand, as shown in FIG. 4A, when the PLL circuit 12 (14) is in the unlocked state, the switch period becomes high level, and the switch S
W1 is turned on. That is, if the unlock state is established at the time shown in FIG. 4A, the control voltage output from the LPF 56 is greatly disturbed as shown in FIG. For this reason, a high-level signal is output from the Q terminal of the DQ-FF 54, and a high-level signal is output until the locked state. Therefore, a stable control voltage is output from the LPF 56 until the screen display start time shown in FIG.

According to this embodiment, when the unlock state of the PLL circuits 12 and 14 is determined, the PLL circuit 1
PLL circuits 12 and 1 before the screen display starts by reducing the time constant τ of LPF 56 included in LPFs 2 and 14
4 can be locked. For this reason, no bowing occurs when the screen is displayed. Further, since the time constant τ is changed by switching the switch SW1,
Jitter can be handled. Therefore, a high-quality image can be output.

In this embodiment, the time constant τ of the LPF 56 is changed by changing the resistance value. However, the time constant is changed by changing the capacitance by using a varicap capacitor instead of the capacitor C1 or C2. τ may be changed.

[Brief description of the drawings]

FIG. 1 is an illustrative view showing one embodiment of the present invention;

FIG. 2 is an illustrative view showing a PLL circuit shown in FIG. 1 embodiment;

FIG. 3 is an illustrative view showing an input signal to a D terminal and a clock terminal and an output signal from a Q terminal of the DQ-FF shown in FIG. 2;

4A is a timing chart showing a composite video signal, FIG. 4B is a timing chart showing a horizontal synchronization signal, FIG. 4C is a timing chart showing a reference signal, and FIG. 6 is a timing chart showing a period, and FIG. 7E is a timing chart showing a control voltage output from the LPF.

FIG. 5 is an illustrative view showing a conventional PLL circuit;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Video signal processing circuit 12, 14 ... PLL circuit 16 ... Time axis control circuit 18 ... Field memory 20 ... Decoder 50 ... Synchronization separation circuit 54 ... DQ-FF 56 ... LPF 58 ... Oscillation circuit 62 ... Divider

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (4)

[Claims] An oscillator for generating a frequency signal corresponding to the control voltage; a comparator for comparing the phase of the frequency signal with a horizontal synchronizing signal; removing a high-frequency component from an output of the comparator to reduce the control voltage. Filter means for generating, determining means for determining whether the frequency signal is locked, and switching means for switching the time constant of the filter means according to the determination result of the determining means,
PLL circuit. 2. A detecting means for detecting a level of the horizontal synchronizing signal at a falling edge of the frequency signal,
2. The PLL circuit according to claim 1, further comprising a lock discriminating means for discriminating according to a detection result of said detecting means. 3. The switching means decreases the time constant when unlocking is determined by the determining means.
Or the PLL circuit according to 2. 4. The P according to claim 1, wherein
A video signal processing circuit using an LL circuit, comprising: a memory; writing means for writing the image data into the memory with a frequency signal of a predetermined clock rate output from the PLL circuit; A video signal processing circuit comprising reading means for reading from the memory at a clock rate twice as high as that of the video signal processing circuit.