JPH0944112A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent disorder of a display screen and characteristic deterioration of an LCD panel even when the horizontal synchronizing signal of a personal computer is not supplied by providing a decision circuit which controls the presence of the horizontal synchronizing signal and a fixed oscillation circuit which generates a signal of specific frequency, and selecting and outputting the horizontal synchronizing signal and the oscillation output signal of the fixed oscillation circuit according to the decision output of the decision circuit. SOLUTION: In a normal state wherein the horizontal synchronizing signal AHSYNC is applied from a personal computer to an interface circuit, the output of a decision circuit 9 controls a switching circuit 10 to supply the horizontal synchronizing signal from the personal computer to a PLL circuit 7. When the horizontal synchronizing signal AHSYNC is not applied to the interface circuit any more, the decision circuit 9 detects that and controls the switching circuit 10 to switch and supply the oscillation output of a fixed oscillation circuit 8 to the PLL circuit 7. Consequently, while the horizontal synchronizing signal AHSYNC is not present, the PLL circuit 7 is locked to the output of the fixed oscillation circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit for displaying on a digital display device using a video signal for an analog display device.

[0002]

2. Description of the Related Art In recent years, multimedia information processing apparatuses have been actively developed, and as a result, so-called personal computers have rapidly become popular not only for business use but also for personal use. These personal computers include a portable type using an LCD as a display device and a stationary type using a CRT display device.

On the other hand, in the LCD display device, a monitor display device with a built-in digital driver using a large panel of 10-inch and 11-inch class has been developed and commercialized for personal computer applications. However, C
R, G of personal computer using RT display device as monitor
Since the B output is an analog signal, such an LCD display device with a built-in digital driver could not be used as a monitor. Therefore, in order to convert the analog signal output of a personal computer into a digital signal, an interface circuit of an A / D conversion circuit is provided in a color LCD display device with a built-in digital driver so that both a digital signal output personal computer and an analog signal output personal computer are provided. I am able to deal with.

FIG. 3 is a block diagram showing a conventional interface circuit. VGA from a personal computer (PC)
Analog color signals based on (Video Graphics Array), AR, AG, AB, a vertical synchronizing signal AVSYNC, and a horizontal synchronizing signal AHSYNC are supplied. On the other hand, the color LCD display device (not shown) is
It has a built-in GA compatible LCD panel, digital driver and controller. From the interface circuit, vertical sync signal VSYNC, horizontal sync signal HSYNC, dot clock DCLK, and control signal ENA necessary for display control.
BLE and digital color signal DR for gradation display,
DG and DB are supplied.

The interface circuit is the PLL circuit 1,
A timing signal generation circuit 2 and an A / D conversion circuit 3,
It consists of 4 and 5. The PLL circuit 1 uses a horizontal synchronizing signal AHSYNC supplied from a personal computer as a reference signal, and generates a clock signal CLK locked to this signal by a voltage controlled oscillator circuit (VCO). The timing signal generation circuit 2 uses the clock signal CL from the PLL circuit 1.
K, A / D conversion circuit 3, based on the vertical synchronizing signal AVSYNC and the horizontal synchronizing signal AHSYNC from the personal computer.
4, 5 sampling control signal FS and color LC
A vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC for the D display device are created and output.

That is, this interface circuit reproduces the reference clock signal CLK based on the horizontal synchronizing signal AHSYNC from the personal computer, and this clock signal C
Various timing signals for controlling the display of the LCD display device from LK, for example, the dot clock DCLK and the digital color signal D synchronized with the dot clock DCLK.
R, DG, and DB are created.

[0007]

However, in the interface circuit shown in FIG. 3, a color LCD is used.
When the power of the personal computer is turned off while the power of the display device is turned on, the horizontal synchronization signal AHSYN from the personal computer is sent.
C is not output, and the VCO of the PLL circuit 1 is in a so-called free-run state in which it oscillates at the maximum or minimum frequency in the variable frequency range. Or, even if the power of the personal computer is turned on, the horizontal sync signal A
Even if HSYNC is no longer output, the same state will occur. When the timing signal generating circuit 2 operates by the clock signal CLK in the free-run state, the sampling signal FS, the dot clock DCLK, and the horizontal synchronizing signal HS.
YNC, vertical sync signal VSYNC, etc. become too high or too low compared to the frequency that should be originally supplied to the LCD. In this case, a non-standard frequency is applied to the LCD display device that should be driven at an appropriate frequency, so that the screen may be disturbed, the display may not be normally performed, and the liquid crystal characteristics may be deteriorated. .

[0008]

The present invention was made in view of the above-mentioned problems, and is an interface for generating a plurality of timing signals based on a horizontal synchronizing signal output from an analog video device. A circuit,
A discriminating circuit for discriminating the presence of the horizontal synchronizing signal, a fixed oscillation circuit for generating a signal of a predetermined frequency, and a discriminating output of the discriminating circuit for selectively outputting the horizontal synchronizing signal and the oscillation output signal of the fixed oscillator circuit. By including a switching circuit, a PLL circuit that generates a signal of a frequency locked to the signal from the switching circuit, and a timing signal generation circuit that generates a plurality of timing signals based on the output signal of the PLL circuit, Even when the synchronization signal is no longer applied to the interface circuit, the PLL circuit locks on the fixed oscillation circuit, so that a normal timing signal can be supplied to the LCD display device.

Further, a discriminating circuit for discriminating the presence of the horizontal synchronizing signal, a PLL circuit for generating a signal having a frequency locked to the horizontal synchronizing signal, and a signal having a frequency substantially equal to the frequency outputted from the PLL circuit are outputted. A fixed oscillation circuit, a switching circuit that selectively outputs the output of the PLL circuit and the output of the fixed oscillation circuit according to the discrimination output of the discrimination circuit, and a plurality of timing signals are generated based on the signal output from the switching circuit. By providing the timing signal generating circuit, the timing signal generating circuit operates by the output of the fixed oscillation circuit instead of the PLL circuit even when the horizontal synchronizing signal is not applied to the interface circuit. Can be supplied to an LCD display device.

Further, A for converting an analog video signal supplied in synchronization with the horizontal sync signal into a digital video signal
A / D conversion circuit, and the sampling clock of the A / D conversion circuit is supplied from the timing signal generation circuit, so that the A / D conversion circuit operates normally even if the horizontal synchronization signal is not applied to the interface circuit. It is possible to secure proper operation.

[0011]

1 is a block diagram of an interface circuit showing an embodiment of the present invention. From the personal computer, analog color signals AR, AG, and AB of each color are applied in synchronization with the vertical sync signal AVSYNC and the horizontal sync signal AHSYNC. The interface circuit includes a timing signal generation circuit 6, a PLL circuit 7, a fixed oscillation circuit 8, a discrimination circuit 9, a switching circuit 10, and A / D conversion circuits 11, 12, and 13.

The timing signal generating circuit 6 includes a vertical synchronizing signal AVSYNC, a vertical synchronizing signal AHSYNC, and
The clock signal CLK of the PLL circuit 7 is applied. As is well known, the timing signal generation circuit 6 includes a counter that divides the clock signal CLK and a logic circuit that creates various timing signals based on the count value of the counter. The dot clock DCLK is a clock for transferring data displayed in the pixels of each line, and in the case of VGA, its frequency is about 20 MHZ. Further, since the A / D conversion circuits 11, 12 and 13 generate digital data synchronized with the dot clock DCLK, the sampling signal FS thereof needs to have the same frequency of about 20 MHZ as the dot clock DCLK.
Therefore, the clock signal CLK needs to have a frequency of 20 MHz or higher.

As is well known, the PLL circuit 7 is a frequency control oscillator circuit VCO, a frequency divider circuit for dividing the oscillation signal of the VCO,
It is composed of a phase comparison circuit for comparing the reference signal with the output of the frequency divider circuit, a low-pass filter for converting the output of the phase comparison circuit into a voltage, and the like. Here, the clock signal CL
Since K requires about 20 MHZ, the oscillation frequency of the VCO is set to about 20 MHZ or 40 MHZ. On the other hand, since the horizontal synchronizing signal 31.5KHZ is used as the reference signal, the oscillation frequency of the VCO is divided into 31.5KHZ by the frequency dividing circuit, and this frequency division output is compared with the reference signal.

A feature of the present invention is that the discrimination circuit 9 for detecting the presence or absence of the horizontal synchronizing signal AHSYNC applied from the personal computer.
If the horizontal synchronization signal AHSYNC is not detected by the switch circuit 10, the switching circuit 10 switches the reference signal from the horizontal synchronization signal AHSYNC to the oscillation output of the fixed oscillation circuit 8. The discriminating circuit 8 integrates the applied horizontal synchronizing signal AHSYNC and determines that there is no horizontal synchronizing signal AHSYNC when the integrated value becomes a predetermined level or less, or by counting the clock signal CLK, The timing at which the synchronization signal AHSYNC is applied is predicted, the gate is opened during that period, and the horizontal synchronization signal AH
There is a method of checking the existence of SYNC. Fixed oscillator circuit 8
Is the same as the AHSYNC with the same oscillation frequency 3
It is composed of a crystal oscillation circuit having 1.5 KHZ and starts oscillation when the display device is powered on.

In the normal state where the horizontal synchronizing signal AHSYNC is applied from the personal computer to the interface circuit, the output of the discrimination circuit 9 controls the switching circuit 10 to PLL the horizontal synchronizing signal AHSYNC from the personal computer.
Supply to the circuit 7. However, the horizontal sync signal AHSYNC
Is not applied to the interface circuit,
The discrimination circuit 9 detects this, controls the switching circuit 10 by its output, and outputs the oscillation output of the fixed oscillation circuit 8 as PL.
The L circuit 7 is switched and supplied. As a result, when the horizontal synchronizing signal AHSYNC does not exist, the PLL circuit 7
Will lock to the output of the fixed oscillation circuit 8, and the VCO will not fall into the free-run state as in the conventional case.
A normal frequency timing signal is obtained.

FIG. 2 is a block diagram of an interface circuit showing another embodiment of the present invention. 2 is different from FIG. 1 in that the PLL is based on the output of the discrimination circuit.
The output of the circuit 10 and the output of the fixed oscillation circuit 15 are switched by the switching circuit 14 and supplied to the timing signal generation circuit 6. The reference signal of the PLL circuit 10 is always the horizontal synchronizing signal AHSYNC, and its output is applied to the switching circuit 14. On the other hand, the fixed oscillator circuit 15
The frequency of the output signal of the PLL circuit 10, that is, about 20 MH
The crystal oscillation circuit has an oscillation frequency equal to Z or 40 MHZ, and its output is applied to the switching circuit 14. The discrimination circuit 9 controls the PLL circuit 10 and the switching circuit 14, and keeps the operation of the PLL circuit 10 in a state where the horizontal synchronizing signal AHSYNC is normally supplied to the interface circuit, as in FIG. ,
Further, the switching circuit 14 is controlled to supply the output of the PLL circuit 10 as the clock signal CLK to the timing signal generating circuit 6. On the other hand, when there is no horizontal synchronizing signal AHSYNC, the determination circuit 14 stops the operation of the PLL circuit 10 and controls the switching circuit 14 to supply the output of the fixed oscillation circuit 15 to the timing signal generation circuit 6.

Therefore, in the state where there is no horizontal synchronizing signal AHSYNC, the timing signal generating circuit 6 operates as the fixed oscillator circuit 1.
Since various timing signals are generated by the clock signal CLK generated by 5, the liquid crystal display device is not supplied with a signal having an abnormal frequency outside the specified range.

[0018]

As described above, according to the present invention, in the interface circuit for analog input of the LCD display device with the built-in digital driver, even if the horizontal synchronizing signal from the personal computer is not supplied, the LCD display device It is possible to generate a timing signal having a frequency within a specified range, and there is an advantage that disturbance of the display screen and deterioration of the characteristics of the LCD panel can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 6 Timing signal generation circuit 7 PLL circuit 8 Fixed oscillation circuit 9 Discrimination circuit 10 Switching circuit 11, 12, 13 A / D conversion circuit 14 Switching circuit 15 Fixed oscillation circuit

Claims (3)

[Claims] 1. An interface circuit for generating a plurality of timing signals based on a horizontal synchronizing signal output from an analog video device, a determining circuit for determining the presence of the horizontal synchronizing signal, and a predetermined frequency. A fixed oscillation circuit for generating a signal of the above, a switching circuit for selectively outputting the horizontal synchronizing signal and the oscillation output signal of the fixed oscillation circuit according to the discrimination output of the discrimination circuit, and a signal of a frequency locked to the signal from the switching circuit. An interface circuit including a PLL circuit that generates a timing signal and a timing signal generation circuit that generates a plurality of timing signals based on an output signal of the PLL circuit. 2. An interface circuit for generating a plurality of timing signals based on a horizontal synchronizing signal output from an analog video device, a determining circuit for determining the presence of the horizontal synchronizing signal, and the horizontal synchronizing signal. PLL circuit for generating a signal of a locked frequency, and the PLL circuit
A fixed oscillation circuit that outputs a signal having a frequency substantially equal to the frequency output from the circuit, a switching circuit that selectively outputs the output of the PLL circuit and the output of the fixed oscillation circuit according to the discrimination output of the discrimination circuit, and the switching circuit. And a timing signal generation circuit that generates a plurality of timing signals based on signals output from the interface circuit. 3. An A / D for converting an analog video signal supplied in synchronization with the horizontal synchronization signal into a digital video signal.
3. The interface circuit according to claim 1, further comprising a conversion circuit, wherein the sampling clock of the A / D conversion circuit is supplied from the timing signal generation circuit.