JPH09191416A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time required for locking when the pull-in range of a phase locked loop is covered by means of plural continuous pull-in ranges. SOLUTION: The frequency of a horizontal synchronizing signal from a terminal 1 is discriminated in a horizontal frequency discrimination part 8. A control signal is transmitted to a clock generator 5 from CPU 13. A signal from a voltage controlled oscillator 4 is controlled to be converted into the frequency corresponding to the horizontal frequency. A corresponding dot clock frequency data table is read from a storage part 9, and it is transmitted to the clock generator 5 so as to control it. A locking discrimination part 10 compares a dot clock 6 with a reference signal 11 so as to discriminate locking, and the dot clock frequency data is recorded in a memory part 12 at every time. At the time of switching the signal, CPU 13 controls the clock generator 5 with data which is read from the memory part 12. When locking is not executed, control is executed with data which is read from the storage part 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and
The present invention relates to one that shortens the search time of the pull-in range when the pull-in range of the LL (phase locked loop) is covered by a plurality of continuous pull-in ranges.

[0002]

2. Description of the Related Art In a video display device in which display pixels have a one-to-one correspondence with video data, for example, a video display device using a liquid crystal display element, the frequency (horizontal frequency) and phase of the horizontal synchronizing signal of the input video signal However, it is necessary to match the frequency and phase of the dot clock, which is the reference of the display timing of the video display device. This is because if the phase of the dot clock deviates from the input synchronization signal, the sampling position of the display data may deviate and the image may not be displayed normally.If the frequency of the dot clock is different from the input horizontal frequency, This is because there is a problem that the image data is thinned out or added due to the difference in the sampling number of the image data per unit time, and the normal image cannot be displayed. Furthermore, the phase of the dot clock and the horizontal synchronization signal is pulled in. If the range is exceeded, it may happen that the synchronization is lost.

When the video signal source is a small computer device or the like, the output signal of the small computer device has a variation in horizontal frequency between the devices, and the pull-in range of the PLL is set wide in order to absorb this variation on the display device side. There is a need. Therefore, a method is used in which a plurality of pull-in ranges are continuously provided and a pull-in range to be locked is searched. However, this method switches the pull-in range in order from the lowest (or highest) frequency every time the lock is released due to switching of the input signal, etc., and searches for the lock-in range. Therefore, the dot clock frequency is high (or There is a problem that it takes time to lock when it is in the (low) area.

[0004]

SUMMARY OF THE INVENTION In view of such a point, the present invention requires a lock when searching for a pull-in range in which a plurality of pull-in ranges are continuously provided in order to widen the pull-in range of the PLL. To save time.

[0005]

In order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by inputting a clock generator for generating a dot clock and an output signal of the clock generator via a frequency divider to obtain a phase of a horizontal synchronizing signal. A phase comparator to compare, a voltage controlled oscillator that oscillates at a frequency based on the signal from the phase comparator, a storage unit that stores predetermined dot clock frequency data, and a signal from the voltage controlled oscillator to a required frequency. A CPU that controls the clock generator based on the data read from the storage unit so as to be converted and output, and a lock determination unit that determines the lock of the PLL including the clock generator, the frequency divider, the phase comparator, and the voltage controlled oscillator. , Horizontal synchronization with the memory unit that records the dot clock frequency data when the lock is determined by the lock determination unit A horizontal frequency discriminating section for discriminating the frequency of the signal, and by switching the input signal, the CPU reads dot clock frequency data corresponding to the signal from the horizontal frequency discriminating section from the memory section, and operates the clock generator. An image display device that is controlled is provided.

[0006]

With the above construction, in the video display device according to the present invention, the CPU reads the dot clock frequency data corresponding to the signal from the horizontal frequency discriminating unit from the storage unit, controls the clock generator, and controls the clock generator. Generate a frequency dot clock. Then, the dot clock frequency data when the PLL is locked is recorded in the memory unit. When switching the input signal, the CPU reads the dot clock frequency data corresponding to the signal from the horizontal frequency discriminating unit from the memory unit, controls the clock generator, and responds to the signal from the horizontal frequency discriminating unit when the PLL is not locked. The dot clock frequency data to be read is read from the storage unit to control the clock generator.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a video display apparatus according to the present invention. FIG. 1 is a block diagram of a main part of an embodiment of a video display device according to the present invention. In the figure, reference numeral 1 is an input terminal for a horizontal synchronizing signal (H-sync), which inputs a horizontal synchronizing signal such as 15 KHz, 24 KHz, 31 KHz or 37 KHz. Reference numeral 2 denotes a phase comparator which compares the phases of the horizontal synchronizing signal from the terminal 1 and the signal from the frequency divider 7 and outputs a signal corresponding to the phase difference. 3 is LPF (low pass filter)
Then, the signal from the phase comparator 2 is integrated to obtain a DC component. A VCO (voltage controlled oscillator) 4 oscillates at a frequency corresponding to the voltage from the LPF 3. A clock generator 5 converts a signal from the VCO 4 into a frequency based on a signal from a CPU 13 described later and outputs it (dot clock 6). The frequency divider 7 frequency-divides the dot clock 6 from the clock generator 5 and inputs it to the phase comparator 2. The phase comparator 2, LPF 3, VCO 4, clock generator 5 and frequency divider 7 form a PLL.

Reference numeral 8 is a horizontal frequency discriminating section for discriminating the frequency of the horizontal synchronizing signal from the terminal 1. A storage unit 9 stores predetermined dot clock frequency data corresponding to the frequency of the horizontal synchronizing signal (15 KHz, 24 KHz, 31 KHz, 37 KHz, etc. described above). A lock determination unit 10 compares the dot clock 6 from the clock generator 5 with a reference signal 11 to determine lock / unlock of the PLL. Reference numeral 12 is a memory unit, and when the lock is determined by the lock determination unit 10, each time,
The dot clock frequency data is recorded together with the data from the horizontal frequency discrimination unit 8. The CPU 13 reads out the dot clock frequency data of the horizontal frequency determined by the horizontal frequency determination unit 8 from the storage unit 9, transmits it to the clock generator 5, controls the frequency of the dot clock, and the lock determination unit 10 unlocks. If it is determined, another dot clock frequency data is read and the clock generator 5 is controlled. When the input signal is switched, the dot clock frequency data corresponding to the data from the horizontal frequency discriminating unit 8 is searched from the data in the memory unit 12, and if it is recorded, it is read out to control the clock generator 5. When the data corresponding to the memory unit 12 is not recorded, the dot clock frequency data is read from the storage unit 9 and the clock generator 5 is controlled.

Next, the operation of the image display device according to the present invention will be described. First of all, in the horizontal frequency discriminating section 8, the frequency of the horizontal synchronizing signal from the terminal 1 (15KHz, 24KHz, etc.)
Is input to the CPU 13. The CPU 13 reads the dot clock frequency data corresponding to this frequency from the storage unit 9, and transmits the lowest dot clock frequency data to the clock generator 5, for example. FIG. 2 is an example of dot clock frequency data. Such data is provided for each horizontal frequency, and each data is plural from the lowest frequency (in the example of the figure, there are six,
(Some dozens of settings may be required depending on the type of small computer device) and the pull-in ranges are appropriately overlapped and set. The clock generator 5 converts the signal from the VCO 4 into a required frequency based on the signal from the CPU 13. The dot clock 6 from the clock generator 5 is frequency-divided by the frequency divider 7 at a required frequency division ratio, and the phase comparator 2
, And compare the phase with the horizontal sync signal from terminal 1,
A signal (voltage) corresponding to the phase difference is output, this signal (voltage) is applied to the VCO 4 via the LPF 3, and the phase of the dot clock 6 gradually approaches the phase of the horizontal synchronizing signal from the terminal 1. Then, the lock discrimination unit 10 compares the dot clock 6 with the reference signal 11, and when the lock is not discriminated, the dot clock frequency data is serially transmitted to the clock generator 5, the unlock is discriminated, and a search operation such as ... Repeatedly search the lock-in range. Then, by locking, the center frequency data is recorded in the memory unit 12 together with the data from the horizontal frequency determining unit 8. In the above description, the lock determination unit 10 compares the dot clock 6 with the reference signal 11 to determine the lock. However, the lock determination unit 10 may determine the lock based on the signal (voltage) from the LPF 3. Good.

When a new horizontal synchronizing signal is input to the terminal 1 by turning off the power of the apparatus or switching the signal input, C
The PU 13 first reads the dot clock frequency data corresponding to the horizontal frequency determined by the horizontal frequency determination unit 8 from the memory unit 12, transmits it to the clock generator 5, and controls the frequency. When the data corresponding to the memory unit 12 is not recorded, the dot clock frequency data corresponding to the signal from the horizontal frequency determining unit 8 is read from the storage unit 9 and the dot clock frequency of the lowest frequency is read, as in the above case. The data is sent to the clock generator 5 for control, and if it is not locked, the dot clock frequency data is sent for control, the search is performed in the same manner as above, and the clock is determined in this state by the lock discrimination. While controlling the generator 5, the dot clock frequency data is recorded in the memory unit 12 together with the data from the horizontal frequency discriminating unit 8. The memory unit 12 records the input data each time the lock is determined. That is, when the input data is the same as the already recorded data, this data is updated (same as the original), and when the unrecorded data is input, it is newly recorded.

As a result, all dot clock frequency data corresponding to the respective horizontal synchronizing signals of the signal sources which are input to this apparatus and which are normally synchronized are recorded in the memory section 12, and the switching input of these signal sources is performed. If so, the CPU 13 controls the clock generator 5 only with the data read from the memory unit 12, so that the PLL locks. Therefore, as described above, the dot clock frequency data is read from the storage unit 9 every time the signal is switched, and the frequency of the frequency is read. The operation of sequentially searching the pull-in range from the lower one is not necessary, and the time required for locking can be shortened. The memory unit 12
In addition, keeping the data for the signal source that is unlikely to be connected in the future is an obstacle to shortening the lock time. Therefore, a clear button or the like may be provided so that the data in the memory unit 12 can be erased via the CPU 13 by a signal from the clear button.

[0012]

As described above, according to the image display device of the present invention, the dot clock frequency data corresponding to the signal source which is input to this device and which is normally synchronized is recorded in the memory, and when the signal input is switched. Since the clock generator is controlled by using the data in this memory, it takes almost no time to lock the PLL regardless of the horizontal frequency as long as the signal source has been processed normally once.

[Brief description of the drawings]

FIG. 1 is a main block diagram of an embodiment of a video display device according to the present invention.

FIG. 2 is an example of a frequency range corresponding to a dot clock of the image display device according to the present invention.

[Explanation of symbols]

 1 Horizontal sync signal (H-sync) input terminal 2 Phase comparator 4 VCO (voltage controlled oscillator) 5 Clock generator 7 Divider 8 Horizontal frequency discrimination unit 9 Storage unit 10 Lock discrimination unit 11 Reference signal 12 Memory unit 13 CPU

Claims (6)

[Claims] 1. A clock generator for generating a dot clock, a phase comparator for inputting an output signal of the clock generator through a frequency divider to compare the phase with a horizontal synchronizing signal, and a signal from the phase comparator. A voltage-controlled oscillator that oscillates at a predetermined frequency, a storage unit that stores predetermined dot clock frequency data, and a signal that is read from the storage unit so that the signal from the voltage-controlled oscillator is converted to a required frequency and output. A CPU for controlling the clock generator, a lock discriminating unit for discriminating the lock of the PLL including the clock generator, the frequency divider, the phase comparator and the voltage controlled oscillator, and dot clock frequency data when the lock discriminating unit discriminates the lock. And a horizontal frequency discriminating unit for discriminating the frequency of the horizontal synchronizing signal, By switching the input signal, the CPU
Read dot clock frequency data corresponding to the signal from the horizontal frequency determination unit from the memory unit,
A video display device adapted to control a clock generator. 2. The storage unit stores a plurality of dot clock frequency data for handling a plurality of types of horizontal synchronizing signals, and the CPU causes a dot clock corresponding to a signal from the horizontal frequency determining unit. The video display device according to claim 1, wherein frequency data is read from a storage unit to control the clock generator. 3. The video according to claim 1, wherein the memory section records the dot clock frequency data together with the data from the horizontal frequency determining section each time the lock determining section determines the lock. Display device. 4. The memory unit controls the clock generator based on the dot clock frequency data read from the storage unit to control the dot clock together with the data from the horizontal frequency determination unit when the lock determination unit determines lock. The video display device according to claim 1 or 2, which records frequency data. 5. The CPU controls the clock generator based on the data read from the memory section, and when the lock is not judged by the lock judging section, the dot clock frequency data is read from the storing section and the clock generator is set. Claims 1, 2, which are controlled by
The image display device according to claim 3 or 4. 6. The image display device according to claim 1, wherein the data recorded in said memory portion can be erased by providing a clear input portion.