JP2622759B2 - PLL circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Locked Loop) circuit capable of quickly locking a frequency change of an input signal, and more particularly to a plurality of video signals having different horizontal frequencies. Is suitably applied to a multi-scan type display device capable of receiving an image.

[Conventional technology]

In addition to standard NTSC video signals, multiple video signals with different horizontal frequencies, such as high-quality video signals with doubled scanning lines and video signals of computer images with high-resolution display,
Multi-scan display devices capable of receiving images with a single receiver have been developed.

FIG. 3 is a block diagram showing an example of a PLL circuit applied to such a multi-scan display device. This PLL circuit includes a basic configuration of a phase comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator (VCO) 4, and a 1 / N divider 5, and furthermore, locks quickly to an input signal Si. VCO control circuit 10 is provided.

The VCO control circuit 10 includes, for example, a frequency / voltage (FV) converter 11 that detects the frequency fi of the input signal Si as a horizontal synchronization signal and outputs a DC voltage Di, a comparator that compares the DC voltage Di with a reference voltage 12, a decoder 13 for outputting a plurality of switching signals SW ₁ to SW ₄ from the comparison result of the comparator 12, the switching signal SW ₁ to SW
₄ by selecting the power from the plurality of DC power supply V ₁ ~V ₄ 1 control signal Sd ₂ as an analog switch 14 supplies the VCO4
Consists of

In this configuration, when the frequency fi of the input signal Si changes, a plurality of DC power supplies V _{1 to} V ₄
Supplied as the control signal Sd ₂ to VCO4 in which one power source is selected in the capture range within from the. Next, by the basic configuration of the PLL circuit, the frequency fo of the output signal So of the VCO 4 acts so that fo = Nfi with respect to the input frequency fi and locks in. Incidentally, VCO 4 is composed of two-input VCO that is controlled by the sum of the output signals Sd ₂ of the output signal Sd ₁ and the analog switch 14 of the loop filter 3.

According to this conventional example, even if the input signal frequency fi changes greatly, the VCO 4 is directly controlled by the VCO control circuit 10 so that the oscillation frequency fo of the VCO 4 immediately falls within the capture range. Time can be greatly reduced.

[Problems to be solved by the invention]

However, in the above-described conventional example, if the DC output value of the amplifier constituting the loop filter 3 deviates by a certain degree or more, VC
O4 oscillation jitter increases, and the tracking performance of the vertical synchronization period deteriorates. Also requires a complicated circuit structure as the VCO control circuit, moreover, it must be adjusted voltage values of the plurality of the DC power supply V ₁ ~V ₄ according to the frequency of the plurality of input signals received, frequent adjustment There is a disadvantage of requiring work.

The present invention provides a PLL circuit that has a simple circuit configuration, can lock quickly even when the input frequency changes to either high or low, and can reduce deterioration of the response level in the jitter level and vertical synchronization period. The purpose is to provide.

[Means for solving the problem]

A PLL circuit according to the present invention detects a fluctuation value of a DC component of a first voltage control signal output from a loop filter, and outputs a voltage signal corresponding to the fluctuation value; And a comparator for comparing the voltage signal output from the comparator with a predetermined reference value and supplying a voltage signal of the difference as a second voltage control signal to a voltage controlled oscillator of the PLL circuit. The oscillation frequency of the voltage controlled oscillator is controlled by the voltage control signal.

(Operation)

In this configuration, the input signal Si of the frequency fi is supplied to the PLL circuit.
Is input from the loop filter, a DC voltage signal corresponding to the phase difference between the input signal frequency fi and the output signal frequency fo of the voltage controlled oscillator is output. Is entered.

When the frequency difference between the frequency fi and the frequency fo is large and the fluctuation of the first voltage control signal is large, the fluctuation value is detected by the fluctuation value detector, and further compared with the reference value by the comparator to obtain the reference value. Is supplied to the voltage controlled oscillator as a second voltage control signal.

The voltage controlled oscillator outputs an output signal So corresponding to the first and second voltage control signals, and compares the output signal So with the input signal Si again.

When this series of operations is continued until the PLL circuit is locked, the level of the second voltage control signal becomes substantially equal to the DC level of the first voltage control signal in the level variable range as the output frequency fo approaches the input signal frequency fi. The output is made to be a point, and after the circuit is locked, the output frequency fo of the voltage controlled oscillator is controlled only by the first voltage control signal.

As described above, since the voltage controlled oscillator is controlled by the second voltage control signal in addition to the first voltage control signal,
Even if the frequency fi of the input signal Si changes greatly, the PLL circuit is quickly pulled into the capture range and locked in a short time with a simple configuration.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. The same parts as those in FIG.

In this embodiment, a phase comparator 1, which is a basic configuration of a PLL circuit, is used.
Charge pump 2, in addition to the loop filter 3, VCO 4 and the 1 / N frequency divider 5, a voltage signal corresponding to the change value by detecting the variation of the voltage control signal Sd ₁ output from the loop filter 3 a variation detector 21 of the low-pass filter configured to output, as compared with a predetermined reference value Vr which defines a voltage signal output from the fluctuation value detector 21 in advance, and outputs the difference as a voltage control signal Sd ₂ And a comparator 22 for supplying to the VCO4.

FIG. 2 is a circuit diagram showing the configuration of the VCO 4. The VCO 4 is a first voltage control signal Sd ₁ output from the loop filter 3.
And the second voltage control signal Sd ₂ output from the comparator 22 are input to the control terminal of the oscillation circuit 41 and are applied to the varactor diodes 42 and 43 to change the varactor capacitance to control the oscillation frequency fo. It is configured as follows.

When a reverse voltage is applied to the varactor diodes 42 and 43,
The capacitance changes according to the applied voltage. Therefore, in order to change the capacitance of the varactor diode 43 according to the voltage value output from the fluctuation value detector 21, it is necessary to add a bias voltage. The reference value Vr of the comparator 2 corresponds to a bias voltage for adding a bias voltage (Vr) to the voltage output from the fluctuation value detector 21. When the PLL circuit is locked to the input signal Si, the output signal Sd ₁ of the loop filter 3 is hardly fluctuate, VCO 4 is controlled only by the signal Sd _1, the output signal So of the frequency fo (= Nfi) Output.

When the input signal Si is switched to another signal and the frequency fi changes, the phase comparator 1 outputs a frequency difference between the input signal frequency fi and the frequency f _N (= fo / N) of the output signal _SN of the frequency divider 5. Is output, and the charge pump 2 outputs a DC error voltage Sc due to the phase difference. The DC error voltage Sc has its high frequency component removed by the loop filter 3 and is input to the VCO ₄ as the voltage control signal Sd1.

Further, the voltage control signal Sd ₁ is input to the fluctuation value detector 21 having a low-pass filter configuration, is converted into a voltage signal corresponding to the fluctuation, and is input to the comparator 22. The comparator 22 compares this voltage signal with the reference value Vr, and supplies a signal corresponding to the difference to the VCO ₄ as a voltage control signal Sd2.

The VCO 4 changes the capacitance of the varactor diodes 42 and 43 according to the voltage control signal Sd ₁ input from the loop filter 3 and the voltage control signal Sd ₂ input from the comparator 22,
The oscillation frequency fo of the oscillation circuit 41 is controlled. In this case, the voltage control signal Sd ₁ is to keep the level in the center of the amplifier power supply voltage of the loop filter 3, a voltage control signal Sd ₂ is controlled so that the voltage control signal Sd ₁ approach the center of the operating range.

The output signal So of the VCO 4 thus obtained is frequency-divided by the frequency divider 5 to 1 / _N , and then input to the phase comparator as the comparison signal _SN . This series of operations is continued until the PLL circuit is locked.

Thus, the oscillation frequency fo of the VCO 4 is equal to the voltage control signal Sd ₁
Besides since it is controlled by the voltage control signal Sd ₂ of
Be varied input signal Si is input signal frequency fi is much switches, PLL circuit is quickly drawn into the capture range can be locked in a shorter time than the case that is controlled only by the voltage control signal Sd ₁ . In this case, the level of the voltage control signal Sd ₂ is outputted as the DC level of the voltage control signal Sd ₁ is substantially middle point of the level variable range as the oscillation frequency fo of the VCO4 approaches the input signal frequency fi,
After the PLL circuit is locked is VCO4 is controlled only by the voltage control signal Sd _1.

〔The invention's effect〕

ADVANTAGE OF THE INVENTION According to this invention, even if an input signal frequency changes, it can lock quickly with a simple structure, and adjustment is unnecessary.
Since a PLL circuit can be provided, the present invention is suitable for, for example, a multi-scan television receiver that receives various video signals having different horizontal frequencies.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, FIG. 2 is a diagram showing a configuration of a two-input VCO in FIG. 1, and FIG. 3 is a block diagram showing a configuration of a conventional PLL circuit. is there. 1 ... phase comparator, 2 ... charge pump, 3 ... loop filter, 4 ... 2 input VCO, 5 ... frequency divider, 21 ...
... fluctuation value detector, 22 ... comparator.

Claims (1)

(57) [Claims] 1. A PLL circuit comprising a phase comparator, a loop filter, and a voltage controlled oscillator, wherein a PLL loop is formed, and input signals having different frequencies are input to the phase comparator, wherein the voltage output from the loop filter is A first voltage control signal for controlling the oscillation frequency of the control oscillator is input, and a fluctuation value detection for detecting a fluctuation value of a DC component of the first voltage control signal and outputting a voltage signal corresponding to the fluctuation value And a comparator for comparing the voltage signal with a predetermined reference value and supplying a voltage signal of the difference as a second voltage control signal to a voltage-controlled oscillator of the PLL loop. A PLL circuit which controls an oscillation frequency of the voltage controlled oscillator by a second voltage control signal from the comparator together with a signal.