JPH03159319A - Pll circuit - Google Patents

Abstract

PURPOSE:To quickly perform lock with simple circuit configuration even when an input frequency changes by controlling the oscillation frequency of a voltage controlled oscillator with a first voltage control signal and a second voltage control signal corresponding to the fluctuation value of the first voltage control signal. CONSTITUTION:The first voltage control signal Sd1 corresponding to a phase difference between an input signal frequency fi and the output signal frequency 0 of the voltage controlled oscillator 4 is inputted from a loop filter 3 to the voltage controlled oscillator 4. When high fluctuation exists in the first voltage control signal Sd1, the fluctuation value is detected with a fluctuation value detector 21, and it is compared with a reference value Vr with a comparator 22, and a differential value is supplied to the voltage controlled oscillator 4 as the second voltage control signal Sd2. Therefore, it follows that the voltage controlled oscillator is controlled with the second voltage control signal other than the first voltage control signal. In sush a way, the PLL circuit can be pulled in to a capture range even when the input signal frequency remarkably changes, and the lock can be performed in a short time with the simple circuit configuration.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a PLL (Phase Lock) system that can rapidly lock against frequency changes in human input signals.
edLoop) circuit, it is particularly suitable for application to a multi-scan display device that can receive a plurality of video signals with different horizontal frequencies.

[Conventional technology]

In addition to standard NTSC video signals, a single receiver can receive multiple video signals with different horizontal frequencies, such as high-quality video signals with double the number of scanning lines and high-resolution computer image video signals. Multi-scan display devices have been developed that are capable of displaying multiple images.

FIG. 3 is a Bronnoch diagram showing an example of a PLL circuit applied to such a multi-scan display device. The basic structure of this PLL circuit is a phase comparator 1, a charge pump 2, a loop filter 3, and a voltage controlled oscillator (VC
○) Equipped with 4 and 1/N frequency divider 5, and further includes human input signal S
A VCO control circuit 10 is provided for quickly clocking to i.

■The CO control circuit 10 includes, for example, a frequency/voltage (FV) converter 11 that detects the frequency fi of the input signal Si as a horizontal synchronization signal and outputs the DC voltage Di;
A comparator 12 for comparing the voltage and the reference voltage, this comparator 12
From the comparison results, multiple switching signals S W t − S W
Decoder 13 outputs 4, switching signal S W t ~ SW
The analog switch 14 selects a power source 1 from a plurality of DC power sources 1 to 4 according to 4 and supplies it to the VCO 4 as a control signal Saz.

In this configuration, when the frequency fi of the input signal St changes, the analog switch l4 causes a plurality of DC power sources
One power source within the capture range is selected from t to 4 and supplied to the VCO 4 as a control signal SaZ. Next, according to the basic structure of the PLL circuit, the frequency fo of the output signal So of the VCO 4 is
=Nfi to lock in. The VCO 4 is a two-man VCO controlled by the sum of the output signal Sd1 of the loop filter 3 and the output signal Sdz of the analog switch l4.

According to this conventional example, even if the input signal frequency fi changes significantly, the oscillation frequency fO of the VCO 4 is immediately captured.
■V is controlled by the CO control circuit 10 so that it is within the range.
Since CO4 is directly controlled, the lock time of the PLL circuit can be significantly shortened.

[Problem to be solved by the invention]

However, in the conventional example described above, if the DC output value of the amplifier that controls the loop filter 3 deviates to a certain extent, the vC
○4 oscillation jitter increases and vertical synchronization period followability worsens. In addition, the ■C○ control circuit requires a complicated circuit configuration, and the voltage values of the multiple DC power supplies ■1 to ■4 must be adjusted according to the frequencies of the multiple input signals received. This has the disadvantage of requiring complicated adjustment work.

The present invention is a PLL circuit that has a simple circuit structure, can quickly lock even if the input frequency changes high or low, and can reduce the jitter level and the deterioration of response during the vertical synchronization period. The purpose is to provide

[Means for Solving the Problems] A PLL circuit according to the present invention detects a DC fluctuation value of a first voltage control signal output from a loop filter and outputs a voltage signal according to this fluctuation value. a fluctuation value detector that determines whether the voltage signal is greater than or equal to a predetermined reference value, and if it is greater than or equal to the reference value, supplies a control signal proportional to the voltage signal to the voltage controlled oscillator of the PLL circuit as a second voltage control signal. and a comparator, and is configured to control the oscillation frequency of the voltage controlled oscillator using the first and second voltage control signals.

[For production]

In this configuration, when an input signal Si with a frequency ft is input to the PLL circuit, a DC voltage signal corresponding to the phase difference between the input signal frequency fi and the output signal frequency fo of the voltage controlled oscillator is output from the loop filter. The voltage control signal is output and input to the voltage control oscillator as the I-th voltage control signal.

When the frequency difference between the frequency "i" and the frequency fo is large and the variation of the l-th voltage control signal is large, the variation value is detected by the variation value detector, and further compared with the reference value by the comparator and set as the reference value. When the difference value from the reference value is larger than the reference value, the difference value from the reference value is supplied to the voltage controlled oscillator as a second voltage control signal.

The voltage controlled oscillator outputs an output signal So corresponding to the first and second voltage control signals, and again outputs an input signal Si.
Compare with.

If this series of actions continues until the PLL circuit locks, the level of the second voltage control signal will change as the output frequency fo approaches the human input signal frequency fi, and the DC level of the first voltage control signal will rise to approximately the middle of the level variable range. After the circuit is locked, the output frequency fo of the voltage controlled oscillator is controlled only by the first voltage control signal.

In this way, since the voltage controlled oscillator is controlled by the second voltage control signal in addition to the first voltage control signal, the PLL circuit can quickly capture even if the frequency fi of the input signal St changes significantly. - Pulls into the microwave and locks in a short time with a simple configuration.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention, and the same parts as those in FIG. 3 will be described with the same reference numerals.

This embodiment uses a phase comparator l, which is the basic structure of a PLL circuit.
, the charge pump 2, the loop filter 3, the VCO 4, and the 1/N frequency divider 5, as well as detecting fluctuations in the voltage control signal Sd output from the loop filter 3, and generating a voltage signal according to the fluctuation value. A fluctuation value detector 21 with a low-pass filter structure that outputs a voltage signal determines whether or not this voltage signal is greater than a predetermined reference value Vr, and when it is equal to or greater than the reference value V', a voltage signal proportional to this voltage signal is determined. The comparator 22 outputs the voltage control signal Sdt and supplies it to the VCO 4.

Figure 2 is a circuit diagram showing the configuration of VCO4.
The first voltage control signal Sd output from the loop filter 3 and the second voltage control signal Sd2 output from the comparator 22 are input to the control terminal of the oscillation circuit 41, and the varactor diode 42 and 43, the oscillation frequency fo is controlled by changing the varactor capacitance.

In this structure, when the PLL circuit is locked to the input signal Si, the output signal Sd1 of the loop filter 3
Since there is almost no variation, CO4 is controlled only by the signal Sd, and outputs an output signal So of frequency fo (=Nfi).

When the input signal Si is switched to another signal and the frequency fi changes, the phase comparator 1 outputs the human input signal frequency fi and the output signal S. A beat signal corresponding to the frequency difference with the frequency rN (=fo/N) of 4 is output, and a DC error voltage Sc due to the phase difference is output from the charge pump 2. This DC error voltage Sc has a high frequency component removed by a loop filter 3, and is inputted to the VCO 4 as a voltage control signal Sd.

Further, the voltage control signal Sd is inputted to a fluctuation value detector 2l having a low-pass filter configuration, converted into a voltage signal corresponding to the fluctuation amount, and inputted to the comparator 22. The comparator 22 compares this voltage signal with a reference value Vr, and supplies a signal corresponding to the difference to the VCO 4 as a voltage control signal Sd.

The VCO 4 receives a voltage control signal SdI input from the loop filter 3 and a voltage control signal S input from the comparator 22.
dt, the capacitances of varactor diodes 42 and 43 are changed to control the oscillation frequency fo of the oscillation circuit 4l. In this case, the voltage control signal Sd is maintained at a level centered on the power supply voltage of the amplifier of the loop filter 3,
The voltage control signal sag is controlled so that the voltage control signal Sd approaches the center of the operating range.

The output signal So of the VCO 4 obtained in this way is divided into 1/N by the frequency divider 5, and then the phase comparator 1
is entered as . This series of operations continues until the PLL circuit locks.

In this way, the oscillation frequency fo of the VCO 4 is determined by the voltage control signal Sd. in addition to the voltage control signal Sd. Since the input signal Si is also controlled by the input signal frequency fi
Even if the value changes significantly, the PLL circuit can quickly capture and
It can be locked in a shorter time than when it is pulled into the range and controlled only by the voltage control signal Sa. In this case, the level of the voltage control signal Sd2 is output such that as the oscillation frequency fo of the VCO 4 approaches the input signal frequency "i", the DC level of the voltage control signal Sd becomes approximately the midpoint of the level variable range, and the PLL circuit After locking, the VCO 4 is controlled only by the voltage control signal Sd.

〔Effect of the invention〕

According to this invention, even if the human signal frequency changes, locking can be performed quickly with a simple configuration, and the P
The present invention can provide an LL circuit and can be applied to a multi-scan television receiver that receives various video signals with different horizontal frequencies.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the PLL circuit according to the present invention, Fig. 2 is a diagram showing the structure of the two-person C○ in Fig. 1, and Fig. 3 is a diagram showing the structure of the conventional PLL circuit. FIG. I... Phase comparator, 2... Charge pump, 3...
・Loop filter, 4...2 human power VC0, 5...
Frequency divider, 2l... Fluctuation value detector, 22... Comparator. Figure 1: 1 block diagram

Claims (1)

[Claims] A fluctuation value detector that detects a fluctuation value of a DC component of a first voltage control signal output from a loop filter constituting a PLL circuit and outputs a voltage signal according to this fluctuation value. , determines whether the voltage signal is greater than or equal to a predetermined reference value, and if it is greater than or equal to the reference value, outputs a control signal proportional to the voltage signal to the PL.
A PLL circuit comprising a comparator that supplies a second voltage control signal to a voltage controlled oscillator of an L circuit, and controlling the oscillation frequency of the voltage controlled oscillator by the first and second voltage control signals. .