KR100677202B1 - Adaptive clock generation apparatus for high definition television - Google Patents

Abstract

The present invention relates to an adaptive clock generator of a high-definition digital TV, and there is a problem in that the NTSC signal and the ATSC signal cannot be simultaneously processed by a conventionally generated clock. Accordingly, the present invention provides a first clock for generating a first clock for processing an ATSC signal in a designated mode by setting a frame rate and an output format using an external synchronization signal input from the outside and a vertical synchronization signal generated internally based on the external synchronization signal. A second clock generating means and a second clock for processing the NTSC signal by changing the frame rate by receiving the vertical synchronizing signal generated by the first clock generating means and the vertical synchronizing signal generated by the first signal; It is provided with a clock generating means, which corresponds to various output formats of the ATSC signal, so that it can be applied to a set corresponding to various formats, and is more effective in a system capable of simultaneously processing an NTSC signal.

Description

ADAPTIVE CLOCK GENERATION APPARATUS FOR HIGH DEFINITION TELEVISION

1 is a block diagram of a clock generator of a conventional high-definition digital TV.

FIG. 2 is a detailed configuration diagram of PLL (PLL) in FIG. 1.

Figure 3 is a block diagram of the adaptive clock generator of the present invention high-definition digital TV.

FIG. 4 is a detailed configuration diagram of the first clock generation PLEL (PLL1) in FIG. 3.

FIG. 5 is a detailed configuration diagram of a second clock generation PLEL (PLL2) in FIG. 3.

***** Explanation of symbols for the main parts of the drawing *****

21,31: Phase comparator 22,32: Low pass filter

23,33: voltage controlled crystal oscillator 24,25,34,35: divider

100: first clock generator 200: second clock generator

PLL1: PL for first clock generation PLL2: PL for second clock generation

The present invention relates to an adaptive clock generator of a high definition digital TV for providing a clock that is adaptable to a frame rate and an output format of an input video signal in a high definition digital TV (HDTV). In particular, the present invention relates to an adaptive clock generator of a high-definition digital TV that provides a clock for simultaneously processing an ATSC signal and an NTSC signal.

FIG. 1 is a block diagram of a clock generator of a conventional high-definition digital TV (HDTV). As shown in FIG. 1, a vertical synchronization signal EXT_V_Sync and an external vertical synchronization signal V_Sync are generated. A phase comparator 11 for generating a phase difference obtained by comparing the phases, a low pass filter 12 for converting the phase difference generated above into a direct current value, and generating a constant clock when inputting the output DC value The voltage controlled crystal oscillator 13 to generate the desired output clock using the clock generated above as an input frequency, and the output clock generated above, The horizontal comparator 15 for generating a synchronization signal H_Sync and the second frequency divider are divided second to generate a vertical synchronization signal V_Sync to generate the phase comparator 1. It consists of a vertical synchronous divider 16 which feeds back 1).

In FIG. 2, the PEL 14 divides the clock provided by the voltage-controlled crystal oscillator 13 into a low frequency, and divides the output clock. Phase comparator 142 for comparing the phases of the clocks of the second divider 145, the first divider 141 and the second divider 145, and outputting the phase difference, and the phase difference outputted above. Low pass filter 143 for low pass to make a DC voltage, a voltage controlled oscillator 144 for oscillating at the input of the DC voltage output from the output to generate an output clock, and the output generated from the voltage controlled oscillator 144 The buffer 146 is configured to buffer and output a clock.

Looking at the prior art configured as described above is as follows.

The phase synchronizer 11 receives the vertical synchronization signal EXT_V_Sync and the internal vertical synchronization signal V_Sync generated from the outside from the phase comparator 11 and compares the phases of the two synchronization signals. Obtain

When the phase difference thus obtained is provided to the low pass filter 12, the low pass filter 12 low-passes the phase difference, converts it into a DC voltage which is an average value, and outputs the result to the voltage controlled crystal oscillator 13.

The voltage controlled crystal oscillator 13 outputs a constant clock (eg, 27 MHz) to the PLL 14 when the DC voltage is input, and the clock is adjusted according to the magnitude of the DC voltage.

The PI 14 generates a constant clock generated by the voltage controlled crystal oscillator 13 as an input frequency and finally generates an output clock.

The horizontal synchronous divider 15 divides the output clock output from the voltage controlled crystal oscillator 13 to generate a horizontal synchronous signal H_Sync, and the vertical synchronous divider 16 is used for the horizontal synchronous divider. The output of the divider 15 is divided again to generate a vertical synchronizing signal V_Sync, which is fed back to the phase comparator 11.

The feedback vertical synchronization signal V_Sync serves as an input signal of the phase comparator 11 to lock the external synchronization signal EXT_V_Sync.

Referring to FIG. 2, when the operation of the PEL 14 is performed, the clock provided by the voltage controlled crystal oscillator 13 is first received by the first divider 141 and divided at a low frequency. It is then provided to the phase comparator 142.

Then, the phase comparator 142 provides the phase difference obtained by comparing the phase of the clock divided by the clock of the second divider 145 with the output clock divided by the first divider 141 to the low pass filter 143. In addition, the low pass filter 143 is low-pass and converted to a DC voltage and output to the voltage-controlled oscillator 144.

Therefore, the voltage controlled oscillator 144 is oscillated by a DC voltage to generate a desired output clock.

By the above operation, a clock required by a high definition digital TV (HDTV) is generated.

However, in the conventional high-definition digital TV (HDTV) as described above, there is a problem in that a clock for simultaneously processing the NTSC signal and the ATSC signal cannot be generated, and therefore the NTSC signal and the ATSC signal cannot be processed simultaneously.

Accordingly, it is an object of the present invention to solve the conventional problems as described above to provide an adaptive clock generator of a high-definition digital TV to provide a clock for processing the ATSC signal and NTSC signal at the same time.

Another object of the present invention is to provide an adaptive clock generator of a high-definition digital TV to provide an adaptive clock according to the frame rate and output format in the case of ATSC.

It is still another object of the present invention to provide an adaptive clock generator of high definition digital TV that provides an adaptive clock according to frame rate in the case of NTSC.

The present invention for achieving the above object is a first clock for processing the ATSC signal in the designated mode by setting the frame rate and output format by using the external synchronization signal input from the outside and the vertical synchronization signal generated internally based on the same A second clock for processing the NTSC signal by receiving a first clock generating means for generating a signal, a vertical synchronous signal generated by the first clock generating means, and a vertical synchronous signal generated by the first signal, and changing a frame rate; It characterized in that it comprises a second clock generating means for generating a.

Hereinafter, with reference to the accompanying drawings in detail as follows.

FIG. 3 is a block diagram of an adaptive clock generator of the present invention, which is a high definition digital TV. As shown in FIG. 3, the external synchronization signal EXT_V_Sync and the vertical synchronization signal V_Sync1 generated from the inside are shown. It is generated by itself with the first clock generator 100 for generating a first clock (clock1) for processing the ATSC signal and the vertical synchronization signal (clock1) generated by the first clock generator 100 The second clock generator 200 receives a vertical synchronization signal clock2 and generates a second clock clock2 for processing the NTSC signal.

Both the first clock generator 100 and the second clock generator 200 are configured in the same configuration as the conventional clock generator, and the first clock generator 100 may adapt to the frame rate and the output format. And a first clock generation PLL (PLL1) for generating a first clock, wherein the second clock generator 200 generates a second clock that can be adapted according to the frame rate. PLEL2 is provided.

As shown in FIG. 4, the first clock generation PLL1 divides the clock (input clock1) oscillated by the oscillator into four different values (Divid 11). -Divid 14), and the divided values of the first and second dividers (Divid 11 and Divid 12) and the third and fourth dividers (Divid 13 and -Divid 14) are input according to the output format. Selects and outputs the first and second multiplexers (MUX 11 and MUX 12) and the first and second multiplexers (MUX 11 and MUX 12) to select one again according to the frame rate. A third multiplexer (MUX 13), fifth to eighth dividers (Divid 21-Divid 24) for dividing the fed back and output clocks into four different values, and the fifth and sixth dividers ( Divid 21, Divid 22) and the fourth and fifth multiplexers (MUX) that select and output one according to the output format by inputting the divided values in the seventh and eighth dividers (Divid 23 and -Divid 24). 21, MUX 22), and a sixth multiplexer (MUX 23) for outputting a value selected through the fourth and fifth multiplexers (MUX 21 and MUX 22) again according to a frame rate, and the third, A phase comparator 41 for comparing the phases of the signals output from the sixth multiplexer and outputting a phase difference, a low pass filter 42 for converting the phase difference to a DC voltage, and oscillating operation at the DC voltage input to perform a desired output. The voltage controlled oscillator 43 generates a clock.

As shown in FIG. 5, the second clock generation PLL2 divides the first and second dividers for dividing an input clock2 generated by an oscillator into two different values. , Divid 32) and a first multiplexer MUX 31 that selects and outputs one of the divided values output from the first and second dividers Divid 31 and Divid 32 according to a frame rate, and is fed back and inputted. The third and fourth dividers (Divid 41-Divid 42) and the third and fourth dividers (Divid 41 and Divid 42) respectively divide the output clocks into two different values. Phase for outputting a phase difference by comparing the phases of the signals selected by the second multiplexer MUX 41 and the first and second multiplexers MUX 31 and MUX 41 respectively according to the frame rate. A comparator 51, a low pass filter 52 for converting the phase difference into a DC voltage, and an oscillation oscillation upon inputting the DC voltage And a voltage controlled oscillator 53 for generating a desired output clock.

Referring to the operation and effect of the present invention configured as described in detail as follows.

The external phase synchronization signal EXT_V_Sync from the outside and the vertical phase synchronization signal V_Sync generated inside are inputted from the first phase comparator 21 to compare the phases of the two synchronization signals to obtain a phase difference.

The phase difference thus obtained is received by the low pass filter 22 to low pass to convert the DC voltage, and when the converted DC voltage is input, the voltage controlled crystal oscillator 23 oscillates to generate a constant input clock 1. It is generated by the clock generation PLEL 24.

Accordingly, the first clock generation PLL1 generates a first clock clock1 capable of processing an ATSC signal.

In addition, the first clock clock1 generated by the first clock generation PLL1 is received from the first divider 24 for horizontal synchronization to divide the first clock signal H_Sync1 to generate a vertical synchronization. The first divider 25 divides the output divided by the horizontal divider 24 and generates a first vertical synchronization signal V_Sync1.

The first vertical synchronization signal V_Sync1 generated as described above is fed back to the first phase comparator 21 and also to the second phase comparator 31.

Then, the second phase comparator 31 compares the phases of the second vertical synchronizing signal V_Sync2 generated by being divided from the first vertical synchronizing signal V_Sync1 and the second clock clock2 for processing the NTSC signal. To generate a phase difference.

The low pass filter 32 and the voltage controlled crystal oscillator 33 perform the same operation as described above to generate the clock input 2 as the PLL2 for the second clock generation.

Accordingly, the second clock generation PLL2 generates a second clock clock2 capable of processing an NTSC signal.

The second clock clock2 generated by the second clock generation PLL2 is inputted from the second divider 34 for horizontal synchronization to divide the second clock 34 to generate a first horizontal synchronization signal H_Sync2. The second divider 35 divides the output divided by the second divider 34 for vertical synchronization to generate a second vertical synchronization signal V_Sync2.

The second vertical synchronization signal V_Sync2 generated as described above is fed back to the second phase comparator 31.

By the above operation, the first clock generation PLL1 of the first clock generator 100 generates the first clock clock1 for processing the ATSC signal and the second clock generator 200. The second clock generation PLL2 generates a second clock clock2 for processing the NTSC signal.

Then, the first clock generation PLL (PLL1) will be described with reference to FIG. 4 as follows.

The voltage control crystal oscillator 23 of the first clock generator 100 receives a predetermined clock (input clock1) from the first to fourth dividers Divid 11-Divid 14 and divides and outputs the divided clock to different values.

That is, it divides into frequencies suitable for each of 59.94Hz / 1080I, 59.94Hz / 540P, 60Hz / 1080I, and 60Hz / 540P.

Thereafter, the first multiplexer MUX 11 receives the outputs of the first divider Divid 11 and the second divider Divid 12 as inputs, and the third divider Divide 13 and the fourth divider ( The output of Divid 14) is taken as input by the second multiplexer (MUX 12).

The first multiplexer (MUX 11) and the second multiplexer (MUX 12) receiving the inputs select one of two inputs according to the output format (e.g., 1080I and 540P) and provide it to the third multiplexer (MUX 13). .

Accordingly, the third multiplexer MUX 13 selects one of the two inputs according to the frame rate (for example, 59.94 Hz and 60 Hz) and provides it to the phase comparator 41.

At this time, the fifth to eighth dividers Divid 21-Divid 24 receive the first clock (clock1) output through the output terminal and divide the divided values to have different values, and divide the divided values into fourth to sixth multiplexers (MUX). 21-MUX 23 selects one of the divided values according to the output format and the frame rate and outputs the same to the phase comparator 41.

Then, the phase comparator 41 compares the phases of the two clocks output from the third multiplexer MUX 13 and the sixth multiplexer MUX 23, obtains a phase difference, and converts the phase difference into a DC voltage in the low pass filter 42. When provided to the voltage controlled oscillator 43, the voltage controlled oscillator 43 generates a first clock (clock1) for processing a constant clock, that is, the ATSC signal.

As a result, the first clock clock1 for processing the ATSC signal is appropriately adjusted according to the output format and the frame rate and output.

As shown in FIG. 5, the second clock generation PLL2 of the second clock generator 200 includes a second clock (not related to the output format of the second clock generator PLL2) depending on the frame rate. clock2) is adjusted and output, and the operation thereof is the same as in FIG.

As a result, since it corresponds to various output formats of the ATSC signal in the high-definition digital TV, it can be applied to the set (SET) corresponding to the various formats, and the NTSC signal can be processed together, thereby achieving a greater effect.

As described in detail above, the present invention simultaneously locks an ATSC signal and an NTSC signal, and outputs a clock suitable for a frame rate and an output format. Therefore, since the ATSC signal corresponds to various output formats, the ATSC signal can be applied to a set corresponding to various formats, and is more effective for a system that can simultaneously process NTSC signals.

Claims (5)

A first clock generating means for generating a first clock for processing the ATSC signal in a designated mode by setting a frame rate and an output format by using an external synchronization signal input from the outside and a vertical synchronization signal generated internally therefrom; A second clock generation means for generating a second clock for processing the NTSC signal by receiving a vertical synchronization signal generated by the first clock generation means and a vertical synchronization signal generated by itself based on the vertical synchronization signal; An adaptive clock generator of a high definition digital TV, characterized in that configured to include. The method of claim 1, wherein the first clock generating means comprises a first clock generating PEL that generates a first clock which can be adapted according to a frame rate and an output format. Adaptive clock generator of high definition digital TV. 3. The PLL of claim 1, wherein the first clock generation PEL includes first to fourth dividers for dividing the internal clock generated by the voltage controlled crystal oscillator into four different values, and the first and second dividers. The first and second multiplexers and the first and second multiplexers for selecting and outputting one according to an output format by inputting the divided values in the third and fourth dividers, respectively. A third multiplexer which selects and outputs one of the selected values again according to the frame rate, and a fifth to eighth divider which divides the output clock fed back and input into four different values; A fourth and fifth multiplexers configured to select one of the fifth and sixth dividers, the seventh and eighth dividers as inputs, and to output one selected according to an output format; Prepress the selected value through the fifth multiplexer. A sixth multiplexer for selecting and outputting one again according to the threshold and a phase comparator for outputting a phase difference by comparing phases of signals output from the third and sixth multiplexers, and a low pass for converting the phase difference into a DC voltage And a filter and a voltage controlled oscillator for generating a desired output clock by performing an oscillation operation when the DC voltage is input. The high definition digital TV adaptive type according to claim 1, wherein the second clock generating means comprises a second clock generation PEL that generates a second clock that can be adapted according to a frame rate. Clock generator. 5. The PLL of claim 4, wherein the second clock generator PEL divides the internal clock generated by the voltage controlled crystal oscillator into two different values, respectively, and the first and second dividers. A first multiplexer for selecting and outputting one of the divided values respectively output according to the frame rate, and a third and fourth divider for dividing the feedback clock inputted into two different values; A phase for outputting a phase difference by comparing a phase of a signal selected from the first and second multiplexers with a second multiplexer for selecting and outputting one according to the frame rate by inputting values divided in the fourth divider A comparator, a low pass filter for converting the phase difference into a DC voltage, and a voltage controlled oscillator for generating a desired output clock by performing an oscillation operation when the DC voltage is input. Is an adaptive clock generator of high definition digital TV.

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