JPH06291651A - Pll circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the PLL circuit capable of stably providing a clock output covering over a wide band and having high response speed by switching the oscillation band of a VCO while multiplying the output of frequency dividing ratio of a programmable frequency divider by the detected result of a horizontal synchronizing frequency detector. CONSTITUTION:Frequency dividing ratio setting data Dn for deciding a PLL output frequency are inputted to a programmable frequency divider 6, and a set frequency dividing ratio (a) is sent to a synchronizing frequency detector 1. Then, the result of applying the digital frequency conversion of the cycle to a horizontal synchronizing pulse fH of an input image signal is sent to a multiplier 2 by being combined with the set frequency dividing ratio (a). The result is sent to a decoder 3 for selecting the oscillation frequency band of a VCO 5 as the arithmetic result of the multiplier 2, and the oscillation frequency band of the VCO 5 is decided through a band switcher 4 by the decoder 3. An output pulse (c) of the VCO 5 is sent to a frequency divider 6, and an output (b) is converted from phase difference to voltage by a phase comparator 7 and fed back through an LPF 8 to the VCO 5 as the control voltage of the VCO 5. By repeating this operation, an output fout is outputted from the VCO 5 as a stable output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called PLL circuit for a liquid crystal display device which is compatible with a plurality of types of synchronizing signal inputs having different scanning line scan rates of image signals (hereinafter referred to as a multi-scanning system).

[0002]

2. Description of the Related Art A conventional PLL circuit has a practical circuit
It can be said that the configuration used in 116436, specifically the configuration shown in the block diagram of FIG. 3, is general.

It divides the reference signal generated from the reference crystal oscillation circuit 101 by a programmable frequency divider 105 which sets a frequency division ratio in order to extract the oscillation output of the VCO 104 as a desired frequency with which the phase is locked,
The frequency-divided output is input to the phase comparator 102 as a signal to be compared, and the phase is compared with the reference signal output of the reference crystal oscillation circuit 101. This result (phase difference) is converted into a voltage V
It is fed back to the VCO 104 as a control voltage of the CO through the low pass filter 103.

As a result, the oscillation output of the VCO 104 controlled by the feedback voltage is returned to the phase comparator 102 again via the programmable frequency divider 105, and the oscillation output of the VCO 104 is the reference signal output of the reference crystal oscillator. Therefore, a phase lock loop that outputs a stable desired frequency without the phase difference between and is established.

This conventional system is suitable for use as an oscillator having a constant channel bandwidth in a predetermined frequency band, as represented by channel control of radio transmitters and receivers. .

[0006]

However, the above-mentioned PLL is used.
In the circuit, a random and variable output clock frequency, which is a specification required for a PLL circuit in a multi-scanning type liquid crystal display device, changes depending on a combination of a horizontal synchronizing period fH of an input image and a frequency dividing ratio of a programmable frequency divider. It was not possible to sufficiently deal with obtaining broadband output.

In the multi-scanning type liquid crystal display device, the reference signal from the reference crystal oscillation circuit is used as the phase comparison reference in the conventional configuration, but it is necessary to use the horizontal synchronizing signal of the input image as the phase comparison reference. This horizontal synchronizing signal has various signal formats in the current range of 10 KHz to several hundred KHz, and the setting range of the programmable frequency divider corresponding to the pixel configuration is also the same. Accordingly, it becomes necessary to support a variable range of hundreds to thousands.

Further, it is indispensable to simultaneously cope with the widening of the band of the VCO and the widening of the stable pull-in frequency of the PLL, but it was almost impossible to realize with the conventional system.

The present invention solves such a problem and is a PL in a multi-scanning type liquid crystal display device.
For the requirement that the output clock frequency, which is the specification required for the L circuit, changes depending on the combination of the horizontal synchronization period fH of the input image and the frequency division ratio of the programmable frequency divider, the output can be obtained in a random and wide band. It is an object of the present invention to realize a PLL circuit which is satisfied and is always stable and has a fast response speed.

[0010]

In order to solve the above-mentioned problems, a PLL circuit for a liquid crystal display device of the present invention comprises a sync frequency detector for detecting a horizontal sync frequency of an input image signal, and a P
A programmable frequency divider capable of arbitrarily setting the frequency division ratio of LL in correspondence with the number of image output pixels of the liquid crystal display device, the frequency division ratio output of the programmable frequency divider, and the detection result of the horizontal synchronizing frequency detector. V having a multiplier for multiplying, a phase comparator, a low-pass filter, and a plurality of oscillation frequency bands
A PLL circuit that can output arbitrary different oscillation frequencies by including a CO, a decoder that selects the oscillation frequency band of the VCO by the output of the multiplier, and a band switch that switches the oscillation frequency band of the VCO. The horizontal synchronizing frequency of the image signal input to the liquid crystal display device and the change in the set value of the dividing ratio of the programmable frequency divider are automatically calculated to switch the oscillation frequency band of the VCO and the PLL. It is characterized by automatically determining the output frequency.

Further, the PLL circuit for a liquid crystal display device having the above-mentioned configuration means is provided with a plurality of low-pass filters having different constants, and the output of the synchronous frequency detector and the output of the multiplier are used as inputs. A filter selector for selectively switching a low-pass filter having an optimum constant from a plurality of low-pass filters is additionally provided, and the filter selector is provided according to the horizontal synchronizing frequency of the input image signal of the liquid crystal display device and the oscillation output frequency of the PLL. The constant switching of the low-pass filter and the oscillation frequency band switching of the VCO are independently and automatically switched.

[0012]

Embodiments Embodiment 1 of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a PLL circuit for a liquid crystal display device according to the present invention, which is an embodiment realizing claim 1.

First, the horizontal synchronizing pulse fH of the input image signal which is the lock reference signal of the PLL circuit is applied to the synchronizing frequency detector 1 and the phase comparator 7, and the synchronizing frequency detector 1 converts the period of fH into a digital frequency. As a result, it is sent to the multiplier 2.

The programmable frequency divider 6 has a PLL.
The frequency division ratio setting data Dn for determining the output frequency is input. The set frequency division ratio a of the programmable frequency divider 6 at this time is sent to the multiplier 2 at the same time, and fH × N
The output frequency of (set frequency division ratio a) = fOUT is output to the decoder 3 which selects the oscillation frequency band of the VCO as the calculation result of the multiplier 2.

The decoder 3 determines the oscillation frequency band of the VCO 5 based on the calculation result of the multiplier 2, and determines the oscillation frequency band of the VCO 5 via the band switch 4.

The output pulse c of the VCO 5 oscillated by this is sent to the programmable frequency divider 6, and the frequency division result output b is phase comparator 7 which determines the phase difference from the horizontal synchronizing pulse fH as a constituent element of the phase comparator. The phase difference is converted to a voltage by the phase discrimination circuit and the charge pump, and V
V as a control voltage of CO5 via the low-pass filter 8
It is fed back to CO5.

By repeating the above feedback operation, f
OUT is phase locked to fH and VC is a stable output.
It is output from O5.

In this description, the structure from the decoder 3 to the band switch 4 to VCO 5 is a variable capacitance diode in which the oscillation frequency variable range of the oscillation circuit which is a component of the VCO 5 is normal. In the VCO, the fMAX / fMIN ratio is limited to 1.5 to 2.0, and the minimum value f of the oscillation output is f.
When MIN is set to 5 MHz, the maximum frequency fma of the variable range
x becomes about 10 MHz, which is provided for the purpose of covering the performance far below the variable output frequency range of 5 to 70 MHz in order to correspond to the PLL output of the multi-scanning type liquid crystal display device of the present invention.

According to the configuration of the oscillation circuit which is the oscillation element of the VCO, a part of L / C and C / R forming the resonance circuit is divided into several bands according to the variable range of the specification request
This is a material that can be realized as a configuration that is switched and used so as to supplement the capacity and capacity ratio of a variable capacity diode incorporated in a part of the combined capacity.

(Embodiment 2) FIG. 2 is a configuration block diagram of a PLL circuit showing an embodiment realizing claim 2 of the present invention.

First, the horizontal synchronizing pulse fH of the input image signal which is the lock reference signal of the PLL circuit is applied to the synchronizing frequency detector 1 and the phase comparator 7, and the synchronizing frequency detector 1 converts the period of fH into a digital frequency. As a result, it is sent to the multiplier 2.

The programmable frequency divider 6 has a PLL.
The frequency division ratio setting data Dn for determining the output frequency is input. The set frequency division ratio a of the programmable frequency divider 6 at this time is sent to the multiplier 2 at the same time, and fH × N
The output frequency of (set frequency division ratio a) = fOUT is output to the decoder 3 which selects the oscillation frequency band of the VCO as the calculation result of the multiplier 2.

The decoder 3 determines the oscillation frequency band of the VCO 5 based on the calculation result of the multiplier 2 and determines the oscillation frequency band of the VCO 5 via the band switch 4.

The output pulse c of the VCO 5 oscillated by this is sent to the programmable frequency divider 6, and the frequency division result output b is the phase comparator 7 which determines the phase difference from the horizontal synchronizing pulse fH as a constituent element of the phase comparator. The phase difference is converted to a voltage by the phase discrimination circuit and the charge pump, and V
As a control voltage for CO5, a low-pass filter 8A or 8
It is fed back to VCO 5 via B.

By repeating this feedback operation, fOU
T is phase locked to fH and VCO is used as a stable output.
5, the input / output characteristics of the PLL configured by the above-mentioned basic path have different theoretical formulas depending on the type of low-pass filter used, such as the gain of the phase comparator and the filter. Is normally calculated by using the gain of, the gain of the programmable frequency divider (1 / N), and the gain of the VCO. According to the required specifications, the calculated step response characteristic satisfies the change of fH input, that is, the response speed of the PLL and the indial response are shorter in various input conditions. It is desirable that the filter selector 9 of this embodiment realizes that by calculating an appropriate low-pass filter value using the input horizontal synchronizing pulse fH and the frequency division ratio setting data Dn of the programmable frequency divider. As an option, it is additionally equipped to the configuration of FIG.

Further, in the present embodiment, the low-pass filters switched by the filter selector 9 are 8A and 8B for convenience.
However, it should be noted that this is increased or decreased according to performance requirements.

[0028]

The PLL circuit for a liquid crystal display device of the present invention comprises:
As described above, in a multi-scanning type liquid crystal display device, a random and wide band clock that is variously changed depending on the combination of the horizontal synchronizing period fH of the input image and the frequency division ratio of the programmable frequency divider required for the PLL circuit. It is possible to realize a PLL circuit in which the oscillation output of the frequency can be taken out very easily (automatically), the output frequency is always stable for different input image signals, and the response speed is fast.

Further, it is an effective means for realizing a multi-scanning type display having a display function similar to that of a CRT by using a liquid crystal display device having a predetermined number of pixels.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment according to claim 1 of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of an embodiment according to claim 2 of the present invention.

FIG. 3 is a circuit block diagram showing a conventional example.

[Explanation of symbols]

 1 Synchronous frequency detector 2 Multiplier 3 Decoder 4 Band switcher 5 VCO 6 Programmable frequency divider 7 Phase comparator 8 Low-pass filter 9 Filter selector 101 Reference crystal oscillator

Claims (2)

[Claims] 1. A synchronous frequency detector for detecting a horizontal synchronous frequency of an input image signal, a programmable frequency divider capable of arbitrarily setting a frequency division ratio of a PLL in accordance with the number of image output pixels of a liquid crystal display device, A voltage-controlled oscillator including a multiplier that multiplies the frequency division ratio output of the programmable frequency divider and the detection result of the horizontal synchronization frequency detector, a phase comparator, a low-pass filter, and a plurality of oscillation frequency bands ( (Hereinafter abbreviated as VCO), a decoder that selects the oscillation frequency band of the VCO by the output of the multiplier, and a band switch that switches the oscillation frequency band of the VCO. A circuit,
The horizontal synchronizing frequency of the image signal input to the liquid crystal display device and the change in the set value of the dividing ratio of the programmable frequency divider are automatically calculated to automatically switch the oscillation frequency band of the VCO and the output frequency of the PLL. A PLL circuit for a liquid crystal display device characterized by being determined. 2. The PLL circuit for a liquid crystal display device according to claim 1, wherein a plurality of low-pass filters having different constants are provided, and the output of the synchronous frequency detector and the output of the multiplier are input to the PLL circuit. A filter selector for selectively switching a low-pass filter having an optimum constant from a plurality of low-pass filters is additionally provided, and the filter selector is provided according to the horizontal synchronizing frequency of the input image signal of the liquid crystal display device and the oscillation output frequency of the PLL. Constant switching of low-pass filter and VCO
2. A PLL circuit for a liquid crystal display device, which automatically switches the oscillation frequency band switching independently.