KR830000983B1 - Dual Phase-Controlled Loop Deflection Synchronization Circuit - Google Patents

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Description

Dual Phase-Controlled Loop Deflection Synchronization Circuit

1 is a configuration and schematic diagram of a television receiver using the present invention.

2 and 3 show various voltages occurring in the receiver of FIG. 1 as amplitude-time waveforms.

The present invention relates to a dual phase-control loop horizontal deflection synchronization circuit.

Television display of broadcast television signals is invented by repeatedly scanning an electron beam on the surface of an image screen. This non-density is modulated such that the video signal forms an image on the screen on which the image is displayed. In order to synchronize the scanning of the beam with display information, the scanning or deflection circuits are synchronized with the synchronizing signal synthesized with the image information in the synthesized video. When a composite signal is received at the television receiver, the composite signal will contain distortions in the form of electrical and thermal noise.

When transmitted, the sync signal pulses are carefully controlled and returned at a completely stable ratio. Since the presence of noise obscures the synchronization signal in any way, it is common practice to use an oscillator to obtain the synchronization of a horizontal deflection circuit with horizontal synchronization signal pulses, the frequency of which is equal to the synchronization signal frequency. Controlled by a fixed loop. Therefore, if any arbitrary sync pulse is unknown by noise, the ratio of the oscillator remains substantially unchanged and the deflection circuit continues to receive normal deflection control pulses.

In normal operation of the television display, the horizontal deflection circuit generates a high voltage pulse to form a relatively fast repeat scan. Typically the very high voltages for operating kinescopes are obtained by rectifying and filtering these high voltages. Often, horizontal deflection circuits are used as a power source to generate low voltages for other circuits in television receivers. It is known that the timing of the retrace pulses generated by the horizontal deflection circuit changes in accordance with the load of the deflection circuit, for example, in accordance with the brightness of the image to be displayed on the kinescope. This change in the timing of the retrace pulse causes distortion in the image to be displayed.

US Patent No. 3891800, filed on June 24, 1975 by some of Jensen, describes a synchronous arrangement in which a second phase control loop is connected to the output of the first phase control loop. The second loop includes a second oscillator and a second phase detector. An integrator coupled to the output of the horizontal deflection circuit integrates the retrace pulses and applies the resulting sawtooth wave to the input of the phase detector which compares the pulses controlled at the average ratio of incoming sync pulses. The short time constant filter connects the output of the second phase detector to a second oscillator for controlling its phase to maintain retrace pulses synchronized with the output of the second phase closed loop. This has the disadvantage that the phase control in the second loop is due to the spacing of the retrace pulses.

Murald Technical Communications No. 118 of April 1973 describes a double loop system in which a sawtooth oscillator is controlled to an average value of the synchronization signals obtained by the first phase locked loop. The second phase control loop is coupled to the sawtooth output of the oscillator. The second phase route includes a controllable phase shifter and a second phase detector. The phase detector responds to the sawtooth output of the oscillator and filters for a short period of time and also controls the pulses of the adjustable phase shifter coupled between the horizontal deflection circuit and the oscillator to maintain retrace pulse synchronization to the average value of the incoming sync signals. Responsive to retrace pulses to provide a signal for use.

It is more preferable in terms of stability to use an oscillator whose frequency is controlled by the inductor and the capacitor than by the resistor and the capacitor. However, considering oscillator operation at the horizontal deflection frequency, large inductors and capacitors are required, which is not only expensive, but also large in shape and tends to extract signals from high output deflection circuits, making the oscillator unstable. Therefore, it is preferable to use small value inductors and capacitors as the frequency determining element of the horizontal oscillator. However, this requires a relatively high operating frequency. With the emergence of integrated circuits, it has been realized to use high-frequency horizontal oscillators with high stability and a series of digital frequency dividers generating horizontal ratios. However, the output of this series of frequency divisions is either a digital or double level signal. This double level signal can be locked at the average time of the incoming sync signals by the first phase closed loop as in Jensen's reference. It is particularly important to reduce the number of intermediate connections between integrated circuits and member elements in realizing integrated circuits because it is required to achieve a given function while doing a lot of signal processing.

According to an embodiment of the present invention, a horizontal synchronizing arrangement for a television display includes a horizontal synchronizing signal source and a horizontal deflection circuit responsive to a drive pulse to generate a deflection current defining a feedback current sweep line and a retrace interval. Include. The deflection circuit also generates variably delayed retrace pulses with respect to the drive pulses as a function of the load of the deflection circuit. This arrangement includes a phase locked loop for providing a stable double level signal that tunes to the average horizontal sync signals. This arrangement also includes a phase control loop to maintain the retrace level in synchronization with the dual level signal. This phase control loop includes a phase detector having a first input coupled to the output of the phase closed loop and a second input coupled to the deflection circuit. The phase control loop drives the phase detector to generate a current of a first polarity when the dual level signal is in the first state and to generate a current of a second polarity when the dual level signal is in the second state. Respond to the retrace pulse driving the phase detector. The phase control loop also includes a loop filter coupled to the output of the phase detector for filtering the first and second polar currents to form a control signal. This phase control loop also includes a phase control device having a control input coupled to a loop filter for providing drive pulses to note retrace pulses tuned with the dual level signal.

Hereinafter, in order to understand the gist of the present invention in more detail and easily, the present invention will be described with reference to embodiments and drawings.

FIG. 1 shows a television receiver and receives a carrier signal from the antenna 10 at the bottom center of the drawing to be connected to the tuner 12. This tuner 12 is an intermediate frequency amplifier and detector that is amplified and demodulated to select a broadcast signal and generate a composite video. The composite video is applied to various luminance and chroma processing circuits shown as block 14 and to the kinescope 16 to display this processing signal. The composite video is also applied to a sync signal divider, shown as a block 18 in which the vertical and horizontal sync signals are separated. These vertical synchronization signals are applied to the vertical deflection circuit 20 to control the deflection current of the vertical deflection winding 22 connected to the kinescope 16.

Horizontal sync signals, represented by waveform 251 in FIG. 2A, are applied from sync signal divider 18 through conductor A to a phase locked loop, shown 30 to the left of FIG. Phase locked loop 030 applies a drive pulse to drive pulse conductor S to the horizontal deflection circuit shown by block 140 at the bottom postal side, and a double level applied through conductors G and G to phase control loop 70. Generate pulses. In addition, the horizontal deflection circuit 140 generates an ultra high voltage for the kinescope 16, and as is well known, the horizontal deflection circuit is variably loaded.

Phase closed loop 30 includes a voltage controlled oscillator as indicated by block 32, which occurs at 503.5 KHz as indicated by 252 in FIG. The oscillator signal is applied to a 32-to-1 splitter including D-type flip-flops (F. F) 34, 40, 46, 52, and 58.

The Q output of the D flip-flop is assumed to be the D (data) state at the falling edge of the signal applied to the C (clock) input. If the Q output of the D flip-flop is connected to the D input, it divides the signal at the clock input of the D flip-flop for two minutes and generates a separate signal at the Q output. Vco signal 242 is divided into two at flip-flop 34 and generates a signal at Q of flip-flop 34 as indicated by 253 of FIG. 2C, which is a pair of conversion amplifiers connected in multiple stages by conductor C. To (36) and (38). The first output 38 a of the conversion amplifier 38 is connected to the clock input of the FF 40 and the second output 38 b is connected to the conductor bus H. FF 40 is divided into two minutes to generate a signal at the Q output as indicated by 254 in FIG. 2 d and coupled as conductor D to the input of conversion amplifier 42. The output 42 a of the conversion amplifier 42 is coupled to the input of the inverter 44 and the output 44 a of the inverter 44 is coupled to the clock input of the FF 46. Flip-flop 46 splits the signal at its clock input into two and generates the signal shown at 255 in FIG. 2 e at the Q output. The Q output of flip-flop 46 is coupled to the input of inverter 48 via conductor E and the output 48 a of inverter 48 is coupled to the input of inverter 50, and the other output 48 b is Is coupled to the conductor bus (H). The output of the inverter 50 is connected to the C input of the FF 52 and the divided signal shown at 256 in the second f diagram is generated at the Q output of the flip-flop 52 and is connected to the converter F by the conductor F. Is coupled to the input of 54). The output 54 b of the inverter 54 is connected to the conductor H and the output 54 a is connected to the input of the inverter 56. The output of inverter 56 is connected to the C input of flip flop 58. The signal labeled 257 in FIG. 2g is generated at the Q output of FF 58 and coupled to the input of inverter 60 and phase control loop 70 through conductor G. The output Q of the FF 58 is also coupled to the conductor H by the buffer amplifier 59. The output of the inverter 60 is the invert 257 of the signal 257 and is coupled to the input of the phase detector 62 and the phase control loop 70 by conductor G.

Phase detector 62 compares signal 257 with horizontal sync signal 251 to generate a control signal that is applied to the loop filter shown by block 64 and directs the control input of VCO 32. . Phase closed loop 30 controls the binary or double level signal 257 on conductors G and G to maintain the transition of waveform 257 synchronized with the average sync pulse signal generated by separator 18. .

As described above, there is a delay due to the load between the time of the horizontal deflection drive pulse and the horizontal synchronizing pulse. This delay is about 90 ° with the horizontal scan and about 1.5 microseconds. The phase control loop 70 includes a controllable phase-shift network or delay circuit 72 to apply the signal generated by the loop 30. The delay of the circuit 72 is driven by the horizontal retrace pulse, and the current of the first and second polarities when the dual level signal 72 generated by the loop 30 becomes the first and second states, respectively. It is controlled by the output of phase detector 92 which provides. The current generated by the phase detector 92 is filtered and applied to the delay circuit 72 to maintain synchronization between the retrace pulse and the double level signal transition.

The phase control circuit 70 includes a retrace pulse type circuit labeled 122 at the bottom right of FIG. 1, a deflection drive period circuit labeled 150 at the top right, and a logic circuit 200 at the top center. Logic circuit 200 generates a drive signal to delay circuit 27 and processes the signals to ensure a pulse output even if delay circuit 72 is at the extreme of its region. The logic circuit 200 includes an inverter 202 having an input coupled to the conductor bus H and an output coupled to the next inverter 204. The output 42 b of the inverter 42 is connected to the output 204 a of the inverter 204 and the synthesized output signal, denoted 259 in FIG. 2 i, is connected through the conductor I of the inverter 194. Is coupled to the input. In the same way, the output 44b of the inverter 44 is coupled to the output 204b of the inverter 204 and the signal labeled 260 in FIG. 2i is input to the inverter 196 via conductor J. FIG. Is coupled to. Signals 259 and 260 have a fixed time relationship with signal 257. Output 196a of inverter 196 is denoted as 178 and is coupled to the input of a flip-flop that includes inverters 180 and 182. The output of inverter 180 is coupled to the input of inverter 182 and the output 182 a of inverter 182 is coupled to the input of inverter 180. Output 194a of inverter 194 is coupled to an input of inverter 812. The output of FF 178 appears on conductor K connected to output 182 b of inverter 182.

Output 196a of inverter 196 is coupled to the input of inverter 186 and is transversely coupled with inverter 188 to form flip-flop FF 184. This stabilizes the output of FF 184.

The signal labeled 263 in FIG. 2m is generated at the output 194b of the inverter 194 and is connected to the input of the inverter 192 by conductor M. FIG. The input of the inverter 192 is also coupled to the collector of the NPN transistor 91 at the output of the delay circuit 72.

The signal labeled 264 in FIG. 2n is generated by the inverter 192 and is connected to the input of the inverter 190 via conductor N. FIG. The output of inverter 190 is coupled to the input of inverter 188 of FF 184. And the output 196 C of the inverter 196 is coupled to the input of the inverter 190.

The output signal of FF 178 is connected to the base of NPN transistor 74 by conductor K. The base of transistor 74 is also biased from B ⁺ through resistor 75. The collector-emitter passage of transistor 74 is connected via conductor L across a ramp capacitor 78 for periodic discharge. Capacitor 78 receives the charging current from B ⁺ through resistor 80.

The periodic ramp generated across the capacitor 78 is coupled to the base of the NPN transistor 86 of the comparator, denoted 82. Comparator 82 includes an NPN transistor 84 in which the emitter of transistor 86 and the emitter of transistor 84 are coupled to B ⁺ through a resistor 88. The collector of transistor 86 is grounded. .

The collector of transistor 84 is connected to the base of transistor 91 and grounded through resistor 90. The base emitter junction of transistor 91 is coupled across resistor 90 to couple the delayed signal to the input of inverter 192.

The output of FF 184 is connected by the conductor 0 to the C input of FF 174 of deflection drive period circuit 150. The Q output of the FF 174 is coupled to the input of the inverter 176 and the output 176 a is connected to the D input of the FF 174 and the other output 176 b is connected to the NPN switch transistor by the conductor P. 156 is coupled to the base. Outputs 176 a and 176 b generate signals that are in phase with the Q output of FF 174. The base of transistor 156 receives a bias current from B ⁺ through resistor 158 and the collector-emitter path is coupled by conductor Q across lamp capacitor 152. Capacitor 152 is charged from B ⁺ by resistor 154. The recurrent ramp output of capacitor 152 is coupled to the base of NPN transistor 168 of the comparator, denoted 160. PNP transistor 162 has an emitter coupled to B ⁺ by an emitter and resistor 166 of transistor 168. The collector of transistor 16 is grounded and the base is connected to the needle of potentiometer 1164 missing between B ⁺ and ground to adjust the deflection drive period. One output is taken from comparator 160 across resistor 170 coupled between the collector of transistor 168 and ground. Resistor 170 is coupled across the base emitter junction of NPN transistor 172 and the Q output of transistor 172 is coupled to input of conversion amplifier 144 by buffer amplifier 146. The output of the conversion amplifier 144 is coupled to the input of the horizontal deflection circuit 140 by conductor S.

The retrace pulse generated by the horizontal deflection circuit 140 is coupled to the retrace pulse circuit 122 by the conductor S in response to the deflection drive on the conductor. The circuit 122 includes a voltage divider 123 composed of resistors 124 and 126.

The base emitter junction of transistor 128 is coupled across resistor 126. The collector of transistor 128 is connected to the base of load 132 and the emitter of transistor 132 is grounded. The collector of transistor 132 is coupled to B ⁺ by load resistor 134. The collector of transistor 132 is coupled to the anode of diode 136 and the cathode of diode 136 is grounded. A base emitter junction of NPN transistor 98 representing the input of phase detector 82 is coupled across diode 136. The collector of transistor 98 is coupled to the emitters of NPN transistors 94 and 96 to supply current. A voltage divider 100 comprising resistors 102 and 104 is coupled between B ⁺ and ground. Bases of transistors 94 and 96 are coupled to vertices on divider 100 by resistors 106 and 108 to bias. The collector of transistor 94 is coupled to the collector of transistor 96 by a current reflector, denoted 109. Reflector 109 includes PNP transistor 110 and the base of transistor 110 is coupled to the collector of transistor 94 and coupled to the collector of PNP transistor 112. And is coupled to B ⁺ through a series connection of resistor 116 and diode 118. The emitter of transistor 112 is coupled to B ⁺ by resistor 114. The collector of transistor 110 is coupled to the collector of transistor 96 to form the output terminal of phase detector 92. The output of the phase detector 92 is coupled to the base of the transistor 84 by conductor μ. The filter capacitor 120 phases the delay circuit 72 to form a phase control signal to control the deflection drive in such a way as to hold the horizontal retrace pulses synchronized with the double level signal 257 on conductors G and G. Coupled between conductor μ and ground to filter out the current generated by detector 92.

The detailed operation of the arrangement of FIG. 1 is very well explained in connection with the waveform of FIG. The waveforms shown in FIGS. 2 a to 2 t show the voltage waveforms on the conductors of FIG. 1 indicated by the corresponding letters. Generally speaking, PLL 30 generates signal waveforms 259 and 260 at the time associated with mutual waveforms 257 and 257. The logic circuit 200 generates a signal 265 applied to the deflection driving period circuit 150 by applying the signals 259 and the delay circuit 72 to the signal 260. The period circuit 150 generates a driving pulse for a predetermined period and applies it to the horizontal deflection circuit 140. The deflection circuit generates a retrace pulse and compares it with the 257 signal in the phase detector 92. Any phase deviation generates an error signal that controls the delay circuit 72 to reduce the deviation.

In operation, VCO 32 generates a 503 KHz pulse 152 and a series of counters of PLL 30 continuously generate waveforms 253 to 257. Phase detector 62 controls VCO 32 to maintain the negative transition of signal 257 that coincides with time T ₀ of the center of horizontal sync pulse 251 in response to signal 257 in a known manner. . The voltage of conductor H is dropped to the lower negative value corresponding to logic 0 by the outputs 38, 48, 54 or buffer 59 of the inverters. If it does not descend, it will remain high (logic 1). Bus H will also be negative during these intervals when signal 253 or 257 is negative and signal 255 or 256 is positive. Therefore, signal 258 remains negative at intervals T ₀ -T ₁ , T ₇ -T _8, and T ₉ -T ₁₀ .

The signal 259 on the conductor will be negative when signal 258 on conductor H is negative and signal 254 on conductor D is positive. Therefore, signal 259 on conductor I becomes positive only during the period T ₆ -T ₇ . Likewise, conductor J phase mutual 260 is negative when signal 254 or 258 is negative and causes signal 260 to be positive only during periods T ₇ -T ₈ . At interval leading time T ₅ , FF 178 is in a state where signal 261 on conductor K is low.

At time T ₇ , signal 259 on conductor I is high and input of inverter 182 is low, so 178 is switched and generates logic 1 on conductor FF. The switched state is maintained until a later time T ₈ , at which time signal 260 on conductor J becomes positive and resells FF 178. Therefore, a pulse is generated on the conductor K in the period T ₇ -T ₈ associated with the fixed time of the fixed time T ₀ . The pulse of signal 261 causes the transistor 74 to conduct and discharges the capacitor 78 within the period T ₅ -T ₈ to generate a ramp voltage. At time T ₈ , transistor 74 is in a non-conducting state and the ramp voltage, indicated at 262 in FIG. 2, starts on conductor L. FIG. At instantaneous intervals after T ₈ , transistor 86 of comparator 82 is conducting and transistor 84 is not conducting. Successively, the transistor 91 is not conductive.

The ramp voltage 262 is increased until reset by the pulse 261 which follows. At the same time as T ₄ , the ramp voltage 262 becomes equal to the output voltage of the phase detector 92 and the comparator 82 drops the voltage of the conductor M shown in FIG. 2m with the transistor 91 conducting. Is switched to. Inverter 192 converts signal 293 to form a signal shown at 264 of FIG. 2n on conductor N. FIG. FF 184 is therefore switched on, starting a negative polarity pulse on conductor 0, indicated by 265 in FIG. Time T ₄ defines the start time of the drive pulse applied to the horizontal deflection circuit 140.

Just before time T ₄ , the FF 174 of the deflection drive period circuit 150 is in a reset state with a low Q output and a high Q output. The negative transition of the signal 265 applied to the clock input at time T ₄ sets FF 174. The Q output is lowered and a positive polarity drive pulse (shown as waveform 269 in FIG. 2S) appears on conductor S due to inverter 144. At the same time, the Q output becomes logic 1 and the output of inverter 176 on conductor P goes to logic 0, shown as voltage waveform 266 in FIG. In logic 0, the base emitter junction of transistor 156 as conductor P is non-conductive and capacitor 152 begins to charge, forming a ramp, denoted 267 in FIG. The ramp voltage rises to T _10, where the ramp voltage is equal to the reference voltage applied to transistor 162. At time T ₁₀ , comparator 160 switches transistor 172 to be in a non-conductive state, so the voltage on conductor R is raised to form the pulse shown as second r-waveform waveform 268. Logic 1 on conductor R resets FF 174 to bring transistor 156 into a conductive state and discharge capacitor 152 for the next cycle of operation. Resetting of FF 174 at time T ₁₀ stops the deflection drive pulse 269 applied to deflection circuit 140. A little later, the retrace pulse indicated by 270 in FIG. 2t is generated by the deflection circuit 140. As shown, retrace pulse 270 is delayed for about seven periods of 503 KHz pulses, or 14 μs.

The remaining portion of the loop will be described in conjunction with the third diagram showing the waveform at time T ₀ with the time scale different from the illustration of FIG. The horizontal retrace pulse 270 generated by the deflection circuit 140 on the conductor T is shown in FIG. 3A at intervals T ₁₂ -T ₂ . The retrace pulse 270 starts at time T ₁ ² in response to the termination of the drive pulse 269 at time T ₁₀ . 3B and 3C show signals 257 and 257 applied to phase detector 92 on conductors G and G. FIGS. Pulse 270 is amplified and clipped by pulse shaping circuit 122, and the resulting pulse at the collector of transistor 132 is shown by VC 132 in FIG. 3d. The leading end of pulse VC 132 occurs at time T ₁₃ and the continuation occurs at T ₁ . Transistor 98 responds to pulse VC 132 as a collector current in terms of pulse amplitude. Since the pulse amplitude is constant, transistor 98 generates a collector current pulse of constant amplitude, indicated as IC 98 in FIG. 3E. This collector current is applied to transistors 94 and 96.

One of transistors 94 and 96 conducts the current drawn from transistor 98 due to the applied base voltage. As shown in FIG. 3, the voltage 257 applied to the base of the transistor 94 at the interval leading time T ₀ is more aggressive than the voltage 257 applied to the base of the transistor 96. As a result, transistor 94 is conducting except transistor 96 as shown by IC 94 and IC 96 at 3f and 3g degrees at intervals T ₁₃ -T ₀ . The conductivity of the transistor 94 is equivalent to that of the transistor 110 of the current reflector 109. Current flow in transistor 110 charges capacitor 120 with the current shown as positive current I 120 in FIG. As is known, a constant total current flowing in the condenser 2120 within time T ₁₃ -T ₀ is generated within the increasing positive lex voltage shown by VC 120 in FIG. 3i.

At time T ₀ , voltage 257 becomes more positive than 257 and transistor 96 is conductive except transistor 94 as shown as collector current IC 94 and IC 96. The conduction by the transistor 96 causes the discharge current in the capacitor 120 to discharge the capacitor indicated by the negative current I 120 in FIG. 3h to be equal to the charging current described above. As is known, in the period T ₀ -T ₁ , the constant discharge current flow in the capacitor 120 is such that the voltage of the voltage shown by VC 120 in FIG. 3i is charged by transistors 94, 110, and 112. To be reduced at a rate such as As a result, with the retrace pulse interval T ₁₂ -T ₂ concentrated at the time when the transition of the signal 257 occurs, the capacitor 120 is neither charged nor discharged and the reference voltage applied to the comparator of the delay circuit 72 is not changed. It is maintained without.

When the load of the deflection circuit 140 is increased, the retrace pulse is further delayed at intervals such as T ₁₄ -T ₃ as indicated by the dashed waveform 302 of FIG. 3A. In this selection the collector current flows in the transistor 68 during the start interval T ₁₄ -T ₃ , as indicated by dashed waveform 304 in FIG. 3E. Current will flow in transistors 94 and 110 for an interval -T ₀ and will flow for an interval T ₀ -T ₃ further in transistor 96. As a result, the interval during which the capacitor 120 is discharged will be larger than the interval during charging. As indicated by the dashed waveform 310 in FIG. 3i, the imbalance in the charge and discharge is caused at the larger negative voltage remaining on the conductor 120 after the comparison interval. When this larger negative voltage is applied to the comparator 82 as a reference, this negative voltage causes the time T ₄ to be generated faster during the double current period, thereby causing the driving pulse 269 to start faster, and driving Compensates for an increase in delay T ₁₀ -T ₁₀ between the end of the pulse and the required center of the retrace pulse spacing.

The described invention provides frequency control of the phase and horizontal deflection circuits to maintain synchronization regardless of the retrace pulse period synchronized with the average time of the synchronization signal and the reversal of the retrace pulse period with changes in the load of the horizontal deflection circuit. Since a small number of elements are used, the arrangement is more reliable than the conventional one.

The connection of logic circuit 200 as described above may be applied in the case of high speed logic and those skilled in the art will appreciate that modification is required in the case of medium speed logic circuits such as in-junction logic. have. In particular, conductors i and j must be connected to the inputs of transducers 196 and 194 respectively to compensate for the phase shift of the I ₂ L heroes. As is known to those skilled in the art, an adjustable oscillator can be used in place of delay circuit 72, logic 200 and pulse width control circuit 150, thus driving a horizontal deflection circuit as shown in FIG. 2S. Provide pulses and exclude the waveforms of 2h to 2r degrees.

Claims (1)

A variable deflection retrace with respect to the drive pulses by generating a deflection current that forms a recurrent trace and a regression interval by consisting of a horizontal synchronization signal source and a horizontal deflection circuit responsive to the drive pulse. In a horizontal synchronizing arrangement for a television display device which generates a pulse, an input of the phase lock loop 30 is connected to the synchronization signal source, and its output is a phase lock loop 70 as a triple level signal 257. A phase detector (92) connecting the first input to the output of the phase locked loop (30) and the second input to the deflection circuit (140), and the phase A dual-phase control loop horizontal deflection synchronizing circuit comprising a loop filter 120 connected to an output of a detector and a phase control circuit 72 that allows a control input to be connected to the loop filter 120.

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