JPH1055161A - Pll circuit for digital video processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To output the optimum reference synchronizing signal by comparing a horizontal synchronizing signal and s specific comparison signal to detect the lock/unlock in a phase locked group, and outputting the comparison signal to the inside when the circuit is locked and the horizontal synchronizing signal when unlocked. SOLUTION: In synchronization with the horizontal synchronizing signals inputted from an image reproducing device, a phase locked loop(PLL) circuit 35 generates system clocks 15 which have a frequency equal to an integer multiple of that of the above signals and feeds back comparison signals 6 divided in frequency to an integer submultiple of that of the system clocks. And a circuit 9 of the PLL circuit 35 detects the lock/unlock condition by comparing the horizontal synchronizing signal 14 with the comparison signal 6, and a reference synchronizing signal generating circuit 8 outputs the comparison signal 6 as the reference synchronizing signal 16 in the case of locked conditions and the horizontal synchronizing signal 14 in the case of unlocked conditions. Thus, the optimum reference synchronizing signal is outputted and undesirable phenomena such as unfixed video images are prevented even in the cases of unlocked conditions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit (Phase Locked Loop) for a digital video processing device,
In particular, the present invention relates to a PLL circuit that can minimize a disturbance of an image when the PLL circuit is unlocked or locked.

[0002]

2. Description of the Related Art Like a PDP (Plasma Display Pannel) display device and an LCD (Liquid Crystal Display) display device, a horizontal synchronizing signal and a vertical synchronizing signal supplied in analog form and a video signal of a predetermined timing based on them Accordingly, a digital video processing device that internally performs digital processing uses a PLL circuit to generate an internal clock signal synchronized with a horizontal synchronization signal or the like.

An analog video signal input by a system clock having a frequency that is K times the horizontal synchronization signal generated by the PLL circuit and a reference synchronization signal that is a comparison signal obtained by dividing the system clock by 1 / K. Is sampled, converted into a digital signal, and an image is displayed via each drive circuit of the display panel. By doing this,
At the time of locking, the reference synchronizing signal, which is phase-synchronized with the horizontal synchronizing signal, and the system clock can be completely one-to-one synchronized, and the video signal can be sampled and displayed accurately.

[0004]

However, for example, when the channel of the television is switched, the mode is switched between the video mode and the television mode, or the multi-scan mode is switched on the monitor side, the input horizontal synchronizing signal. And the phase of the vertical synchronizing signal changes. Immediately after the switching, the PLL circuit becomes out of lock. Of course, the frequency of the system clock is changed and controlled according to the phase difference by the voltage control frequency generation circuit (VCO) in the PLL circuit, and the lock is pulled in. Until then, the unlock state continues and the image is displayed on the display screen. The phenomenon that flows or occurs.

To solve the problem, it has been proposed that the image is not output to the screen when the lock is released. However, the phenomenon that the screen becomes black even temporarily is not a preferable solution.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a PLL circuit capable of outputting an optimum reference synchronization signal even when a PLL circuit in a digital video processing device loses lock. .

Another object of the present invention is to provide a digital video processing apparatus capable of preventing undesired phenomena such as a video flow even when an unlocked state is attained.

[0008]

According to the present invention, a clock signal having a frequency which is an integral multiple of the supplied horizontal synchronizing signal is output, and the clock signal is divided into a fraction of the integer. In a phase locked loop circuit for a digital video processing device for generating the clock signal phase-synchronized with the horizontal synchronization signal by feeding back the compared comparison signal, the horizontal synchronization signal is further compared with the comparison signal. A lock / unlock detection circuit for detecting a lock state and an unlock state of the phase locked loop circuit, and when the lock / unlock detection circuit detects the lock state, the comparison signal is internally referred to. A reference sync signal is output as a sync signal, and when the unlock state is detected, the horizontal sync signal is output as the reference sync signal. It is achieved by providing a phase locked loop circuit for digital video processing apparatus characterized by comprising a circuit.

With such a configuration, a comparison signal in a locked state and a horizontal synchronization signal supplied from the outside in an unlocked state are used as a reference synchronization signal serving as a reference for an internal horizontal synchronization signal. Will be. Therefore, even in the unlocked state including the retracted state, the external horizontal synchronizing signal that maintains the phase relationship with the video signal is used as it is for the internal horizontal synchronizing signal. Can be prevented.

According to the present invention, a horizontal synchronizing signal, a vertical synchronizing signal and an analog video signal at a predetermined timing based on the synchronizing signal are supplied from the outside, and a digital video signal is generated internally. In a digital video processing device for displaying an image, a clock signal having a frequency that is an integral multiple of the horizontal synchronization signal is output, and a comparison signal obtained by dividing the frequency of the clock signal by 1 is fed back to the horizontal synchronization signal. A phase-locked loop circuit for generating the clock signal phase-locked to the phase-locked loop circuit, and when the phase-locked loop circuit is in a locked state, generate an internal horizontal synchronization signal based on the comparison signal; In the state, a generating circuit for generating an internal horizontal synchronizing signal based on the external horizontal synchronizing signal; Achieved by providing a digital video processing device having an analog / digital conversion circuit that samples the analog video signal and generates a digital video signal, and a display unit that performs video display according to the digital video signal and an internal horizontal synchronization signal. Is done.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. However, it goes without saying that the technical scope of the present invention is not limited to the following embodiments.

FIG. 1 is a block diagram schematically showing the entire digital video processing apparatus. The input terminal 30 is connected to an external image reproducing device, for example, a video tape recorder (V
TR) The composite signal 31 from the device is input.
The composite signal 31 is input to an RGB separation circuit 32 and separated into R, G, and B analog signals. At the same time, the composite signal 31
Is separated into a horizontal synchronizing signal (EHD) 14 and a vertical synchronizing signal 38.

As described above, based on the horizontal synchronizing signal (EHD) 14 input from an external image reproducing apparatus,
The PLL circuit 35 generates a system clock signal (CLK) 15 having an integral multiple frequency in synchronization with the horizontal synchronization signal (EHD) 14. The system clock signal 15 generated by the PLL circuit 35 is used for sampling and A
It is supplied to an A / D conversion circuit 33 for performing / D conversion (analog / digital conversion) and a display unit 36. The PLL circuit 35 will be described in detail later with reference to FIG.

The A / D conversion circuit 33 samples analog RGB signals at the timing of the system clock signal 15 and converts each sampled analog signal into a digital signal of a predetermined bit. The sampling timing is set, for example, in the display unit 36.
When the PDP device is used, the timing is set to the time obtained by dividing the time for scanning one screen by the number of dots of one screen. Then, the RGB digital signals extracted at that timing are supplied to the display unit 36, and the internally generated horizontal synchronization signal (output of 37) and vertical synchronization signal (output of 39) and the system clock signal 15 are output.
The display is driven by the display unit 36 in accordance with the electrode driving method of the PDP device. Therefore, if the phase synchronization with the external synchronization signal is lost, disturbance such as the flow of the image on the screen occurs. Also, when a liquid crystal display panel is used, the display is driven in the same manner.

In the digital video processing apparatus, a comparison signal obtained by dividing the system clock signal 15 generated by the PLL circuit by a factor of 1 as described above is used as a reference synchronization signal (SYNC) 16. The horizontal timing signal generation circuit 37 generates a necessary horizontal timing signal in the display unit 36. Further, a vertical timing signal signal is generated by a vertical timing signal signal generation circuit 39 from the vertical synchronization signal 38 separated from the composite signal 31 and the horizontal timing signal. Then, the horizontal and vertical timing signal signals are supplied to the display unit 36, respectively.

In this embodiment, the comparison signal is used as the reference synchronization signal (SYNC) 16 to the inside when the PLL circuit is in the locked state as described above. The supplied horizontal synchronization signal (E
HD) 14.

FIG. 2 is a block diagram showing the internal configuration of the PLL circuit 35 in FIG. FIG. 3 shows the PLL circuit 3
FIG. 6 is a timing chart for explaining how the reference synchronization signal (SYNC) 16 is switched by 5.

The horizontal synchronizing signal (EHD) 14 separated from the composite video signal by the synchronizing separation circuit 34 is input to the PLL circuit 35 shown in FIG. As outputs, a system clock (CLK) 15 and a reference synchronization signal (SYNC) 16 are output. Reference numeral 2 denotes a phase comparison circuit which compares the phase of a horizontal synchronizing signal EHD input from the outside with a comparison signal (VHD) 6 obtained by dividing the system clock CLK by 1 / K (K is an integer) to obtain a phase difference. Outputs the corresponding signal. Reference numeral 3 denotes an integration circuit or a low-pass filter, which supplies the integrated value of the output of the phase comparison circuit 2 to the voltage controlled oscillator 4 as a control voltage. Then, the voltage controlled oscillator (VCO) 4 generates a clock signal having a frequency corresponding to the phase difference, and outputs it as a system clock (CLK) 15. Therefore, a portion 10 surrounded by a broken line is a portion of a conventional general PLL circuit. Conventionally, the comparison signal (VHD) 6 obtained by dividing the system clock CLK is used as it is as the internal reference synchronization signal (SYNC) 16.

The PLL circuit shown in FIG. 2 detects the edge of an external horizontal synchronizing signal EHD and detects the system clock CLK.
A circuit 7 for outputting a pulse signal having one pulse width of
Circuit 9 for determining whether the circuit is locked or unlocked
And a reference synchronization signal generation circuit 8 for selecting and outputting either the comparison signal VHD or the external horizontal synchronization signal EHD according to the output of the determination circuit 9.

An outline of the operation will be described with reference to FIG. 3. In the PLL operation in the normal locked state, for example, during the comparison period of two pulses generated from the comparison signal VHD6, the external horizontal synchronization signal EHD is output. The lock / unlock determination circuit 9 determines whether or not the level becomes the L level. P
In the LL circuit, because of its feedback operation, the phase of the output system clock is accompanied by a kind of fluctuation called jitter. Therefore, the horizontal synchronization signal EHD and the comparison signal V
In determining whether or not the phases of the HDs are synchronized, it is necessary to allow for this jitter, and as described above, for example, a period of two pulses based on the comparison signal (VHD) 6 is set as the comparison period. I have.

As shown in FIG. 3, at T1, the phase of the horizontal synchronizing signal EHD and the phase of the comparison signal VHD match, so that they are locked. Therefore, in that case, the comparison signal (VHD) 6 in the PLL circuit is selected and output as the reference synchronization signal (SYNC) 16 as usual. Next, T2
In, since the phase of the horizontal synchronization signal (EHD) 14 is earlier than that of the comparison signal (VHD) 6, the lock is released. In that case, the reference synchronization signal (SYN
C) Select and output the horizontal synchronizing signal (EHD) 14 as 16. As shown in FIG. 3, T during the lock retraction operation
In the case of 3, T4, the horizontal synchronizing signal (EHD) 14
Select and output. Only at time T5, the lock state is established, and the comparison signal (VHD) 6 is selected and output.

FIG. 4 is an internal block diagram of the lock / unlock determination circuit 9 and the synchronization signal generation circuit 8 in the PLL circuit 35 of FIG. FIG. 5 is a timing chart of the circuit shown in FIG. 4, and shows signal waveforms in three states of a locked state, an unlocked state, and a free-run switching state.

In FIG. 4, since the comparison signal VHD and the external horizontal synchronizing signal EHD are L-active signals in terms of circuit, bars indicating inversion are displayed. 91,
84, 85 and 86 are delay flip-flops. First, in the lock / unlock determination circuit 9, the comparison signal (VH
D) A signal having a pulse width of 2 from 6 is generated at the output of the AND gate 92, and the output (92) is output from the flip-flop 93 at the falling timing of the horizontal synchronizing signal (EHD) 14.
Loading. As a result, flip flop 93
The output Q of the L level is output at the L level when both signals are synchronized and in the unlocked state where both signals are out of synchronization, and the H level is output. Then, the determination result signal of the output Q is supplied as the S signal of the switch circuit 83 via the OR and AND gates 81 and 82. The signal A delayed by two pulses of the comparison signal (VHD) 6 is in the locked state, and the horizontal synchronization signal (EHD) is in the unlocked state.
Fourteen signals B with a two-pulse delay are selected and output as a reference synchronization signal (SYNC) 16.

Reference numeral 88 denotes a free-run switching signal which is provided by an operator or the like operating the display device and forcibly selects and outputs the comparison signal (VHD) 6. The delay flip-flop 86, the AND gate 87, and the OR gate 81 switch the output Q of the load flip-flop 93 by the load signal of the horizontal synchronizing signal (EHD) 14, so that the lock-unlock is performed only at a necessary timing. The output Q of the lock determination circuit 9 is provided to the switch circuit 83 as an S signal.

The operation of the circuit of FIG. 4 in each state will be described with reference to FIG. First, the locked state will be described. 2 based on comparison signal VHD
A signal indicating a pulse comparison period is output to the AND gate 92. Then, when the horizontal synchronizing signal EHD phase-synchronized with the comparison signal VHD is at L level, loading is performed at the rising edge of the next clock, so that the flip-flop 93
Is output at the L level indicating the locked state.
Then, from the horizontal synchronization signal EHD, flip-flop 8
5, 86 and the clock (the output of 87) generated by the AND gate 87, the signal of the output Q (93) is ORed.
The data is supplied to the capture switch circuit 83 via the gate 81. The free-run switching signal 88 is normally at the H level, and the output of the OR gate 81 is passed through as it is to the switch signal 83. As a result, the switch circuit 83
Selects the comparison signal VHD on the A terminal side and outputs it as the reference synchronization signal (SYNC) 16.

Next, the unlocked state will be described. The output of AND gate 92 is equivalent to the above. When the horizontal synchronization signal EHD is at L level and loaded at the next rising edge of the clock, the phase is not synchronized.
The input D is supplied with the H level and the signal is loaded.
The H level is output to the output Q (93). And 87
Through the OR gate 81 at the timing of the output signal of
The level is supplied to the S signal of the switch circuit 83. As a result, the terminal B is selected, and an external horizontal synchronizing signal E
A signal (output of 86) delayed by two pulses from HD is output as a reference synchronization signal (SYNC) 16.

As described above, when the unlock state is determined, the comparison signal (VHD) out of phase with the video signal is determined.
6 is not used as the internal reference synchronization signal (SYNC) 16, but is used as the internal horizontal synchronization signal by using the externally input horizontal synchronization signal (EHD) 14 as it is. Therefore, the timing of the horizontal scanning on the display screen is tentatively phase-synchronized, and disturbance such as the display screen flowing can be prevented. Note that the sampling system clock (CLK) 15 is out of phase at the time of unlocking, but has a slight deviation in frequency to some extent, and does not cause much image disturbance. Therefore, in the unlocked state, it is possible to avoid a situation where a large image flows.

Further, in the free-run switching state, the switching signal 88 is forcibly set to the L level, so that the output of the AND gate 82 is also forcibly set to the L level. (SYNC) 16 selects the comparison signal VHD.

Although the output of the AND gate 92 is used as a signal indicating the comparison period, the comparison period can be appropriately set according to the allowable range of the jitter and the allowable range of the jitter in the forward and backward directions.

[0030]

As described above, according to the present invention, in a digital image processing apparatus, a system clock synchronized in phase with an externally supplied horizontal synchronizing signal and an internal reference synchronizing signal (internal horizontal synchronizing signal). Can output the optimum synchronization signal as the reference synchronization signal in the locked state and the unlocked state. Therefore, even when the channel is switched or the display mode is switched to temporarily unlock the display, it is possible to prevent the display screen from flowing into a defective display state as much as possible.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing an entire digital video processing device.

FIG. 2 is a block diagram showing an internal configuration of a PLL circuit 35 in FIG. 1;

FIG. 3 shows an output synchronization signal SYNC generated by a PLL circuit 35;
FIG. 14 is a timing chart for explaining how the switching of the reference numeral 16 is performed.

FIG. 4 is a detailed block diagram of a lock / unlock determination circuit and a synchronization signal generation circuit in the PLL circuit.

FIG. 5 is a timing chart of the circuit of FIG. 4;

[Explanation of symbols]

 Reference Signs List 2 phase comparison circuit 3 low-pass filter circuit 4 voltage-controlled oscillator 5 divider 6 comparison signal (VHD) 8 reference synchronization signal generator 9 lock / unlock determination circuit 14 external horizontal synchronization signal (EHD) 15 system clock signal (CLK) , CK) 16 Reference synchronization signal (SYNC) 33 Analog-to-digital converter 35 PLL circuit 36 Display

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/66 102 H04N 5/66 102Z

Claims (6)

[Claims] 1. A clock signal having a frequency that is an integral multiple of a supplied horizontal synchronizing signal is output, and a comparison signal obtained by dividing the frequency of the clock signal by a factor of 1 is fed back to the horizontal synchronizing signal. A phase locked loop circuit for a digital video processing device for generating the clock signal, further comprising comparing the horizontal synchronization signal with a comparison signal to determine whether the phase locked loop circuit is locked or unlocked. And a lock / unlock detection circuit for detecting the lock state.When the lock state is detected by the lock / unlock detection circuit, the comparison signal is output internally as a reference synchronization signal, and when the unlock state is detected, And a reference synchronizing signal generating circuit for outputting the horizontal synchronizing signal as the reference synchronizing signal. Phase-locked loop circuit for the management apparatus. 2. The phase-locked loop circuit for a digital video processing device according to claim 1, wherein the lock / unlock detection circuit is configured to control the horizontal synchronization signal during a predetermined comparison period based on the comparison signal. The locked state or the unlocked state is detected by determining whether or not is supplied. 3. A digital video processing device which is supplied with a horizontal synchronizing signal, a vertical synchronizing signal and an analog video signal at a predetermined timing based on the synchronizing signal, generates a digital video signal internally, and displays a video. A clock signal having an integer multiple of the frequency of the horizontal synchronization signal is output, and a comparison signal obtained by dividing the frequency of the clock signal by a factor of 1 is fed back to generate the clock signal phase-synchronized with the horizontal synchronization signal. A phase locked loop circuit to be performed, and when the phase locked loop circuit is in a locked state, an internal horizontal synchronization signal is generated based on the comparison signal, and when the phase locked loop circuit is in an unlocked state, the external horizontal synchronization signal is generated. A generation circuit for generating an internal horizontal synchronization signal based on the analog video signal; Grayed, and digital image processing apparatus having an analog-to-digital converter for generating a digital video signal, and a display unit for performing image display in accordance with said digital video signal and the internal horizontal sync signal. 4. The digital video processing apparatus according to claim 3, further comprising: a lock / unlock circuit for comparing the horizontal synchronization signal with a comparison signal to detect a locked state and an unlocked state of the phase locked loop circuit. A lock detection circuit is provided. 5. The digital video processing device according to claim 4, wherein the lock / unlock detection circuit determines whether or not the horizontal synchronizing signal is supplied during a predetermined comparison period based on the comparison signal. The locked state or the unlocked state is detected by the determination. 6. The digital video processing device according to claim 3, wherein said display section is constituted by a plasma display panel or a liquid crystal display panel.