JP3463464B2 - Image display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix type image display device in which pixels are arranged in a horizontal direction and a vertical direction at regular intervals.

[0002]

2. Description of the Related Art In a conventional image display device, when an image is compressed and expanded in the horizontal direction, for example, JP-A-7-67046.
As disclosed in Japanese Patent Laid-Open No. 4-354279 and Japanese Patent Laid-Open No. 4-354279, a video signal is sampled with a sampling signal having a constant frequency within one horizontal period, and the obtained data is held in a temporary storage device such as a memory. Then, the stored data is subjected to arithmetic processing or the reading speed of the held data is changed from the writing speed to compress and expand the video in the horizontal direction.

[0003]

However, as described above, sampling is performed using a sampling signal having a constant frequency within one horizontal period, the obtained data is temporarily held, and the held data is subjected to arithmetic processing. When compressing / decompressing a horizontal video image, a temporary storage device such as a line memory to hold the data and a circuit configuration to perform arithmetic processing on the held data are required. And / or there is a problem that it leads to an increase in circuit scale.

[0004]

In order to solve the above-mentioned problems, an image display device of the present invention comprises a sampling signal generating means for generating a sampling signal for sampling a video signal, and a video signal by the sampling signal. A video signal sampling means for sampling, and a display section for displaying an image by the signal sampled by the video signal sampling means, the sampling signal generating means generating means for generating a clock of a constant frequency, and inverting the clock. A means for generating a clock and one of two predetermined minimum repeating unit setting values
After reading in the shift register as shift data
A frequency- divided signal of the clock and the two minimum repetitions by repeatedly shifting and outputting the clock with the clock .
The other of the unit setting values is different from the shift register.
After reading it as shift data into the shift register of
To be repeatedly output by shifting with the inverted clock
The exclusive logic of the signal obtained by dividing the inverted clock by
Means for synthesizing by a summing means and generating a sampling signal having a cycle of (n + 1) / 2 times (n is a natural number) of the clock. Further, a plurality of sampling signal generating means are set in the selector.
Switch the setting value of the minimum repeating unit
A signal having a plurality of frequency division ratios is read by the shift register, and the video signal is sampled by a sampling signal having a different cycle depending on the horizontal position of the display unit. It is characterized by.

According to the present invention, there is no need for a temporary storage device such as a line memory or a circuit configuration for processing held data.
The video signal can be compressed and expanded in the horizontal direction and displayed on the image display device.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to an image display device in which pixels are arranged in the horizontal direction and in the vertical direction at regular intervals, and when sampling a video signal, a sampling signal whose frequency changes within one horizontal period is used. It is characterized by performing sampling, and has an effect that an image can be freely expanded / contracted in the horizontal direction and the expansion / contraction rate can be changed within one horizontal period.

According to the present invention, a sampling signal generating means for generating a sampling signal for sampling a video signal, a video signal sampling means for sampling a video signal by the sampling signal, and a signal sampled by the video signal sampling means. And a display unit for displaying an image, and has an effect of performing sampling with a sampling signal whose frequency changes within one horizontal period.

According to the present invention, in the above invention, the sampling signal generating means is provided with a logic circuit, a clock signal system of a constant frequency for operating the logic circuit, and an inverted clock signal system of the clock signal system. A video signal is sampled by a signal obtained by synthesizing signals generated in the system, and by using the two types of clock signals, (n + 1) / 2 times the cycle of the clock signal. (However, n is a natural number)
The video signal can be sampled with a signal having a cycle of.

This means that the period of the sampling signal generated by using only one kind of clock signal is n times as large as that of the clock signal, which means that the degree of freedom is increased, that is, the image is horizontal. This has the effect of increasing the degree of freedom in setting the expansion / contraction ratio when the image is expanded / contracted in the direction.

Within a horizontal period, the sampling frequency of the video signal (in other words, the cycle of the sampling signal) is changed to realize horizontal expansion / contraction of the image, and the expansion / contraction rate is set to 1.
This has the effect of increasing the degree of freedom in setting the sampling frequency, that is, the expansion / contraction ratio of the image, when changing within the horizontal period.

In the invention described above, the sampling signal generating means is provided with a logic circuit, a clock signal system of a constant frequency for operating the logic circuit, and an inverted clock signal system of the clock signal system, and each clock signal system is provided. The signal obtained by synthesizing the signals generated in step 1 is used while switching among multiple types according to the horizontal area (position) of the image, and the horizontal area (position) of the screen is used. Accordingly, the sampling frequency of the video signal is changed according to the above, and the expansion / contraction ratio of the image is changed for each region in the horizontal direction.

According to the present invention, in the above invention, the voltage controlled oscillator circuit (Volt) of the clock signal generating section for operating the logic circuit is operated.
age Controlled Oscillator: Hereinafter referred to as VCO)
And a circuit for continuously changing the voltage applied to the VCO within one horizontal period is provided, and the frequency of a signal for sampling a video signal is added to the logic circuit without additional change. It can be controlled according to the voltage.

As a result, the horizontal expansion / contraction of the image is realized,
In addition, it has an effect that the expansion / contraction ratio can be freely set.

FIG. 1 shows an embodiment of the present invention.
Starting from FIG. It should be noted that the present invention will be described here by taking as an example the case of displaying an NTSC television image on an active matrix type liquid crystal display device.

(Embodiment 1) An embodiment of the present invention will be described.

FIG. 2 shows a block diagram of the image display device of the present invention. In FIG.
It has the function of generating the sampling signal 2 whose frequency changes within the horizontal period.

The video signal sampling section 201 samples the video signal 1 at the rising edge (or falling edge) of the sampling signal 2. The active matrix liquid crystal display device 202 includes a video signal sampling unit 201.
The light transmissivity of each pixel is changed according to the potential of the video signal sampled in (3) to display an image.

When sampling the video signal 1 by the video signal sampling unit 201, either analog sampling or digital sampling may be performed. At that time, in the case of analog sampling, the potential of the sampled video signal is applied to the active matrix type liquid crystal display device 202, and when digital sampling is performed, the value is analogized by the D / A converter. After being converted into the potential of, the voltage is applied to the active matrix type liquid crystal display device 202. The following description will be made on the assumption that analog sampling is performed.

The control unit 203 includes the sampling signal generation unit 2
00, a control signal 203 for controlling the video signal sampling unit 201 and the active matrix type liquid crystal display device 202.

The sampling signal generator 20 shown in FIG.
The sampling signal 2 generated at 0 will be described with reference to FIG. As shown in FIG. 1, the sampling signal 2 is 1
The frequency changes within the horizontal scanning period.

If the video signal 1 is sampled at the rising edge of the sampling signal 2, the sampled potential has a value indicated by a black circle on the video signal 1. In the active matrix type liquid crystal display device, the pixels are arranged at equal intervals in the horizontal direction and the vertical direction, and this state is drawn only for one line in the horizontal direction, which is the pixel 5 of the active matrix type liquid crystal display device. .

The above-mentioned sampled video signal potential is applied to this pixel. At this time, since the values engraved with unequal intervals of time correspond to the pixels arranged at equal intervals, compression / expansion in the horizontal direction is performed. Can be realized.

(Embodiment 2) An embodiment of the present invention will be described.

The sampling signal generator 200 of FIG. 2 described in the first embodiment will be further described with reference to FIGS. 3 and 4.

In FIG. 3, the clock signal 6 having a constant cycle operates the logic circuit, but the signal that can be generated at this time always has a changing point at the rising edge of the clock signal 6 and can therefore be used as a sampling signal. The signal cycle is a signal having a cycle of 1 time (1 time represents the clock signal itself), 2 times, 3 times ...

Similarly, a signal which can be generated from the inverted clock signal 7 having a frequency of a constant cycle has a period which is one time the cycle of the clock signal 6 (or the inverted clock signal 7) (however, one time is the clock signal itself). 2)
It is a signal with a cycle of double or triple, and the phase is shifted by half a cycle. In either case, the period of a signal that can be generated from one type of clock signal is n times the period of the clock signal 6 (n is a natural number).

Therefore, consider a case where the clock signal 6 and the inverted clock signal 7 are combined. As an example, a signal example 30 with a triple cycle created by a logic circuit operating with a constant frequency clock signal 6 and a signal example 31 with a triple cycle created by a logic circuit operating with an inverted clock signal 7 with a constant frequency are shown. The period of the signal 32 obtained by synthesizing using the exclusive OR is ⅔ times the period of the clock signal 6, and thus the degree of freedom in setting the period of the sampling signal can be increased.

In FIG. 4, (a) is a signal created by a logic circuit that operates with a clock signal 6 having a constant cycle, and (a) is a signal created by a logic circuit that operates with an inverted clock signal 7. The signal (a) is obtained by taking the exclusive OR of the signal and the signal (a). Similarly, signals (SI), (SU), (SE) and (SO) having various periods (frequency) are obtained.

By using the signals (SA) to (SO) as the signals for sampling the video signal 1, it is possible to provide an image display device which expands and contracts the video in the horizontal direction and displays it.

(Embodiment 3) An embodiment of the present invention will be described.

Regarding the sampling signal generator 200 of FIG. 2 described in the first embodiment, FIG. 4, FIG. 5 and FIG.
Will be further explained using. The signals (s), (s), (so), (s), shown in FIG. 4 as the sampling signal 2,
(So), (Si), and (Su) are used in this order by joining them in one horizontal period. The combined signal is shown in FIG.

FIG. 5 shows an example of the configuration of the sampling signal generator for generating the signal shown in FIG. Selectors 12 and 1
3 includes signals (s), (s), (s), and (s) shown in FIG.
The signal before (c) is synthesized by the exclusive OR, that is, the signal (e) for the signal (s), the signal (c) for the signal (c), the signal (c), (d) for the signal (c). Set the minimum repeating unit of signal (K) for signal (S) and signal (K) and signal (K) for signal (S), respectively. The timing control unit 14 switches the selectors 12 and 13 according to the horizontal area (position) of the image to change the set value of the shift data set in the shift registers 8 and 9. The timing control unit 14 also controls the timing of reading shift data into the shift registers 8 and 9. This timing corresponds to the length of the shift data and is configured to repeat the operation of reading and shifting the minimum repeating unit.

The EX-OR gate 15 receives the signals sent from the shift register 8 which operates with the clock signal 6 having a constant cycle and the shift register 9 which operates with the inverted clock signal 7 having a constant cycle, and generates the sampling signal 2. .

By sampling the video signal 1 with the sampling signal 2 thus generated,
It is possible to provide an image display device capable of changing the expansion / contraction rate of an image for each horizontal region by changing the sampling frequency according to the horizontal region (position) of the screen.

(Embodiment 4) An embodiment of the present invention will be described with reference to FIGS. 7 and 8.

FIG. 7 is a circuit configuration diagram for controlling a clock frequency for sampling a video signal, and FIG. 8 is a diagram showing waveforms of main parts.

The circuit shown in FIG. 7 includes a voltage control oscillator (VCO) including an inverter 70, a feedback resistor 71, a resonance inductance 72, a resonance capacitance 74, a varicap 80, and a bias power supply 81, resistors 75, 76, 79, and a capacitance. 77, 78
Control voltage feedback circuit composed of a phase comparator 87 and 1 / N
Phase-locked loop (P
LL) as a basic circuit, to which a control voltage modulation circuit including a memory 82, a D / A converter 83, resistors 84 and 85, and a reference voltage 86 is added.

Of these, the former PLL circuit may be of a general type and generates an N × fH clock signal which is phase-synchronized with the horizontal synchronizing signal (F) (frequency fH) applied to the input terminal 90.

It is the above-mentioned VCO that generates the clock signal, but its frequency is the resonance inductance 7
2, and the series capacitance of the resonance capacitance 74 and the varicap 80. In a normal PLL, the output of the phase comparator 87 is almost converted into direct current by the control voltage feedback circuit and applied to the anode of the varicap 80 to change the potential difference between the cathode and the bias power supply 81. It works by moving the frequency and eliminating the phase difference.

In the circuit of the present invention, the output of the control voltage modulation circuit is connected to the anode of the varicap 80. If the voltage waveform (K) of this portion is modulated, the VCO frequency is modulated according to the waveform. Will be done. Assuming that the waveform is changed into a parabolic shape within one horizontal scanning period as shown in FIG. 8, the waveform of the oscillation clock is
The frequency is smoothly changed like a parabola like.

At this time, it is necessary to pay attention to the movement of the output of the phase comparator 87. That is, in order for the PLL to be kept in the locked state, the waveform (g) must be equivalent to that before the parabolic waveform is added in the direct current. For that purpose, even after adding the parabolic waveform, it must be added in such a form that the DC value before adding it and the average value of the waveform (K) are equal (the area of the shaded areas a and b is 1 Equal within the horizontal period). As a result, the phase lock of the PLL is maintained at the division ratio N.

The parabolic waveform can be obtained by, for example, digitally storing the data in the memory 82 and converting the data into analog data by the D / A converter 83. To adjust the amplitude, for example, if a current output type D / A converter is used, the amplitude can be adjusted by the variable output resistance 84 connected to the power supply 91. Further, the DC level of the output can be adjusted by the reference voltage 86 given to the D / A converter 83. The resistor 85 has a meaning of isolation because it does not affect the resonance constant, and a large value is selected.

In this way, a clock signal whose frequency continuously changes in a parabola shape within one horizontal period can be created. Therefore, if this clock signal is used as a clock for sampling a video signal, an image in the horizontal direction of the screen can be displayed. It is possible to display an image in which the expansion and contraction rate changes continuously.

Needless to say, the change in frequency is not limited to the parabolic shape and may be any shape.

[0045]

As described above, according to the present invention, a temporary storage device such as a line memory and a circuit configuration for performing arithmetic processing on retained data are not required, and the number of components and / or the circuit scale is reduced. The advantageous effect that it can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a sampling signal and a brightness level displayed on a pixel according to an embodiment of the present invention.

FIG. 2 is a block diagram according to an embodiment of the present invention.

FIG. 3 is a timing chart of sampling signals according to an embodiment of the present invention.

FIG. 4 is a timing chart of sampling signals according to an embodiment of the present invention.

FIG. 5 is a block diagram according to an embodiment of the present invention.

FIG. 6 is a timing chart of sampling signals according to an embodiment of the present invention.

FIG. 7 is a circuit configuration diagram for controlling a clock frequency according to an embodiment of the present invention.

FIG. 8 is a diagram showing a VCO control voltage waveform and a sampling signal according to an embodiment of the present invention.

[Explanation of symbols]

1 Video signal 2 Sampling signal 3 Arrow indicating the correspondence between sampling point and pixel of active matrix type liquid crystal display device 4 Brightness level displayed on pixel 5 Pixel of active matrix type liquid crystal display device (one horizontal line) 6 Fixed frequency clock signal 7 Fixed frequency inverted clock signal 8, 9 Shift register 10, 11 Flip-flop 12, 13 Selector 14 Timing control unit 15 EX-OR gate 16 Selector control signal 17 Shift data load signal 30 Fixed frequency clock signal Example of signal with triple cycle created by logic circuit operating in 6 31 Example of signal with triple cycle created by logic circuit operating with constant frequency 7 32 Example of signal with 3/2 cycle 70 Inverter 71 Feedback Resistor 72 Resonance inductance 73, 74 Resonance capacitance 80 Varicap 81 Bias power supply 75, 76, 79 Resistor 77, 78 Capacitance 87 Phase comparator 88 1 / N frequency divider 82 Memory 83 D / A converter 84, 85 Resistor 86 Reference voltage 90 Input terminal 200 Sampling signal generator 201 video signal sampling unit 202 active matrix type liquid crystal display device 203 control signal

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-8-65609 (JP, A) JP-A-8-123359 (JP, A) JP-A-3-226085 (JP, A) JP-A-7- 222120 (JP, A) JP-A-5-207326 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04N 5/66 H04N 7/01 H04N 1/387 G09G 5/36

Claims (2)

(57) [Claims] 1. Sampling signal generating means for generating a sampling signal for sampling a video signal,
A video signal sampling means for sampling a video signal by the sampling signal and a display section for displaying an image by the signal sampled by the video signal sampling means are provided, and the sampling signal generating means generates a clock having a constant frequency. Means, means for generating an inverted clock of the clock, and setting of two predetermined minimum repeating units
Read one of the values into the shift register as shift data
Repeatedly output after shifting by the clock after allowing
Signal and the two obtained by frequency-dividing the clock by
Of the set value of the minimum repeat unit of
Read as shift data in a shift register different from the register
Repeat after shifting by the inversion clock after allowing
Signal obtained by dividing the inverted clock by outputting the
And a means for synthesizing by means of an exclusive OR, and a sampling signal having a cycle of (n + 1) / 2 times (n is a natural number) of the clock is generated. 2. The sampling signal generating means is a selector.
Setting of the minimum repeating unit set in multiple units
Switch the value and read it into each of the shift registers.
By further comprising means for switching signals of a plurality of frequency division ratios at arbitrary timings, the video signal is sampled by sampling signals of different cycles depending on the horizontal region (position) of the display section. The image display device according to claim 1.