JP7434770B2 - Duty correction circuit, receiving circuit and duty correction method - Google Patents

Description

The present invention relates to a duty correction circuit, a receiving circuit, and a duty correction method.

When transmitting a clock signal between devices, the duty ratio of the clock signal received by the receiving circuit may be different from that of the source clock signal due to variations in temperature, voltage, electrical characteristics of the circuit transmitting the clock signal, etc., and other factors. It may deviate from the duty ratio. For example, if the duty ratio of a clock signal for receiving a data signal deviates, the reception margin of the data signal in the receiving circuit decreases.

Further, when a receiving circuit receives a data signal in which a clock signal is embedded, the receiving circuit reproduces the clock signal from the data signal and latches the data signal in synchronization with the reproduced clock signal. Also in this case, if there is jitter in the reproduced clock signal, the reception margin of the data signal decreases.

Therefore, a duty correction circuit has been proposed that corrects the clock signal to have a duty ratio of 50% regardless of the duty ratio of the received clock signal (see Patent Document 1).

However, in conventional duty correction circuits, although the duty ratio is set to 50%, depending on the duty ratio of the received clock signal, the phase of the clock signal whose duty ratio has been corrected may deviate from the phase of the original clock signal. There is a problem. In this case, for example, it is not possible to improve the reception margin of a data signal received in synchronization with a clock signal.

The disclosed technology was developed in view of the above-mentioned problems, and aims to generate an output clock that matches the phase of the source of the input clock while correcting the duty ratio of the received input clock to 50%. shall be.

In order to solve the above technical problem, a duty correction circuit according to one embodiment of the present invention includes a phase shift circuit that generates a shift clock whose phase is shifted by 180 degrees with respect to a received input clock, and the input clock and the shift clock. inverts the logic value of the output clock in response to one of the rising or falling edges of the input clock and the shift clock, and in response to the other of the rising or falling edges of the input clock and the shift clock, the other edge a logic setting circuit that holds the logic value of the output clock immediately before it appears, and the logic setting circuit includes a first flip-flop circuit that has a first NAND gate that receives the input clock and a second NAND gate that receives the shift clock. a second flip-flop having a third NAND gate receiving the output signal of the first NAND gate and a fourth NAND gate receiving the output signal of the second NAND gate; and a positive clock mode in which the beginning of the input clock is a rising edge. a fifth NAND gate that outputs a low level when both the input clock and the shift clock are at a high level, and outputs a high level when the input clock has a leading edge as a falling edge in a negative clock mode; a NOR gate that outputs a high level when the input clock and the shift clock are both at a low level and outputs a low level when in the negative clock mode; and a NOR gate that receives an output signal of the fifth NAND gate and an output signal of the NOR gate. a seventh NAND gate receiving an output signal of the third NAND gate and an output signal of the sixth NAND gate; and an eighth NAND gate receiving an inverted signal of the output signal of the fourth NAND gate and the output signal of the sixth NAND gate. and a ninth NAND gate that receives the output signal of the seventh NAND gate and the output signal of the eighth NAND gate and outputs the output clock, and the rising edge or the rising edge that inverts the logic value of the output clock. The one transition direction of the falling edge is the same as the transition direction of the leading edge of the input clock.

It is possible to generate an output clock that matches the phase of the source of the input clock while correcting the duty ratio of the received input clock to 50%.

FIG. 1 is a block diagram showing an example of a system including a duty correction circuit according to a first embodiment of the present invention. 2 is a circuit diagram showing an example of the duty correction circuit of FIG. 1. FIG. FIG. 2 is a timing chart showing an example of an operation in which the duty correction circuit of FIG. 1 corrects the duty ratio of a clock signal to 50%. 3 is a timing diagram showing another example of an operation in which the duty correction circuit of FIG. 1 corrects the duty ratio of a clock signal to 50%. FIG. FIG. 3 is a timing diagram showing still another example of the operation in which the duty correction circuit of FIG. 1 corrects the duty ratio of a clock signal to 50%. FIG. 7 is a circuit diagram showing an example (comparative example) of another duty correction circuit. 7 is a timing diagram showing an example of an operation in which the duty correction circuit of FIG. 6 corrects the duty ratio of a clock signal to 50%. FIG. FIG. 2 is a block diagram showing an example of a system including a duty correction circuit according to a second embodiment of the present invention. 9 is a circuit diagram showing an example of the duty correction circuit of FIG. 8. FIG. 10 is a timing diagram showing an example of an operation in which the duty correction circuit of FIG. 9 corrects the duty ratio of a clock signal to 50%. FIG. 7 is a timing diagram showing another example of the operation in which the duty correction circuit of FIG. 6 corrects the duty ratio of the clock signal to 50%. FIG. FIG. 7 is a block diagram showing an example of a system including a duty correction circuit according to a third embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a duty correction circuit according to a fourth embodiment of the present invention. 14 is a timing diagram showing an example of the operation when the duty correction circuit of FIG. 13 receives a positive clock signal. FIG. 14 is a timing diagram showing an example of the operation when the duty correction circuit of FIG. 13 receives a negative clock signal. FIG. It is a circuit diagram showing an example of a duty correction circuit concerning a 5th embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a receiving circuit including a duty correction circuit according to a sixth embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a receiving circuit including a duty correction circuit according to a seventh embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a duty correction circuit according to an eighth embodiment of the present invention. FIG. 7 is a circuit diagram showing an example of a duty correction circuit according to a ninth embodiment of the present invention. FIG. 2 is a block diagram showing an example of a system in which the duty correction circuit of the embodiment described above is installed. FIG. 3 is a block diagram showing another example of a system in which the duty correction circuit of the embodiment described above is installed. It is a block diagram showing still another example of a system in which the duty correction circuit of the above-mentioned embodiment is installed.

Embodiments will be described below with reference to the drawings. In the following description, the same symbols as the signal names are used for signal lines through which signals are transmitted. The logical value of a signal is indicated by a low level and a high level. In each drawing, the same components are given the same reference numerals, and redundant explanations may be omitted.

(First embodiment)
FIG. 1 is a block diagram showing an example of a system including a duty correction circuit according to a first embodiment of the present invention. The system 100 shown in FIG. 1 includes a transmitter 200 and a receiver 300 that are connected to each other via a signal line.

The transmitting section 200 has a data transmitting processing circuit 210, and the receiving section 300 has a duty correction circuit 310 and a data receiving processing circuit 320. The data transmission processing circuit 210 transmits a clock signal CLK and a data signal DATA synchronized with the clock signal CLK to the receiving section 300. The data reception processing circuit 320 receives the data signal DATA in synchronization with the clock signal CLK (output clock OP in FIG. 2) received via the duty correction circuit 310, and performs data processing using the received data signal DATA. Implement.

For example, the transmitter 200 and the receiver 300 may be placed in the same housing or on the same board, or may be placed in different housings. In this case, the clock signal line CLK and data signal line DATA connecting the data transmission processing circuit 210 and the data reception processing circuit 320 are cables or wiring patterns.

When the transmitter 200 is composed of a board and components mounted on the board, the clock signal line CLK and data signal line DATA in the transmitter 200 are wiring patterns on the board. When the transmitting section 200 is composed of a semiconductor device such as an LSI (Large-Scale Integration), the clock signal line CLK and the data signal line DATA within the transmitting section 200 are internal wiring of the semiconductor device.

Similarly, when the receiving section 300 is composed of a substrate and components mounted on the substrate, the clock signal line CLK and the data signal line DATA in the receiving section 300 are wiring patterns on the substrate. When the receiving section 300 is composed of a semiconductor device such as an LSI, the clock signal line CLK and the data signal line DATA within the receiving section 300 are internal wiring of the semiconductor device.

In this embodiment, system 100 employs a positive clock scheme in which transmission of data signal DATA begins in response to a rising edge of clock signal CLK. Furthermore, the system 100 employs so-called DDR (Double Data Rate), which transmits the data signal DATA in synchronization with each of the rising edge and falling edge of the clock signal CLK.

For example, the data transmission processing circuit 210 generates and transmits the clock signal CLK and the data signal DATA such that the rising edge and falling edge of the clock signal CLK are at the center of the valid period of the data signal DATA. That is, data transmission processing circuit 210 sets equal setup time and hold time for the transition edge of clock signal CLK.

Furthermore, the data transmission processing circuit 210 sets the duty ratio of the clock signal CLK to 50% in order to transmit the data signal DATA in synchronization with the rising edge and the falling edge of the clock signal CLK, respectively. The data reception processing circuit 320 is designed to receive the data signal DATA in synchronization with the rising edge and falling edge of the clock signal CLK having a duty ratio of 50%.

Although FIG. 1 shows an example in which serial data signals DATA are transmitted via one data signal line DATA, it is also possible to transmit multiple data signals DATA in parallel via multiple data signal lines DATA. good. Further, the data signal DATA transmitted from the transmitting section 200 to the receiving section 300 may be a single-ended signal or a differential signal, but in this embodiment, an example of a single-ended signal is shown. Examples of differential signals are explained in FIGS. 18 and 20.

For example, the transmission characteristics of the clock signal CLK are determined by the temperature of the clock signal CLK transmission circuit, fluctuations in the power supply voltage, variations in the electrical characteristics of the circuit, noise received by the clock signal line CLK, and the effects of the device to which the clock signal CLK is distributed. Changes due to various factors associated with additions, changes, etc. As a result, the duty ratio of the clock signal CLK received by the receiving section 300 may be distorted, and the duty ratio may become a value smaller than 50% or a value larger than 50%.

As the duty ratio deviates from 50%, the reception margin of the data signal line DATA becomes smaller. For example, if the phase of the falling edge of the clock signal CLK becomes earlier due to a decrease in the duty ratio, and the setup time of the data signal DATA with respect to the falling edge of the clock signal CLK decreases, there is a possibility that the data signal DATA cannot be received. Furthermore, if the phase of the falling edge of the clock signal CLK is delayed due to an increase in the duty ratio, and the hold time of the data signal DATA with respect to the falling edge of the clock signal CLK is reduced, there is a possibility that the data signal DATA cannot be received. . Furthermore, if the clock signal CLK with a corrupted duty ratio is supplied over multiple cycles, there is a possibility that reception errors (NG) will occur continuously.

Therefore, in this embodiment, a duty correction circuit 310 is arranged before the data reception processing circuit 320, and the clock signal CLK with a corrupted duty ratio is returned to the original clock signal CLK with a duty ratio of 50%. Supplied to circuit 320.

Thereby, the setup margin of the data signal DATA with respect to the transition edge of the clock signal CLK can be made equal to the setup margin of the data signal line DATA output from the data transmission processing circuit 210. Further, the hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK can be made equal to the hold margin of the data signal line DATA output from the data transmission processing circuit 210. In other words, the timing margins of the DDR data signal DATA, which are synchronized with the rising edge and the falling edge of the clock signal CLK, can be made equal to each other. As a result, even if the duty ratio of the clock signal CLK collapses, the data reception processing circuit 320 reliably receives the data signal DATA in synchronization with both edges of the clock signal CLK whose duty ratio has been corrected by the duty correction circuit 310. and can be processed.

FIG. 2 is a circuit diagram showing an example of the duty correction circuit 310 of FIG. 1. The duty correction circuit 310 includes a phase shift circuit 318 and a plurality of two-input NAND gates NAND1, NAND2, NAND3, NAND4, NAND5, NAND6, NAND7, NAND8, and NAND9. Hereinafter, the NAND gates NAND (NAND1-NAND9) will be referred to as NAND1, etc. only by the reference numeral. Furthermore, hereinafter, the upper input of each NAND1 to NAND9 will be referred to as one input, and the lower input of each NAND1 to NAND9 will be referred to as the other input.

The phase shift circuit 318 shifts the phase of the received clock signal CLK by 180° and outputs it as a shifted clock signal. In the following, the clock signal CLK received by the duty correction circuit 310 is also referred to as an input clock IP, and the shift clock signal output by the phase shift circuit 318 is also referred to as an input clock IN.

Input clock IP is supplied to one input of NAND1 and one input of NAND5. The input clock IN is supplied to the other input of NAND2 and the other input of NAND5. NAND1 and NAND2 function as flip-flop FF1, and NAND3 and NAND4 function as flip-flop FF2. Flip-flops FF1 and FF2 are connected in series.

The output of NAND3 is connected to one input of NAND7 and one input of NAND4, and the output of NAND4 is connected to the other input of NAND8 and the other input of NAND3. The output of NAND5 is connected to one and the other input of NAND6 and the other input of NAND7. The output of NAND6, which operates as an inverter, is connected to one input of NAND8. The output of NAND7 is connected to one input of NAND9, and the output of NAND8 is connected to the other input of NAND9. Then, an output clock OP whose duty ratio has been corrected to 50% is output from the output of the NAND9. The output clock OP is supplied as a clock signal CLK to the data reception processing circuit 320 in FIG.

FIG. 3 is a timing chart showing an example of an operation in which the duty correction circuit 310 of FIG. 1 corrects the duty ratio of the clock signal CLK to 50%. That is, FIG. 3 shows an example of a duty correction method by the duty correction circuit 310. FIG. 3 shows an example where the duty ratio (Duty) of the clock signal CLK received from the data transmission processing circuit 210 is smaller than 50%. Hereinafter, it is assumed that the duty ratio of the positive clock method is the ratio of the high level period of the clock signal CLK to one period of the clock signal CLK.

Note that in the actual system 100, there is a signal delay in the transmission path between the data transmission processing circuit 210 and the duty correction circuit 310. Therefore, the phase of the input clock IP is shifted from the phase of the clock signal CLK transmitted by the data transmission processing circuit 210. However, in the subsequent timing diagrams including FIG. 3, waveforms are shown assuming that there is no signal delay in the transmission path to make the explanation easier to understand.

In the initial state, input clocks IP and IN and output clock OP are at low level (FIG. 3(a)). Note that the initial state indicates a state before the leading edge of the clock signal CLK appears at the start of transmission of the data signal DATA. Furthermore, although FIG. 3 shows the waveforms during transmission of the data signal DATA, both input clocks IP and IN are at a low level in the initial state immediately before starting transmission of the data signal DATA.

In FIG. 3, it is assumed that the phase of the rising edge of the clock signal CLK transmitted by the data transmission processing circuit 210 is equal to the phase of the rising edge of the input clock IP. The phase of the input clock IN is shifted by 180° from the phase of the input clock IP. The rising edge and falling edge of clock signal CLK are located at the center of the valid period of data signal DATA, respectively. Therefore, the rising edges of the input clocks IP, IN are located at the center of the valid period of the data signal DATA, and the setup time and hold time of the data signal DATA with respect to the rising edges of the input clocks IP, IN are equal to each other.

In the initial state, the outputs of NAND1 and NAND2 are at high level, the output of NAND3 is at low level, and the output of NAND4 is at high level. The output of NAND5 is high level, and the output of NAND6 is low level. The outputs of NAND7 and NAND8 are at high level, and the output of NAND9 (output clock OP) is at low level.

The phase shift circuit 318 of the duty correction circuit 310 shifts the phase of the input clock IP, which is the clock signal CLK with a duty ratio smaller than 50%, by 180° to generate the input clock IN (FIG. 3(b)).

In synchronization with the rising edge of the input clock IP, the output of NAND1 is inverted from high level to low level. As the output of NAND1 changes to low level, the output of NAND3 is inverted from low level to high level, and the output of NAND4 is inverted from high level to low level.

NAND7 inverts its output from high level to low level in response to the high level from NAND3. NAND9 inverts its output from low level to high level in response to the low level from NAND7, and outputs high level output clock OP (FIG. 3(c)). Thereby, the duty correction circuit 310 can generate an output clock OP having the same rising edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 320.

The data reception processing circuit 320 receives the data signal DATA transmitted from the data transmission processing circuit 210 in synchronization with the rising edge of the output clock OP (FIG. 3(d)). At this time, the phase of the rising edge of the output clock OP is equal to the phase of the rising edge of the original clock signal CLK transmitted by the data transmission processing circuit 210.

In other words, the timing relationship between the output clock OP received by the data reception processing circuit 320 and the data signal DATA is the same as the timing relationship between the clock signal CLK and the data signal DATA transmitted by the data transmission processing circuit 210. Therefore, the data reception processing circuit 320 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the rising edge of the clock signal CLK.

Since the duty ratio is smaller than 50%, the phase of the falling edge of the input clock IP is earlier than the phase of the falling edge of the clock signal CLK output by the data transmission processing circuit 210. Therefore, in response to the falling edge of the clock signal CLK, the input clock IP changes from high level to low level before the input clock IN changes to high level (FIG. 3(e)).

As a result, the output of NAND1 is inverted from low level to high level. However, since NAND3 receives a low level from NAND4, it maintains a high level output. Therefore, the states of NAND7, NAND8, and NAND9 do not change, and the output clock OP is held at a high level (FIG. 3(f)). That is, the duty correction circuit 310 performs a duty correction operation in response to the falling edge of the input clock IP to maintain the high level of the output clock OP immediately before the falling edge of the input clock IP appears (see FIG. 3). g)).

After this, the input clock IN changes from low level to high level (FIG. 3(h)). Since the input clock IN is a signal obtained by shifting the phase of the input clock IP by 180 degrees, the phase of the rising edge of the input clock IN is equal to the phase of the falling edge of the clock signal CLK output by the data transmission processing circuit 210.

In synchronization with the rising edge of the input clock IN, the output of NAND2 is inverted from high level to low level. As the output of NAND2 changes to low level, the output of NAND3 is inverted from high level to low level, and the output of NAND4 is inverted from low level to high level.

NAND7 inverts its output from low level to high level in response to the low level from NAND3. NAND9 inverts its output from high level to low level in response to the high level from NAND7, and outputs the low level output clock OP (FIG. 3(i)). Thereby, the duty correction circuit 310 can generate an output clock OP having the same falling edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 320.

The data reception processing circuit 320 receives the data signal DATA transmitted from the data transmission processing circuit 210 in synchronization with the falling edge of the output clock OP (FIG. 3(j)). At this time, the phase of the falling edge of the output clock OP is equal to the phase of the falling edge of the original clock signal CLK transmitted by the data transmission processing circuit 210.

In other words, the timing relationship between the output clock OP received by the data reception processing circuit 320 and the data signal DATA is the same as the timing relationship between the clock signal CLK and the data signal DATA transmitted by the data transmission processing circuit 210. Therefore, the data reception processing circuit 320 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the falling edge of the clock signal CLK.

Next, in response to the falling edge of the clock signal CLK, the input clock IP whose phase has been shifted by 180° changes from high level to low level (FIG. 3(k)). The phase of the falling edge of the input clock IN is earlier than the phase of the falling edge of the clock signal CLK output from the data transmission processing circuit 210.

As a result, the output of NAND2 is inverted from low level to high level. However, since NAND4 receives a low level from NAND3, it maintains a high level output. Therefore, the states of NAND7, NAND8, and NAND9 do not change, and the output clock OP is held at low level (FIG. 3(l)). That is, in response to the falling edge of the input clock IN, the duty correction circuit 310 performs a duty correction operation of maintaining the low level of the output clock OP immediately before the falling edge of the input clock IN appears (see (m) in FIG. 3). )).

After this, the above-described operation is repeated, and the duty correction circuit 310 generates an output clock OP with a duty ratio of 50% based on the input clock IP with a duty ratio smaller than 50%, and outputs it to the data reception processing circuit 320. do.

As described above, NAND1 to NAND9 of the duty correction circuit 310 have the function of changing the output clock OP from a low level to a high level in synchronization with the rising edge of the input clock IP. Further, NAND1 to NAND9 have a function of changing the output clock OP from high level to low level in synchronization with the rising edge of the input clock IN. Furthermore, NAND1 to NAND9 have a function of maintaining the logical value of the output clock OP at the logical value immediately before the falling edge appears in response to a falling edge of the input clock IP or IN. NAND1 to NAND9 are examples of logic setting circuits that set the logic of the output clock OP.

FIG. 4 is a timing diagram showing another example of the operation in which the duty correction circuit 310 of FIG. 1 corrects the duty ratio of the clock signal CLK to 50%. That is, FIG. 4 shows an example of a duty correction method by the duty correction circuit 310. Detailed description of operations similar to those in FIG. 3 will be omitted. FIG. 4 shows an example where the duty ratio (Duty) of the clock signal CLK received from the data transmission processing circuit 210 is greater than 50%. It is assumed that the phase of the rising edge of the input clock IP is equal to the phase of the rising edge of the clock signal CLK output by the data transmission processing circuit 210.

In the initial state, the input clock IP is at low level and the input clock IN is at high level. At this time, the output of NAND1 is at high level, and the output of NAND2 is at low level. The output of NAND3 is low level, and the output of NAND4 is high level. The output of NAND5 is high level, and the output of NAND6 is low level. The outputs of NAND7 and NAND8 are high level, and the output of NAND9 is low level.

In FIG. 4 as well, it is assumed that the relative positional relationship between the rising edge of the clock signal CLK transmitted by the data transmission processing circuit 210 and the rising edges of the input clocks IP and IN is the same. That is, the rising edges of the input clocks IP, IN are located at the center of the valid period of the data signal DATA, and the setup time and hold time of the data signal DATA with respect to the rising edges of the input clocks IP, IN are equal to each other.

In synchronization with the rising edge of the input clock IP, the output of NAND5 is inverted from high level to low level, and the output of NAND6 is inverted from low level to high level. As the output of NAND6 changes to low level, the output of NAND8 is inverted from high level to low level. NAND9 receives the low level from NAND8 and changes the output clock OP from low level to high level (FIG. 4(a)). Thereby, the duty correction circuit 310 can generate an output clock OP having the same rising edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 320.

The data reception processing circuit 320 receives the data signal DATA transmitted from the data transmission processing circuit 210 in synchronization with the rising edge of the output clock OP (FIG. 4(b)). Therefore, the data reception processing circuit 320 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK.

Next, in response to the falling edge of the clock signal CLK, the input clock IN whose phase has been shifted by 180° changes from high level to low level (FIG. 4(c)). As a result, the output of NAND1 is inverted from high level to low level, and the output of NAND2 is inverted from low level to high level. The output of NAND3 is inverted from low level to high level, and the output of NAND4 is inverted from high level to low level.

Further, the output of NAND5 is inverted from low level to high level, and the output of NAND6 is inverted from high level to low level. The output of NAND7 is inverted from high level to low level by the high level from NAND3 and NAND5, and the output of NAND8 is inverted from low level to high level by the low level from NAND4 and NAND6.

Therefore, before and after the input clock IN changes to low level, NAND9 receives the low level from either NAND7 or NAND8, so the state of NAND9 does not change and the output clock OP is held at high level (see FIG. 4). d)). That is, in response to the falling edge of the input clock IN, the duty correction circuit 310 performs a duty correction operation that maintains the high level of the output clock OP immediately before the falling edge of the input clock IN appears (see FIG. 4(e)). )).

After this, the input clock IN changes from low level to high level (FIG. 4(f)). As described with reference to FIG. 3, the phase of the rising edge of the input clock IN is equal to the phase of the falling edge of the clock signal CLK output by the data transmission processing circuit 210.

In synchronization with the rising edge of the input clock IN, the output of NAND5 is inverted from high level to low level, and the output of NAND6 is changed from low level to high level. As the output of NAND5 changes to low level, the output of NAND7 is inverted from low level to high level. NAND9 receives high level from NAND7 and NAND8, inverts the output from high level to low level, and outputs low level output clock OP (FIG. 4(g)).

Thereby, the duty correction circuit 310 can generate an output clock OP having the same falling edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 320. The data reception processing circuit 320 receives the data signal DATA transmitted from the data transmission processing circuit 210 in synchronization with the falling edge of the output clock OP (FIG. 4(h)).

At this time, the phase of the falling edge of the output clock OP is equal to the phase of the falling edge of the original clock signal CLK transmitted by the data transmission processing circuit 210. Therefore, the data reception processing circuit 320 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK.

Next, the input clock IP changes from high level to low level (FIG. 4(i)). Since the duty ratio of the input clock IP is greater than 50%, the phase of the falling edge of the input clock IP is slower than the phase of the falling edge of the clock signal CLK output by the data transmission processing circuit 210. As the input clock IP changes to low level, the output of NAND1 is inverted from low level to high level, and the output of NAND2 is inverted from high level to low level. The output of NAND3 is inverted from high level to low level, and the output of NAND4 is inverted from low level to high level.

Further, the output of NAND5 is inverted from low level to high level, and the output of NAND6 is inverted from high level to low level. However, the output of NAND7 is maintained at a high level due to the high level from NAND3, and the output of NAND8 is maintained at a high level due to the low level from NAND6.

Therefore, before and after the input clock IP changes to low level, NAND9 receives high level from NAND7 and NAND8, so the state of NAND9 does not change and the output clock OP is held at low level (Fig. 4 (j) ). That is, in response to the falling edge of the input clock IP, the duty correction circuit 310 performs a duty correction operation that maintains the low level of the output clock OP immediately before the falling edge of the input clock IP appears (see FIG. 4(k). )).

After this, the above-described operation is repeated, and the duty correction circuit 310 generates an output clock OP with a duty ratio of 50% based on the input clock IP having a large duty ratio with respect to the clock signal CLK, and the data reception processing circuit 320. In this way, even if the duty ratio of the received clock signal CLK is greater than 50%, the duty correction circuit 310 adjusts the same phase as the clock signal CLK output from the data transmission processing circuit 210, as in FIG. Generates an output clock OP having the following values.

FIG. 5 is a timing diagram showing still another example of the operation when the duty correction circuit 310 of FIG. 1 receives a positive clock signal. Detailed description of operations similar to those in FIGS. 3 and 4 will be omitted. FIG. 5 shows an example in which cases where the duty ratio of the clock signal CLK received from the data transmission processing circuit 210 is larger than 50% and cases where the duty ratio is smaller than 50% coexist. It is assumed that the phase of the rising edge of the input clock IP is equal to the phase of the rising edge of the clock signal CLK output by the data transmission processing circuit 210.

The operation of the duty correction circuit 310 shown in FIG. 5 is a combination of the operations shown in FIGS. 3 and 4. That is, when the duty ratio of the received clock signal CLK (input clock IP) is smaller than 50%, the duty correction circuit 310 operates in the same manner as in FIG. 3. When the duty ratio of the received clock signal CLK (input clock IP) is greater than 50%, the duty correction circuit 310 operates in the same manner as in FIG. 4 .

As shown in FIGS. 3 to 5, the duty correction circuit 310 changes the transition direction of the transition edges of the input clocks IP and IN, which invert the logical value of the output clock OP, to the clock at the start of transmission of the data signal DATA. The transition direction is the same as that of the leading edge of signal CLK. Further, the duty correction circuit 310 sets the input clock IP (that is, the clock signal CLK) and the output clock OP to the same logical value in an initial state before the leading edge appears. Thereby, the duty correction circuit 310 can generate the output clock OP having the same phase as the transition edge of the clock signal CLK output by the data transmission processing circuit 210, and as a result, the duty ratio of the output clock OP can be set to 50%. Can be corrected.

FIG. 6 is a circuit diagram showing an example (comparative example) of another duty correction circuit. The same elements as in FIG. 2 are given the same reference numerals, and detailed explanations are omitted. For example, the duty correction circuit 319 shown in FIG. 6 is placed in the receiving section 300 instead of the duty correction circuit 310 in the system 100 of FIG.

The duty correction circuit 319 shown in FIG. 6 includes a phase shift circuit 318 and flip-flops FF1 and FF2. Similarly to the duty correction circuit 310 shown in FIG. 3, the duty correction circuit 319 receives the input clock IP at one input of NAND1, and receives the input clock IN at the other input of NAND2. Further, the duty correction circuit 319 outputs an output clock OP from the output of NAND3.

FIG. 7 is a timing diagram showing an example of an operation in which the duty correction circuit 319 of FIG. 6 corrects the duty ratio of the clock signal CLK to 50%. The system 100 equipped with the duty correction circuit 319 employs a positive clock method in which transmission of the data signal DATA is started from the rising edge of the clock signal CLK. Detailed description of operations similar to those in FIGS. 3 to 5 will be omitted. FIG. 7 shows an example where the duty ratio (Duty) of the clock signal CLK received from the data transmission processing circuit 210 is greater than 50%.

In the duty correction circuit 319, when the input clock IP changes from low level to high level, NAND1 maintains the high level output, so the output clock OP is held at low level (FIGS. 7(a) and (b)). . That is, when the input clock IP changes from low level to high level, the duty correction circuit 319 performs a duty correction operation to maintain the low level of the output clock OP (FIG. 7(c)).

Next, when the input clock IN changes from high level to low level, the output of NAND1 changes to low level and the output of NAND3 changes to high level, so the output clock OP changes from low level to high level (Figure 7 (d), (e)). Therefore, the phase of the rising edge of the output clock OP lags behind the phase of the rising edge of the input clock IP (clock signal CLK).

Next, when the input clock IN changes from low level to high level, NAND2 maintains the high level output, so the output clock OP is held at high level (FIGS. 7(f) and (g)). That is, when the input clock IN changes from a low level to a high level, the duty correction circuit 319 performs a duty correction operation to maintain the high level of the output clock OP (FIG. 7(h)).

Next, when the input clock IP changes from high level to low level, the output of NAND1 changes to high level and the output of NAND3 changes to low level, so the output clock OP changes from high level to low level (Figure 7 (i), (j)). Therefore, the phase of the falling edge of the output clock OP lags behind the phase of the falling edge of the input clock IP (clock signal CLK).

As described above, the duty correction circuit 319 shown in FIG. 6 cannot generate the output clock OP having the same phase as the clock signal CLK output from the data transmission processing circuit 210. Therefore, the setup margin and hold margin of the data signal DATA output from the data transmission processing circuit 210 with respect to the clock signal CLK are reduced. In the worst case, the data reception processing circuit 320 cannot receive the data signal DATA.

As described above, in this embodiment, the duty correction circuit 310 generates the output clock OP having the same phase as the clock signal CLK output by the data transmission processing circuit 210 even when receiving the clock signal CLK whose duty ratio is not 50%. can do. That is, the duty correction circuit 310 can generate the output clock OP matching the phase of the received clock signal CLK while correcting the duty ratio of the received clock signal CLK to 50%. As a result, even when receiving the clock signal CLK with a duty ratio other than 50%, the receiving section 300 transmits the data signal DATA in synchronization with the output clock OP having the same phase as the clock signal CLK output from the data transmission processing circuit 210. can be received.

In other words, the data transmission processing circuit 210 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK. As a result, the system 100 can operate stably regardless of the duty ratio of the clock signal CLK, and the reliability of the system 100 can be improved.

(Second embodiment)
FIG. 8 is a block diagram showing an example of a system including a duty correction circuit according to the second embodiment of the present invention. The same elements as in FIG. 1 are given the same reference numerals, and detailed explanations are omitted. The system 101 shown in FIG. 8 includes a transmitter 201 and a receiver 301 that are connected to each other via a signal line.

The transmitting section 201 has a data transmitting processing circuit 211, and the receiving section 301 has a duty correction circuit 311 and a data receiving processing circuit 321. In this embodiment, the system 101 employs a negative clock method that starts transmitting the data signal DATA from the falling edge of the clock signal CLK.

The transmitter 201 is similar to the transmitter 200 shown in FIG. 1, except that the data transmission processing circuit 211 starts transmitting the data signal DATA from the falling edge of the clock signal CLK. Receiving section 301 is similar to receiving section 300 shown in FIG. 1, except that the polarity of clock signal CLK received by duty correction circuit 311 and data reception processing circuit 321 is opposite.

FIG. 9 is a circuit diagram showing an example of the duty correction circuit 311 of FIG. 8. The same elements as in FIG. 2 are given the same reference numerals, and detailed explanations are omitted.

The duty correction circuit 311 has a NOR gate NOR1 instead of the NAND5 of the duty correction circuit 310 in FIG. Hereinafter, the NOR gate NOR will be referred to as NOR1, etc. only by the code. Further, one and the other inputs of NAND6 are connected to the output of NOR1, the other input of NAND7 is connected to the output of NAND6, and one input of NAND8 is connected to the output of NOR1. The other configuration of the duty correction circuit 311 is the same as that of the duty correction circuit 310 in FIG. NAND1 to NAND4, NOR1, and NAND6 to NAND9 are examples of logic setting circuits that set the logic of the output clock OP.

FIG. 10 is a timing diagram showing an example of an operation in which the duty correction circuit 311 of FIG. 9 corrects the duty ratio of the clock signal CLK to 50%. That is, FIG. 10 shows an example of a duty correction method by the duty correction circuit 311. Detailed description of operations similar to those in FIGS. 3 to 5 will be omitted.

FIG. 10 shows an example in which cases where the duty ratio (Duty) of the clock signal CLK received from the data transmission processing circuit 211 is larger than 50% and cases where it is smaller are mixed. It is assumed that the phase of the falling edge of the input clock IP is equal to the phase of the falling edge of the clock signal CLK output by the data transmission processing circuit 211. In the following description, it is assumed that the duty ratio of the negative clock method is the ratio of the low level period of the clock signal CLK to one cycle of the clock signal CLK.

In the initial state of FIG. 10, the input clock IP is at high level and the input clock IN is at low level. At this time, the output of NAND1 is at low level, and the output of NAND2 is at high level. The output of NAND3 is high level, and the output of NAND4 is low level. The output of NOR1 is low level, and the output of NAND6 is high level. The output of NAND7 is low level, the output of NAND8 is high level, and the output clock OP, which is the output of NAND9, is high level.

In FIG. 10, it is assumed that the relative positional relationship between the rising edge of the clock signal CLK transmitted by the data transmission processing circuit 211 and the falling edges of the input clocks IP and IN is equal. That is, the falling edges of the input clocks IP, IN are located at the center of the valid period of the data signal DATA, and the setup time and hold time of the data signal DATA with respect to the falling edges of the input clocks IP, IN are equal to each other.

In synchronization with the falling edge of the input clock IP, the output of NAND1 is inverted from low level to high level, and the output of NOR1 is inverted from low level to high level (FIG. 10(a)). Due to the high level output from NOR1, the output from NAND6 changes to low level, and the output from NAND7 changes to high level. As a result, the NAND 9 inverts its output from high level to low level and outputs the low level output clock OP (FIG. 10(b)). Thereby, the duty correction circuit 310 can generate an output clock OP having the same falling edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 321.

The data reception processing circuit 321 receives the data signal DATA transmitted from the data transmission processing circuit 211 in synchronization with the falling edge of the output clock OP (FIG. 10(c)). At this time, the phase of the falling edge of the output clock OP is equal to the phase of the falling edge of the original clock signal CLK transmitted by the data transmission processing circuit 211. Therefore, the data transmission processing circuit 211 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK.

Next, in response to the falling edge of the clock signal CLK, the input clock IP whose phase has been shifted by 180° changes from low level to high level (FIG. 10(d)). As a result, the output of NAND2 is inverted from high level to low level, and the output of NAND4 is inverted from low level to high level. Further, the output of NOR1 is inverted from high level to low level, and the output of NAND6 is inverted from low level to high level.

The output of NAND7 maintains a high level due to the high level from NAND3, and the output of NAND8 maintains a high level due to the low level from NOR1. Therefore, before and after the input clock IN changes to high level, NAND9 receives high level from NAND7 and NAND8, so the state of NAND9 does not change and the output clock OP is held at low level (Fig. 10(e) )). That is, the duty correction circuit 311 performs a duty correction operation to maintain the low level of the output clock OP immediately before the rising edge of the input clock IN appears (FIG. 10(f)).

After this, the input clock IN changes from high level to low level (FIG. 10(g)). The phase of the falling edge of the input clock IN is equal to the phase of the rising edge of the clock signal CLK output by the data transmission processing circuit 211.

In synchronization with the falling edge of the input clock IN, the output of NAND2 of the flip-flop FF1 is inverted from low level to high level. Further, the output of NOR1 is inverted from low level to high level, and the output of NAND6 is inverted from high level to low level. As the output of NOR1 changes to high level, the output of NAND8 is inverted from high level to low level. NAND9 receives the low level from NAND8, inverts the output from low level to high level, and outputs high level output clock OP (FIG. 10(h)).

Thereby, the duty correction circuit 310 can generate an output clock OP having the same rising edge timing as the received clock signal CLK, and can supply the generated output clock OP to the data reception processing circuit 321. The data reception processing circuit 321 receives the data signal DATA transmitted from the data transmission processing circuit 211 in synchronization with the rising edge of the output clock OP (FIG. 10(i)).

At this time, the phase of the rising edge of the output clock OP is equal to the phase of the rising edge of the original clock signal CLK transmitted by the data transmission processing circuit 211. Therefore, the data transmission processing circuit 211 can reliably receive and process the data signal DATA without reducing the setup margin and hold margin of the data signal DATA with respect to the transition edge of the clock signal CLK.

Next, the input clock IP changes from low level to high level (FIG. 10(j)). At this time, since the duty ratio of the input clock IP is greater than 50%, the phase of the rising edge of the input clock IP is later than the phase of the rising edge of the clock signal CLK output by the data transmission processing circuit 211.

As the input clock IP changes to high level, the output of NAND1 is inverted from high level to low level. The output of NAND3 is inverted from low level to high level, and the output of NAND4 is inverted from high level to low level. Further, the output of NOR1 is inverted from high level to low level, and the output of NAND6 is inverted from low level to high level. The output of NAND8 is inverted to high level by the low level from NOR1 and NAND4. However, since the output of NAND7 is inverted to low level by the high level from NAND3 and NAND6, the output of NAND9 is maintained at high level.

Therefore, before and after the input clock IP changes to high level, NAND9 maintains the output at high level, and the output clock OP is held at high level (FIG. 10(k)). That is, the duty correction circuit 310 performs a duty correction operation to maintain the high level of the output clock OP immediately before the rising edge of the input clock IP appears (FIG. 10(l)).

Next, when the input clock IP changes from a high level to a low level while the input clock IN is at a low level (FIG. 10(m)), the duty correction circuit 311 changes the output clock OP from a high level to a low level as described above. It is inverted to low level (FIG. 10(n)). Further, when the input clock IN changes from low level to high level while the input clock IP is low level (FIG. 10(o)), the duty correction circuit 311 maintains the low level of the output clock OP as described above. A duty correction operation is performed (FIG. 10(p)).

Next, as the duty ratio of the input clock IP becomes smaller than 50%, the input clock IP changes from a low level to a high level while the input clock IN is at a high level (FIG. 10(q)). At this time, NAND1 maintains a high level output due to the low level from NAND2, and NOR1 maintains a low level output due to the high level of the input clock IN. Therefore, the states of NAND2 to NAND9 do not change, and the output clock OP is maintained at a low level (FIG. 10(r)). That is, the duty correction circuit 310 performs a duty correction operation to maintain the high level of the output clock OP immediately before the rising edge of the input clock IP appears (FIG. 10(s)).

Next, while the input clock IP is at the high level, the input clock IN changes from the high level to the low level (FIG. 10(t)). As the input clock IN changes to low level, the output of NAND2 is inverted from low level to high level, and the output of NAND1 is inverted from high level to low level. The output of NAND3 is inverted from low level to high level, and the output of NAND4 is inverted from high level to low level.

As a result, the output of NAND7 is inverted from high level to low level, the output of NAND9 is inverted from low level to high level, and an output clock OP having the same rising edge timing as the received clock signal CLK is generated (see FIG. 10). u)). Therefore, the data reception processing circuit 321 can receive the data signal DATA transmitted from the data transmission processing circuit 211 in synchronization with the rising edge of the output clock OP having the same phase as the original clock signal CLK (Fig. 10 (v)).

Next, as the duty ratio of the input clock IN becomes smaller than 50%, the input clock IN changes from a high level to a low level while the input clock IP is at a high level (FIG. 10(w)). At this time, NAND2 maintains a high level output due to the low level from NAND1, and NOR1 maintains a low level output due to the high level of the input clock IP. Therefore, the states of NAND2 to NAND9 do not change, and the output clock OP is maintained at a high level (FIG. 10(x)). That is, the duty correction circuit 310 performs a duty correction operation to maintain the high level of the output clock OP immediately before the rising edge of the input clock IN appears (FIG. 10(y)).

Next, while the input clock IN is at a high level, the input clock IP changes from a high level to a low level (FIG. 10(z)). As a result, the output of NAND1 is inverted from low level to high level, and the output of NAND2 is inverted from high level to low level. The output of NAND3 is inverted from high level to low level, and the output of NAND4 is inverted from low level to high level.

Due to the low level from NAND3, the output of NAND7 is inverted from low level to high level. Then, NAND9 inverts the output from high level to low level due to the high level from NAND7 and NAND8. Then, the duty correction circuit 310 generates an output clock OP having the same falling edge timing as the received clock signal CLK (FIG. 10 (z1)). Therefore, the data reception processing circuit 321 can receive the data signal DATA transmitted from the data transmission processing circuit 211 in synchronization with the falling edge of the output clock OP having the same phase as the original clock signal CLK (Fig. 10(z2)).

FIG. 11 is a timing diagram showing another example of the operation in which the duty correction circuit 319 of FIG. 6 corrects the duty ratio of the clock signal CLK to 50%. The system 100 equipped with the duty correction circuit 319 employs a negative clock method in which transmission of the data signal DATA starts from the falling edge of the clock signal CLK. Detailed description of operations similar to those in FIGS. 3 to 5 and 7 will be omitted. FIG. 11 shows an example where the duty ratio of the clock signal CLK received from the data transmission processing circuit 211 is greater than 50%.

In the duty correction circuit 319, when the input clock IP changes from high level to low level (FIG. 11(a)), the output of NAND1 changes to low level, but since the output of NAND4 is low level, the output of NAND3 remains high. maintained at the level. Therefore, the output clock OP is held at a high level (FIG. 11(b)). That is, when the input clock IP changes from high level to low level, the duty correction circuit 319 performs a duty correction operation to maintain the high level of the output clock OP (FIG. 11(c)).

Next, when the input clock IN changes from low level to high level (FIG. 11(d)), the output of NAND2 changes to low level, and the output of NAND4 changes to high level. Since the output of NAND1 is at high level, the output clock OP, which is the output of NAND3, changes from high level to low level (FIG. 11(e)). Therefore, the phase of the falling edge of the output clock OP lags behind the phase of the falling edge of the input clock IP (clock signal CLK).

Next, when the input clock IN changes from high level to low level (Fig. 11(f)), the output of NAND2 changes to high level, but since the output of NAND3 is low level, the output of NAND4 changes to high level. maintained. Therefore, the output clock OP is held at low level (FIG. 11(g)). That is, when the input clock IN changes from high level to low level, the duty correction circuit 319 performs a duty correction operation to maintain the low level of the output clock OP (FIG. 11(h)).

Next, when the input clock IP changes from low level to high level (Fig. 11(i)), the output of NAND1 changes to low level and the output of NAND3 changes to high level, so the output clock OP changes from low level to high level. level (Fig. 11(j)). Therefore, the phase of the rising edge of the output clock OP lags behind the phase of the rising edge of the input clock IP (clock signal CLK).

Therefore, the duty correction circuit 319 in FIG. 6 cannot generate the output clock OP having the same phase as the phase of the clock signal CLK output by the data transmission processing circuit 211 even in the negative clock method. Therefore, the setup margin and hold margin of the data signal DATA output from the data transmission processing circuit 211 with respect to the clock signal CLK are reduced. In the worst case, the data transmission processing circuit 211 cannot receive the data signal DATA.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. That is, in the negative clock method, the duty correction circuit 311 can generate the output clock OP matching the phase of the received clock signal CLK while correcting the duty ratio of the received clock signal CLK to 50%. As a result, even when receiving the clock signal CLK whose duty ratio is not 50%, the receiving section 300 transmits the data signal DATA in synchronization with the output clock OP having the same phase as the clock signal CLK output from the data transmission processing circuit 211. can be received.

(Third embodiment)
FIG. 12 is a block diagram showing an example of a system including a duty correction circuit according to the third embodiment of the present invention. The same elements as in FIG. 1 are given the same reference numerals, and detailed explanations are omitted. The system 102 shown in FIG. 12 includes a transmitter 202 and a receiver 302 that are connected to each other via a signal line.

The transmitting section 202 is similar to the transmitting section 200 shown in FIG. 1 except that it includes a clock output circuit 222 instead of the data transmission processing circuit 210 of the transmitting section 200 shown in FIG. The clock output circuit 222 outputs differential clock signals CLKP and CLKN each having a duty ratio of 50%. Clock signal CLKP is a positive clock signal whose generation starts from a rising edge. Clock signal CLKN is a negative clock signal whose generation starts from a falling edge.

The receiving unit 302 includes the duty correction circuit 310 shown in FIG. 1, the duty correction circuit 311 shown in FIG. 9, and hardware IP (Intellectual Property) 322. The duty correction circuit 310 corrects the duty ratio of the received clock signal CLKP to 50% and outputs it to the hardware IP322. The duty correction circuit 311 corrects the duty ratio of the received clock signal CLKN to 50% and outputs it to the hardware IP 322. Note that the duty ratio of the clock signals CLKP and CLKN of the hardware IP 322 is defined to be, for example, 50%±5%.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, even when the receiving unit 302 receives the differential clock signals CLKP and CLKN, the duty ratio of each is corrected to 50% regardless of the polarity of the clock signals CLKP and CLKN, and the hardware It can be output to IP322.

FIG. 13 is a circuit diagram showing an example of a duty correction circuit according to the fourth embodiment of the present invention. The same elements as in FIG. 2 are given the same reference numerals, and detailed explanations are omitted. A system equipped with the duty correction circuit 312 shown in FIG. 13 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is transmitted as a positive clock signal or a negative clock signal. be done.

The duty correction circuit 312 operates as if the clock signal CLK is a positive clock signal when the logical value of the control signal P is "1", and operates as if the clock signal CLK is a negative clock signal when the logical value of the control signal P is "0". It operates as if it were a clock signal. In this way, whether the clock signal CLK is a positive clock signal or a negative clock signal is determined according to the control signal P indicating the clock mode of the systems 100 and 101.

For example, when the duty correction circuit 312 is installed in the receiving section 300 of the system 100 shown in FIG. Fixed. Furthermore, when the duty correction circuit 312 is installed in the receiving section 301 of the system 101 shown in FIG. Fixed.

In this way, the duty correction circuit 312 can be installed in both the system 100 that uses a positive clock signal and the system 101 that uses a negative clock method. Therefore, the duty correction circuit 311 in FIG. 1 and the duty correction circuit 311 in FIG. 8 can be replaced with one duty correction circuit 312. As a result, the cost for developing the duty correction circuit 312 can be reduced compared to the case where the duty correction circuits 310 and 311 are developed individually.

Note that in a system that can operate in either a positive clock method or a negative clock method by switching the clock mode, the logical value of the control signal P may be switched depending on the clock mode.

Duty correction circuit 312 includes inverters IV1, IV2, NAND10, NAND11, and NOR2 instead of NAND5 and NAND6 of duty correction circuit 310 in FIG. In the following, the inverters IV will be referred to as IV1, IV2, etc. only by their symbols. NAND1-NAND4, NAND7-NAND11, NOR2, IV1, and IV2 are examples of logic setting circuits that set the logic of the output clock OP.

NAND10 has three inputs that receive input clocks IP, IN and control signal P, and its output is connected to one input of NAND11. The NAND 10 becomes valid when the logical value of the control signal P is "1", and receives input clocks IP and IN, which are positive clocks, and performs control to generate an output clock OP.

NOR2 has three inputs that receive input clocks IP and IN and a control signal P whose logic value is inverted by inverter IV1, and its output is connected to the other input of NAND11. NOR2 becomes valid when the logical value of control signal P is "0", and performs control to generate output clock OP by receiving input clocks IP and IN, which are negative clocks. The output of NAND11 is connected to the other input of NAND7, and is connected to one input of NAND8 via inverter IV2.

As a result, when the logical value of the control signal P is set to "1", the duty correction circuit 312 adjusts the duty ratio of the clock signal CLK, which is a positive clock signal, similarly to the duty correction circuit 310 shown in FIG. Perform an operation to correct it to 50%. Further, when the logical value of the control signal P is set to "0", the duty correction circuit 312 adjusts the duty ratio of the clock signal CLK, which is a negative clock signal, to 50, similarly to the duty correction circuit 311 shown in FIG. %.

FIG. 14 is a timing diagram showing an example of the operation when the duty correction circuit 312 of FIG. 13 receives a positive clock signal. That is, FIG. 14 shows an example of a duty correction method by the duty correction circuit 312. The waveform of the clock signal CLK shown in FIG. 14 is, for example, the waveform output by the data transmission processing circuit 210 of the transmitter 200 shown in FIG. 1. The waveform of the clock signal CLK received by the duty correction circuit 312 is shown as the waveform of the input clock IP. The logical value of control signal P is set to "1".

As shown in the upper timing waveform of FIG. 14, the duty correction circuit 312 can generate the output clock OP with a duty ratio of 50% even when the duty ratio of the clock signal CLK is smaller than 50%. Furthermore, as shown in the lower timing waveform of FIG. 14, the duty correction circuit 312 can generate the output clock OP with a duty ratio of 50% even when the duty ratio of the clock signal CLK is greater than 50%. can.

FIG. 15 is a timing diagram showing an example of the operation when the duty correction circuit 312 of FIG. 13 receives a negative clock signal. That is, FIG. 15 shows an example of a duty correction method by the duty correction circuit 312. The waveform of the clock signal CLK shown in FIG. 15 is, for example, the waveform output by the data transmission processing circuit 211 of the transmitter 201 shown in FIG. 8. The waveform of the clock signal CLK received by the duty correction circuit 312 is shown as the waveform of the input clock IP. The logical value of control signal P is set to "0".

As shown in the upper timing waveform of FIG. 15, the duty correction circuit 312 can generate the output clock OP with a duty ratio of 50% even when the duty ratio of the clock signal CLK is smaller than 50%. Further, as shown in the timing waveform on the lower side of FIG. 15, the duty correction circuit 312 can generate the output clock OP with a duty ratio of 50% even when the duty ratio of the clock signal CLK is greater than 50%. can.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, the duty correction circuit 312 can be installed in both the system 100 that uses a positive clock signal and the system 101 that uses a negative clock method. As a result, the development cost of the systems 100 and 101 can be reduced compared to the case where the duty correction circuits 310 and 311 are developed respectively.

In a system where the clock signal CLK switches to a positive clock signal or a negative clock signal depending on the clock mode, the duty ratio of the received clock signal CLK can be corrected to generate an output clock OP with a duty ratio of 50%. That is, one duty correction circuit 312 can correct the duty ratio of the clock signal CLK in both the positive clock system and the negative clock system.

(Fifth embodiment)
FIG. 16 is a circuit diagram showing an example of a duty correction circuit according to the fifth embodiment of the present invention. The same elements as in FIGS. 2 and 13 are given the same reference numerals, and detailed explanations are omitted. A system equipped with the duty correction circuit 313 shown in FIG. 16 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is a positive clock signal or Transmitted as a negative clock signal. The duty correction circuit 313 includes 10 NAND21-NAND30, 5 IV21-IV25, and a phase shift circuit 318. NAND21-NAND30 and IV21-IV25 are examples of logic setting circuits that set the logic of the output clock OP.

One input of NAND21 is connected to the clock signal line CLK (input clock IP), and the other input of NAND21 is connected to the output of inverter IV22. One input of NAND22 is connected to the clock signal line CLK, and the other input of NAND22 is connected to the output of NAND24.

One input of NAND23 is connected to the output of inverter IV22, and the other input of NAND23 is connected to the output of NAND24. Three inputs of NAND24 are connected to outputs of NAND21, NAND22, and NAND23, respectively.

The upper input of the NAND 25 is connected to the clock signal line CLK, the center input of the NAND 25 is connected to the output (input clock IN) of the phase shift circuit 318, and the lower input of the NAND 25 is connected to the control signal line P. Connected. The upper input of NAND26 is connected to the output of inverter IV21, the center input of NAND26 is connected to the output of inverter IV22, and the lower input of NAND26 is connected to the output of inverter IV23.

Inverter IV21 inverts the logical value of input clock IP, inverter IV22 inverts the logical value of input clock IN from phase shift circuit 318, and inverter IV23 inverts the logical value of control signal P. One input of NAND27 is connected to the output of NAND25, and the other input of NAND27 is connected to the output of NAND26.

One input of NAND28 is connected to the output of NAND24, and the other input of NAND28 is connected to the output of NAND27. One input of NAND29 is connected to the output of NAND24 via inverter IV24, and the other input of NAND29 is connected to the output of NAND27 via inverter IV25. One input of NAND30 is connected to the output of NAND28, and the other input of NAND30 is connected to the output of NAND29. Then, an output clock OP whose duty ratio has been corrected to 50% is output from the output of the NAND 30.

Similar to the duty correction circuit 312 shown in FIG. 13, the duty correction circuit 313 of this embodiment sets the duty ratio to 50% by using the clock signal CLK as a positive clock signal when the logical value of the control signal P is "1". Perform corrective action. Further, when the logical value of the control signal P is "0", the duty correction circuit 313 assumes that the clock signal CLK is a negative clock signal and performs an operation of correcting the duty ratio to 50%. The operation timing of the duty correction circuit 313 is the same as in FIGS. 14 and 15 described above.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. For example, the duty ratio of the positive clock type clock signal CLK can be corrected to 50%, and the duty ratio of the negative clock type clock signal CLK can be corrected to 50%. Further, depending on the logical value of the control signal P, the duty ratio of the clock signal CLK in both the positive clock system and the negative clock system can be corrected by one duty correction circuit 313.

(Sixth embodiment)
FIG. 17 is a circuit diagram showing an example of a receiving circuit including a duty correction circuit according to the sixth embodiment of the present invention. The same elements as in FIGS. 2 and 13 are given the same reference numerals, and detailed explanations are omitted. A system equipped with the duty correction circuit 314 shown in FIG. 17 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is a positive clock signal or Transmitted as a negative clock signal.

The receiving circuit 330 shown in FIG. 17 is installed in the receiving section 300 shown in FIG. 1 or the receiving section 301 shown in FIG. 8. The receiving circuit 330 includes a duty correction circuit 314 and a data delay adjustment circuit 340. The duty correction circuit 314 has buffer circuits BUF11 and BUF12 and delay circuits DLY1, DLY2, and DLY3 added to the duty correction circuit 312 shown in FIG. 13. For example, delay circuits DLY1, DLY2, and DLY3 are the same circuit and have the same delay time as the delay time of inverter IV2. Further, the delay circuits DLY1 to DLY3 are variable delay circuits whose delay times can be finely adjusted. NAND1-NAND4, NAND7-NAND11, NOR2, IV1, IV2 and delay circuits DLY1-DLY3 are examples of logic setting circuits that set the logic of output clock OP.

Buffer circuit BUF11 receives clock signal CLK and outputs input clock IP. The buffer circuit BUF12 has an input connected to the output of NAND9, and outputs an output clock OP. Delay circuit DLY1 is arranged between the output of NAND3 and one input of NAND7. Delay circuit DLY2 is arranged between the output of NAND4 and the other input of NAND8. Delay circuit DLY3 is arranged between the output of NAND11 and the other input of NAND7.

By adding delay circuits DLY1 to DLY3 having the same delay time as inverter IV2 to the signal paths from NAND3, NAND4, and NAND11 to NAND7 and NAND8, the amount of delay of the signals received by NAND7 and NAND8 can be made equal. This can be achieved by making the number of logic gates from the first stage logic gate connected to the output of the buffer circuit BUF11 to the buffer circuit BUF12 equal to the number of logic stages from the control signal line P to the buffer circuit BUF12. can. Furthermore, by making the delay circuits DLY1 to DLY3 variable delay circuits, the amount of delay can be made uniform even when, for example, a signal output from NAND3 passes through NAND4.

Thereby, regardless of the logical value of the control signal P, signals can be supplied to NAND7 and NAND8 at the same timing, and the accuracy of generating the output clock OP with a duty ratio of 50% can be improved. Note that since the control signal P is a signal whose logical value is fixed during operation of the system, there is no need to arrange a delay circuit in the input path of the control signal P. That is, the delay circuit shown by the broken triangle in the input path of the control signal P is unnecessary.

The data delay adjustment circuit 340 gives each of the received n+1 data signals DATA the same delay time as the delay time from the clock signal CLK to the output clock OP by the duty correction circuit 314. Therefore, the data delay adjustment circuit 340 includes buffer circuits BUF13, NAND12, NAND13, and delay circuits DLY4, NAND14, and NAND15, which are arranged in series on the transmission path of each data signal DATA.

For example, the buffer circuit BUF13 is the same circuit as the buffer circuit BUF11, and the buffer circuit BUF14 is the same circuit as the buffer circuit BUF12. For example, NAND12-NAND15 are the same circuits as NAND1-NAND4 and NAND7-NAND11. For example, the delay circuit DLY4 is the same circuit as the delay circuits DLY1-DLY3, and is a variable delay circuit.

Thereby, the number of gate stages of the data delay adjustment circuit 340 and the duty correction circuit 314 can be made equal to each other. Further, the amount of delay of the data signal DATA by the data delay adjustment circuit 340 can be made the same as the amount of delay of the clock signal CLK by the duty correction circuit 314. Note that the delay circuit DLY4 is provided to match the number of gate stages with the duty correction circuit 314 and to adjust the delay amount in accordance with the adjustment of the delay amount of the delay circuits DLY1 to DLY3.

Then, the data delay adjustment circuit 340 delays the received data signals DATA_IN[0] to DATA_IN[n] and outputs them as delayed data signals DATA_OUT[0] to DATA_OUT[n]. The delayed data signals DATA_OUT[0] to DATA_OUT[n] are supplied together with the output clock OP to the data reception processing circuit 320 shown in FIG. 1 or the data reception processing circuit 321 shown in FIG. 8. The data reception processing circuits 320 and 321 are examples of data reception circuits that receive delayed data signals DATA_OUT[0] to DATA_OUT[n] in synchronization with the output clock OP. The operation timing of the duty correction circuit 314 is the same as in FIGS. 14 and 15 described above.

Note that the duty correction circuit 314 may be configured by adding buffer circuits BUF21 and BUF22 and delay circuits DLY1, DLY2, and DLY3 to the duty correction circuit 313 shown in FIG. 16.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, the data delay adjustment circuit 340 provides the data signal DATA with the same delay amount as the internal delay amount of the duty correction circuit 314, thereby delaying the delayed data corresponding to the delay amount of the output clock OP. A signal DATA_OUT can be generated. As a result, the data reception processing circuits 320 and 321 can receive and process the delayed data signal DATA_OUT in accordance with the amount of delay of the output clock OP, and the timing margin can be improved.

Note that the delay circuits DLY1, DLY2, and DLY3 may be provided in the duty correction circuit 310 in FIG. 2, the duty correction circuit 311 in FIG. 9, or the duty correction circuit 313 in FIG. 16.

(Seventh embodiment)
FIG. 18 is a circuit diagram showing an example of a receiving circuit including a duty correction circuit according to the seventh embodiment of the present invention. Elements that are the same as those in FIGS. 2, 13, and 17 are given the same reference numerals, and detailed explanations will be omitted. A system equipped with the duty correction circuit 315 shown in FIG. 18 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is a positive clock signal or Transmitted as a negative clock signal.

The receiving circuit 350 shown in FIG. 18 is installed in a receiving section similar to the receiving section 300 shown in FIG. 1 or the receiving section 301 shown in FIG. 8. However, the receiving section of this embodiment receives differential clock signals CLK+ and CLK- and differential data signals DATA_IN+ and DATA_IN-. The receiving circuit 350 includes a duty correction circuit 315 and a data delay adjustment circuit 340. The duty correction circuit 315 has buffer circuits BUF21 and BUF22 and delay circuits DLY1, DLY2, and DLY3 added to the duty correction circuit 312 shown in FIG. 13. NAND1-NAND4, NAND7-NAND11, NOR2, IV1, IV2 and delay circuits DLY1-DLY3 are examples of logic setting circuits that set the logic of output clock OP.

In this embodiment, differential clock signals CLK+ and CLK- and differential data signals DATA_IN+ and DATA_IN- are transmitted between the transmitter 200 and the like and the receiver 300 and the like in FIG. Therefore, the buffer circuit BUF21 receives the differential clock signals CLK+ and CLK- and outputs the single-ended input clock IP. The buffer circuit BUF22 receives the single-ended output clock OP and outputs differential output clocks OP+ and OP-. The operation timing of the duty correction circuit 315 is the same as in FIGS. 14 and 15 described above.

Similar to the data delay adjustment circuit 340 shown in FIG. 17, the data delay adjustment circuit 360 applies the same delay time as the delay time from the input clock IP to the output clock OP by the duty correction circuit 315 to the received n+1 data signals. Give each to DATA. For this reason, the data delay adjustment circuit 360, like the data delay adjustment circuit 340, includes NAND12, NAND13, and delay circuits DLY4, NAND14, and NAND15.

Further, the data delay adjustment circuit 360 includes buffer circuits BUF23 and BUF24 instead of the buffer circuits BUF13 and BUF14 of the data delay adjustment circuit 340 shown in FIG. Buffer circuit BUF23 receives differential data signals DATA_IN+ and DATA_IN- and outputs single-ended data signal DATA_IN. The buffer circuit BUF24 receives the single-ended delayed data signal DATA_OUT and outputs differential delayed data signals DATA_OUT+ and DATA_OUT-.

The data delay adjustment circuit 360 delays the received data signals DATA_IN+, DATA_IN- (DATA_IN[0]+ to DATA_IN[n]+, data signals DATA_IN[0]- to DATA_IN[n]-). The data delay adjustment circuit 360 then outputs delayed data signals DATA_OUT+ and DATA_OUT-. The delayed data signals DATA_OUT+ and DATA_OUT- are supplied to a data receiving circuit (not shown) together with the output clock OP. The data receiving circuit receives delayed data signals DATA_OUT[0] to DATA_OUT[n] in synchronization with the output clock OP. For example, the data receiving circuit has a built-in SerDes (SERializer/DESerializer), and the clock signals CLK+, CLK- and data signals DATA_IN+, DATA_IN- are transmitted using an LVDS (Low Voltage Differential Signal) interface. .

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, in a system in which differential clock signals CLK+ and CLK- are transmitted between the transmitting section and the receiving section, the duty ratio of the clock signals CLK+ and CLK- can be corrected to 50%. . Furthermore, the amount of delay of the data signals DATA_IN+ and DATA_IN- can be adjusted according to the amount of delay caused by the duty correction circuit 315. As a result, the data receiving circuit can receive and process the delayed data signals DATA_OUT+ and DATA_OUT+ in accordance with the amount of delay of the output clocks OP+ and OP-, and the timing margin can be improved.

(Eighth embodiment)
FIG. 19 is a circuit diagram showing an example of a duty correction circuit according to the eighth embodiment of the present invention. The same elements as in FIGS. 2 and 13 are given the same reference numerals, and detailed explanations are omitted. A system equipped with the duty correction circuit 316 shown in FIG. 19 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is a positive clock signal or Transmitted as a negative clock signal.

For example, the duty correction circuit 316 is installed in the receiving section 300 instead of the duty correction circuit 310 shown in FIG. 1, or in the receiving section 301 instead of the duty correction circuit 311 shown in FIG. Duty correction circuit 316 includes a switch circuit SW1 instead of NAND7, NAND8, NAND9 and inverter IV2 of duty correction circuit 312 shown in FIG. Further, the duty correction circuit 316 has the same buffer circuits BUF11 and BUF12 as in FIG. 7. NAND1 to NAND4, NAND10, NAND11, NOR2, IV1, and switch circuit SW1 are examples of a logic setting circuit that sets the logic of output clock OP.

Switch circuit SW1 connects the output of NAND3 to the input of buffer circuit BUF12 when the output of NAND11 is logic 0. Furthermore, when the output of NAND11 is logic 1, switch circuit SW1 connects the output of NAND4 to the input of buffer circuit BUF12.

The duty correction circuit 312 shown in FIG. 13 described above enables either the path of NAND7 and NAND9 or the path of NAND8 and NAND9 and outputs the output clock OP according to the logical value outputted by NAND11. The duty correction circuit 316 in FIG. 19 realizes the functions of NAND7, NAND8, NAND9 and inverter IV2 in FIG. 13 by a switch circuit SW1 controlled by the output of NAND11.

Thereby, the internal speed of the duty correction circuit 316 can be increased, and the circuit scale can be reduced. For example, the switch circuit SW1 can be configured with a CMOS (Complementary Metal Oxide Semiconductor) transmission gate including one p-channel transistor and one n-channel transistor, and an inverter that controls the transmission gate.

The signal transmission speed by the CMOS transmission gate can be made higher than the signal transmission speed by NAND7-NAND9 shown in FIG. Further, for example, a CMOS transmission gate, unlike a gate circuit such as a NAND, has no difference in propagation delay time of an output signal with respect to a rising edge and a falling edge of an input signal, so timing design etc. can be facilitated. Note that the operation timing of the duty correction circuit 314 is the same as in FIGS. 14 and 15 described above.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, the speed of the duty correction circuit 316 can be increased, the circuit scale can be reduced, and timing design can be facilitated.

(Ninth embodiment)
FIG. 20 is a circuit diagram showing an example of a duty correction circuit according to the ninth embodiment of the present invention. Elements that are the same as those in FIGS. 2, 13, and 19 are designated by the same reference numerals, and detailed description thereof will be omitted. The system equipped with the duty correction circuit 317 shown in FIG. 20 is similar to the system 100 shown in FIG. 1 and the system 101 shown in FIG. 8, but the clock signal CLK is a positive clock signal or Transmitted as a negative clock signal.

For example, the duty correction circuit 317 is installed in the receiving section 300 instead of the duty correction circuit 310 shown in FIG. 1, or in the receiving section 301 instead of the duty correction circuit 311 shown in FIG. The duty correction circuit 317 has buffer circuits BUF21 and BUF22 shown in FIG. 18 instead of the buffer circuits BUF11 and BUF12 of the duty correction circuit 316 shown in FIG. 19. Then, the duty correction circuit 3107 corrects the duty ratio of the differential clock signals CLK+ and CLK- to 50% and outputs them as differential output locks OP+ and OP-. The other configurations are the same as the duty correction circuit 316 shown in FIG. 19.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. Furthermore, in this embodiment, in a system in which differential clock signals CLK+ and CLK- are transmitted between the transmitting section and the receiving section, the duty correction circuit 317 can be made faster and the circuit scale can be reduced. This makes timing design easier.

FIG. 21 is a block diagram showing an example of a system in which the duty correction circuit of the embodiment described above is installed. For example, the system 103 shown in FIG. 21 is included in a multifunction printer called an MFP (MultiFunction Printer), and in the example shown in FIG. 21, it is installed in a scanner device equipped with an automatic document feeder (ADF). . The scanner device includes a back scanner 410, a front scanner 420, an IPU (Image Processing Unit) board 430, and a controller board 440.

The back scanner 410 outputs back image data read by, for example, a CIS (Contact Image Sensor) to the IPU board 430 through an LVDS interface. Similarly, the front side scanner 420 outputs the front side image data read by the CIS to the IPU board 430 through the LVDS interface.

The IPU board 430 includes LVDS repeaters 431 and 432, a preprocessing section 433, and an IPU 434. The LVDS repeater 431 outputs the back side image data received from the back side scanner 410 to the preprocessing unit 433. LVDS repeater 432 outputs the front surface image data received from front scanner 420 to preprocessing section 433.

The preprocessing unit 433 performs preprocessing on the back image data received from the back scanner 410, and outputs the preprocessed back image data to the IPU 434 via the LVDS interface. Further, the preprocessing unit 433 performs preprocessing on the front surface image data received from the front scanner 420, and outputs the preprocessed front surface image data to the IPU 434 via the LVDS interface. For example, the preprocessing is format conversion of image data. The IPU 434 performs image processing on the received back side image data and front side image data, and writes the data into a memory (not shown) in the controller board 440 via, for example, a PCIe interface.

For example, the duty correction circuit 315 shown in FIG. 18 or the duty correction circuit 317 shown in FIG. It will be done. Signals marked with dashed circles include clock signals CLK+, CLK- and data signals DATA+, DATA-. This facilitates board design (timing design) of the scanner device. Furthermore, since the signal quality can be improved, the reliability of the scanner device can be improved.

FIG. 22 is a block diagram showing another example of a system in which the duty correction circuit of the embodiment described above is installed. For example, the system 104 shown in FIG. 21 is installed in a printer included in an MFP. The printer includes, for example, a post-processing section 450 connected to the IPU 434 and CPU (Central Processing Unit) 435 of the IPU board 430 in FIG. 21, and a printer control section 460. The post-processing unit 450 converts the written image data, such as CMYK (Cyan, Magenta, Yellow, Key plate), processed by the IPU 434 into a format, and sends it to the printer control unit 460 . The printer control unit 460 controls a printer engine (not shown) or the like to print the written image data on paper or the like.

For example, the duty correction circuit 310 in FIG. 2, the duty correction circuit 311 in FIG. 9, the duty correction circuit 312 in FIG. and printer control unit 460, respectively. This facilitates printer board design (timing design). Furthermore, since the signal quality can be improved, the reliability of the printer can be improved.

FIG. 23 is a block diagram showing still another example of a system in which the duty correction circuit of the embodiment described above is installed. For example, the system 105 shown in FIG. 21 is installed in an image processing device that processes image data obtained by imaging by the right camera 510 and the left camera 520, and sends the processed image data to a processor for image processing.

The image processing device includes a video preprocessing device 530 that performs image processing on video data input from the right camera 510 and the left camera 520, and a video processing processor 540 that processes the video data processed by the video preprocessing device 530. has.

For example, the duty correction circuit 310 in FIG. 2, the duty correction circuit 311 in FIG. 9, the duty correction circuit 312 in FIG. established in This facilitates board design and chip design (timing design) of the image processing device. Furthermore, since the signal quality can be improved, the reliability of the image processing device can be improved.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without detracting from the gist of the present invention, and can be determined appropriately depending on the application thereof.

100, 101, 102, 103, 104, 105 System 200, 201, 202 Transmitting section 210, 211 Data transmission processing circuit 222 Clock output circuit 300, 301, 302 Receiving section 310, 311, 312, 313 Duty correction circuit 314, 315 , 316, 317 Duty correction circuit 318 Phase shift circuit 320, 321 Data reception processing circuit 322 Hardware IP
330 Receiving circuit 340 Data delay adjustment circuit 350 Receiving circuit 410 Back scanner 420 Front scanner 430 IPU board 440 Controller board 431, 432 LVDS repeater 433 Preprocessing section 434 IPU
435 CPU
450 rear processing unit 460 printer control unit 510 Right camera 520 Left camera 530 Video Processing device 540 Video processor processor CLK, CLK +, CLK -Clock signal Data, Data_in +, Data_in -Data_in -Data Signal Data_ut +, Data_OUT -delayed data signal Dly1, Dly2, DLY3, DLY4 Delay circuit IN, IP Input clock OP Output clock P Control signal SW1 Switch circuit

Japanese Patent Application Publication No. 2011-120106

Claims (8)

a phase shift circuit that generates a shift clock whose phase is shifted by 180 degrees with respect to the received input clock;
inverting the logical value of an output clock in response to one of the rising edge or the falling edge of the input clock and the shift clock, and in response to the other of the rising edge or the falling edge of the input clock and the shift clock; a logic setting circuit that holds the logic value of the output clock immediately before the other edge appears;
The logic setting circuit is
a first flip-flop having a first NAND gate receiving the input clock and a second NAND gate receiving the shift clock;
a second flip-flop having a third NAND gate receiving the output signal of the first NAND gate and a fourth NAND gate receiving the output signal of the second NAND gate;
A low level is output when the input clock and the shift clock are both high level in a positive clock mode in which the leading edge of the input clock is a rising edge, and a high level in a negative clock mode in which the leading edge of the input clock is a falling edge. a fifth NAND gate that outputs
a NOR gate that outputs a high level when the input clock and the shift clock are both low in the positive clock mode, and outputs a low level in the negative clock mode;
a sixth NAND gate receiving the output signal of the fifth NAND gate and the output signal of the NOR gate;
a seventh NAND gate receiving the output signal of the third NAND gate and the output signal of the sixth NAND gate;
an eighth NAND gate receiving a signal obtained by inverting the output signal of the fourth NAND gate and the output signal of the sixth NAND gate;
a ninth NAND gate that receives the output signal of the seventh NAND gate and the output signal of the eighth NAND gate and outputs the output clock;
A duty correction circuit, wherein a transition direction of one of the rising edge and the falling edge that inverts the logical value of the output clock is the same as the transition direction of the leading edge of the input clock. 2. The duty correction circuit according to claim 1, wherein logical values of the input clock and the output clock are the same in an initial state before the leading edge appears. The logic setting circuit is
When a control signal indicating that the leading edge of the input clock is a rising edge is received, the logic value of the output clock is inverted in response to the rising edges of the input clock and the shift clock, and the logic value of the output clock is inverted. responsive to the falling edge of the shift clock, holding the logical value of the output clock immediately before the falling edge appeared;
When receiving the control signal indicating that the leading edge of the input clock is a falling edge, inverting the logical value of the output clock in response to the falling edges of the input clock and the shift clock; 3. The duty correction circuit according to claim 1, wherein in response to the rising edge of the input clock and the shift clock , the logic value of the output clock immediately before the rising edge appears is held . The logic setting circuit has a number of stages from a first-stage logic gate that receives the control signal to a logic gate that outputs the output clock, and a logic that outputs the output clock from the first-stage logic gate that receives the input clock and the shift clock. 4. The duty correction circuit according to claim 3, wherein the number of stages up to the gate is equal. a duty correction circuit that generates an output clock by correcting the duty ratio of the received input clock;
a data delay adjustment circuit that adjusts a delay amount of a data signal supplied in synchronization with the input clock and outputs a delayed data signal;
a data receiving circuit that receives the delayed data signal in synchronization with the output clock;
The duty correction circuit is
a phase shift circuit that generates a shift clock whose phase is shifted by 180 degrees with respect to the received input clock;
inverting the logical value of the output clock in response to one of the rising edge or the falling edge of the input clock and the shift clock, and in response to the other of the rising edge or the falling edge of the input clock and the shift clock; and a logic setting circuit that holds the logic value of the output clock immediately before the other edge appears,
The logic setting circuit is
a first flip-flop having a first NAND gate receiving the input clock and a second NAND gate receiving the shift clock;
a second flip-flop having a third NAND gate receiving the output signal of the first NAND gate and a fourth NAND gate receiving the output signal of the second NAND gate;
A low level is output when the input clock and the shift clock are both high level in a positive clock mode in which the leading edge of the input clock is a rising edge, and a high level in a negative clock mode in which the leading edge of the input clock is a falling edge. a fifth NAND gate that outputs
a NOR gate that outputs a high level when the input clock and the shift clock are both low in the positive clock mode, and outputs a low level in the negative clock mode;
a sixth NAND gate receiving the output signal of the fifth NAND gate and the output signal of the NOR gate;
a seventh NAND gate receiving the output signal of the third NAND gate and the output signal of the sixth NAND gate;
an eighth NAND gate receiving a signal obtained by inverting the output signal of the fourth NAND gate and the output signal of the sixth NAND gate;
a ninth NAND gate that receives the output signal of the seventh NAND gate and the output signal of the eighth NAND gate and outputs the output clock;
The one transition direction of the rising edge or the falling edge that inverts the logical value of the output clock is the same as the transition direction of the leading edge of the input clock,
The number of stages from the first-stage logic gate that receives the data signal to the logic gate that outputs the delayed data signal in the data delay adjustment circuit is such that in the logic setting circuit, the first-stage logic gate that receives the input clock outputs the output clock. The receiving circuit is equal to the number of stages up to the logic gate. The duty correction circuit corrects the duty ratio of the differential input clock,
6. The receiving circuit according to claim 5, wherein the data delay adjustment circuit adjusts a delay amount of the differential data signal. a phase shift circuit that generates a shift clock whose phase is shifted by 180 degrees with respect to the received input clock;
a first flip-flop having a first NAND gate receiving the input clock and a second NAND gate receiving the shift clock; a third NAND gate receiving the output signal of the first NAND gate; and a fourth NAND gate receiving the output signal of the second NAND gate. a second flip-flop having a gate, and outputs a low level when the input clock and the shift clock are both at high level in a positive clock mode in which the leading edge of the input clock is a rising edge; a fifth NAND gate that outputs a high level when the negative clock mode is a falling edge, outputs a high level when the input clock and the shift clock are both low levels during the positive clock mode, and outputs a low level when the negative clock mode a sixth NAND gate receiving the output signal of the fifth NAND gate and the output signal of the NOR gate; a seventh NAND gate receiving the output signal of the third NAND gate and the output signal of the sixth NAND gate; an eighth NAND gate that receives the output signal of the fourth NAND gate and an inverted signal of the output signal of the sixth NAND gate; and a ninth NAND gate that receives the output signal of the seventh NAND gate and the output signal of the eighth NAND gate and outputs an output clock. a logic setting circuit having a gate;
A duty correction method using a duty correction circuit having:
inverting the logical value of the output clock in response to one of the rising edge or the falling edge of the input clock and the shift clock, and in response to the other of the rising edge or the falling edge of the input clock and the shift clock; and hold the logical value of the output clock immediately before the other edge appears;
The duty correction method, wherein the one transition direction of the rising edge or the falling edge is the same as the transition direction of the leading edge of the input clock. When a control signal indicating that the leading edge of the input clock is a rising edge is received, the logic value of the output clock is inverted in response to the rising edges of the input clock and the shift clock, and the logic value of the output clock is inverted. responsive to the falling edge of the shift clock, holding the logical value of the output clock immediately before the falling edge appeared;
When receiving the control signal indicating that the leading edge of the input clock is a falling edge, inverting the logical value of the output clock in response to the falling edges of the input clock and the shift clock; 8. The duty correction method according to claim 7, wherein the logical value of the output clock immediately before the rising edge appears is held in response to the rising edge of the input clock and the shift clock.

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