JP2008131103A - Frequency division clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency division clock generating circuit which generates no phase inversion phenomenon between a system clock and a frequency division clock even at an end of a clock wiring. <P>SOLUTION: The frequency division clock generating circuit 1 comprises a frequency divider 11 which outputs a basic frequency division clock PH generated by dividing the frequency of the system clock FPH, a phase decision circuit 12 which decides whether the system clock FPHD at the clock wiring end leads or lags in phase with respect to the basic frequency division clock PH and outputs a decision signal SEL, a synchronism delay circuit 13 which outputs a delayed frequency division clock PHT generated by synchronizing the basic frequency division clock PH with the system clock FPHD at the wiring end and then delaying it, and a selecting circuit 14 which selects the delayed frequency division clock PHT when the decision signal SEL output from the phase decision circuit 12 shows a phase lag or the basic frequency division clock PH when the decision signal SEL shows a phase lead, and outputs it as a frequency division clock PHS. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a divided clock generation circuit.

  When a clock is distributed to a semiconductor integrated circuit, a divided clock obtained by dividing the system clock by a divider circuit may be distributed together with the distribution of the system clock serving as a reference for operation timing. The internal circuit of the semiconductor integrated circuit receives the distribution of the system clock and the divided clock and controls the operation timing. As an example, a system clock and a divided clock are input to an AND gate, and an output thereof is used as a clock of a flip-flop of an internal circuit.

  Normally, when such a clock distribution is performed, the frequency-divided clock is considered to be delayed by the delay time of the frequency-dividing circuit with respect to the system clock, and the circuit timing design is performed on the assumption. However, due to the increase of distributed constant wiring delay accompanying the recent miniaturization of semiconductor integrated circuit wiring, the phase of the system clock at the end of the clock wiring is delayed relative to the divided clock depending on the routing of the clock wiring. The reversal phenomenon may occur.

  When such a phase inversion phenomenon occurs, a short pulse called a glitch is generated at the output of the AND gate to which the system clock and the divided clock are input. When such a glitch occurs, there arises a problem that a flip-flop using the output of the AND gate as a clock malfunctions. Further, since the power supply current flows with the change of the glitch waveform, there arises a problem that the consumption current of the semiconductor integrated circuit increases.

  Therefore, a glitch eater circuit has been proposed as a circuit for removing such a glitch (see, for example, Patent Document 1). By this glitch eta circuit, the glitch superimposed on the input signal is removed.

However, it is necessary to provide one glitch eater circuit as described above for each circuit where a glitch occurs. For this reason, when there are many circuits in which glitches occur, a large number of glitch eater circuits are required, which increases the circuit scale of the semiconductor integrated circuit.
Japanese Patent Laid-Open No. 10-290146 (Page 4, FIG. 5)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a divided clock generation circuit that does not cause a phase reversal phenomenon between a system clock and a divided clock even at the end of a clock wiring.

  According to one aspect of the present invention, there is provided a divided clock generation circuit for distributing a divided clock obtained by dividing a system clock distributed to an internal circuit of a semiconductor integrated circuit to the internal circuit of the semiconductor integrated circuit, the system Frequency dividing means that divides the clock and outputs it as a basic divided clock, and the phase of the system clock at the wiring end that distributes the system clock to the internal circuit is delayed or advanced with respect to the phase of the basic divided clock A phase determination means for determining whether the basic frequency division clock is synchronized with a system clock at the end of the wiring, a delay means for delaying and outputting as a delay division clock, and a determination by the phase determination means When the phase is delayed, the delayed divided clock is selected. When the determination is the phase advanced, the basic divided clock is selected. Divided clock signal generator circuit comprising: a selecting means for outputting a divided clock is provided.

  According to the present invention, it is possible to prevent a phase inversion phenomenon from occurring between the system clock and the divided clock even at the end of the clock wiring.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing an example of the configuration of a divided clock generation circuit 1 according to an embodiment of the present invention.

  The frequency-divided clock generation circuit 1 of the present embodiment divides the system clock FPH distributed to the internal circuit of the semiconductor integrated circuit and outputs it as a basic frequency-divided clock PH, and the system clock FPH. A phase determination circuit 12 that determines whether the phase of the system clock FPHD at the end of the clock wiring where the wiring delay occurs is delayed or advanced with respect to the phase of the basic frequency-divided clock PH, and outputs a determination signal SEL; When the PH is synchronized with the system clock FPHD at the end of the wiring and then delayed and output as a delay divided clock PHT, and when the determination signal SEL output from the phase determination circuit 12 shows a phase delay, the delay When the divided clock PHT is selected and the determination signal SEL indicates phase advance, the basic divided clock PH is selected. Comprises a selection circuit 14 for outputting a divided clock PHS, a.

  Among these, FIG. 2 shows an example of a circuit configuration when the frequency divider 11 is a frequency divider circuit.

  The divide-by-2 circuit shown in FIG. 2 is a circuit that inverts the Q output of a commonly used master-slave flip-flop by an inverter 119 and connects it to the D input.

  The master-slave type flip-flop is formed by a master latch composed of a clocked inverter 113, an inverter 114 and a clocked inverter 115, and a slave latch composed of a clocked inverter 116, an inverter 117 and a clocked inverter 118. .

  Here, the clocked inverter 116 serving as the Q output of the master-slave flip-flop shown in this example is turned on when the CGV obtained by inverting the system clock FPH by the inverter 111 is at the “H” level. Therefore, the basic frequency-divided clock PH that outputs the output of the clocked inverter 116 via the buffer 120 changes in synchronization with the fall of the system clock FPH.

  Next, the phase determination circuit 12 shown in FIG. 1 detects both rising and falling edges of the basic frequency-divided clock PH, and outputs a PLS signal that is a pulse signal of “H” level. The AND gate 122 to which the PLS signal output from both the edge detection circuits 121 and the system clock FPHD at the end of the wiring are input, the output signal TRG of the AND gate 122 as a set input signal, and the system reset signal RST as a reset input signal RS flip-flop 123.

  FIG. 3 shows an example of the circuit configuration of the double edge detection circuit 121.

  Both edge detection circuits 121 include inverters 1211 to 1213 that delay and invert the basic frequency-divided clock PH, an AND gate 1214 to which the basic frequency-divided clock PH and the output of the inverter 1213 are input, the basic frequency-divided clock PH, and the inverter A NOR gate 1215 to which the output of 1213 is input and an OR gate 1216 to which the output of the AND gate 1214 and the NOR gate 1215 are input are provided, and the OR gate 1216 outputs the both-edge detection signal PLS.

  FIG. 4 is a waveform diagram showing how the double edge detection circuit 121 shown in FIG. 3 operates.

  An AND gate 1214 to which the basic frequency-divided clock PH and the output of the inverter 1213 obtained by inverting and delaying the basic frequency-divided clock PH output a pulse waveform of “H” level at the rising edge of the basic frequency-divided clock PH, and a NOR gate 1215. Outputs a pulse waveform at the “H” level at the falling edge of the basic frequency-divided clock PH. Therefore, the both-edge detection signal PLS, which is the output of the OR gate 1216 to which the output of the AND gate 1214 and the output of the NOR gate 1215 are input, rises and falls of the basic frequency-divided clock PH, that is, the “H” level at both edges. This is a signal that outputs a pulse waveform.

  Returning to FIG. 1, the AND gate 122 included in the phase determination circuit 12 determines that the phase of the system clock FPHD at the end of the wiring is delayed with respect to the phase of the basic frequency-divided clock PH, that is, the double-edge detection signal PLS is If the system clock FPHD at the end of the wiring is at the “H” level when outputting the pulse waveform, a pulsed TRG signal at the “H” level is output.

  The RS flip-flop 123 whose initial state is the reset state by the system reset signal RST is set by this TRG signal, and the output signal SEL becomes ‘H’.

  That is, when the phase of the system clock FPHD at the end of the wiring is delayed with respect to the phase of the basic frequency-divided clock PH, the output signal SEL of the phase determination circuit 12 becomes 'H'.

  On the other hand, when the phase of the system clock FPHD at the wiring end is advanced with respect to the phase of the basic frequency-divided clock PH, the system clock FPHD at the wiring end is 'L' when both edge detection signals PLS output a pulse waveform. Therefore, the TRG signal of the AND gate 122 becomes the “L” level.

  Therefore, the output signal SEL of the RS flip-flop 123 remains at the “L” level in the initial state.

  That is, when the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic frequency-divided clock PH, the output signal SEL of the phase determination circuit 12 becomes 'L'.

  Next, the synchronous delay circuit 13 will be described. FIG. 5 is a circuit diagram showing an example of the configuration of the synchronous delay circuit 13.

  The synchronous delay circuit 13 has a latch composed of a clocked inverter 134, an inverter 135, and a clocked inverter 136 whose input is a basic frequency-divided clock PH inverted by the inverter 133. The electrical characteristics of each element constituting this latch are the same as the electrical characteristics of each element constituting the slave latch shown in FIG. Further, the electrical characteristics of the inverter 137 and the buffer 138 that are the loads of the clocked inverter 134 are the same as the electrical characteristics of the inverter 119 and the buffer 120 that are the loads of the clocked inverter 116 shown in FIG. . As a result, the output delay of the clocked inverter 134 is equivalent to the output delay of the clocked inverter 116.

  The clocked inverter 134 is turned on when the CTV obtained by inverting the system clock FPHD at the end of the wiring by the inverter 131 is at the “H” level. Therefore, the delay-divided clock PHT that outputs the output of the clocked inverter 134 via the buffer 138 changes in synchronization with the falling edge of the system clock FPHD at the end of the wiring.

  That is, the synchronous delay circuit 13 takes in the basic frequency-divided clock PH into the latch, and outputs the delay-divided clock PHT synchronized with the falling of the system clock FPHD at the end of the wiring. At that time, the delay from the fall of the system clock FPHD at the end of the wiring until the delay divided clock PHT changes is the delay from the fall of the system clock FPH to the change of the basic divided clock PH in the frequency divider 11. It becomes equivalent.

  Next, the selection circuit 14 will be described.

  The selection circuit 14 shown in FIG. 1 receives a basic frequency division clock PH and a delay frequency division clock PHT as input signals to be selected, and an output signal SEL of the phase determination circuit as a selection switching input signal.

  The selection circuit 14 selects the delay divided clock PHT when the selection switching input signal SEL is 'H', and selects the basic division clock PH when the selection switching input signal SEL is 'L'. It is output as a divided clock PHS.

  That is, when the phase determination circuit 12 determines that the phase of the system clock FPHD at the end of the wiring is delayed with respect to the phase of the basic frequency-divided clock PH, the selection circuit 14 converts the delay frequency-divided clock PHT into the frequency-divided clock PHS. When the phase determination circuit 12 determines that the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic divided clock PH, the basic divided clock PH is output as the divided clock PHS. .

  Next, the operation of the divided clock generation circuit 1 will be described using the waveform diagram shown in FIG.

  FIG. 6A is a waveform diagram showing an example of the operation of the divided clock generation circuit 1 when the phase of the system clock FPHD at the end of the wiring is delayed with respect to the phase of the basic divided clock PH.

  When the phase of the system clock FPHD at the end of the wiring is delayed with respect to the phase of the basic frequency-divided clock PH, the system clock FPHD at the end of the wiring is output when the both-edge detection signal PLS outputs a pulse waveform at the “H” level. 'H' level. Therefore, a pulse of 'H' level is output to the TRG signal that is the output of the AND gate 122 of the phase determination circuit 12. As a result, the RS flip-flop 123 of the phase determination circuit 12 is set, and the output signal SEL of the RS flip-flop 123 becomes ‘H’.

  When the output signal SEL of the RS flip-flop 123 becomes “H”, the selection circuit 14 selects the delay divided clock PHT and outputs it as the divided clock PHS.

  Here, the delay frequency-divided clock PHT is a signal obtained by synchronizing the basic frequency-divided clock PH with the falling of the system clock FPHD at the end of the wiring and delaying it by time T2. The time T2 is a value equivalent to the delay time T1 from the fall of the system clock FPH to the rise of the basic frequency-divided clock PH.

  As described above, when the phase of the system clock FPHD at the wiring end is delayed with respect to the phase of the basic frequency-divided clock PH, the delay frequency-divided clock PHT that changes after the falling of the system clock FPHD at the wiring end is This is output as a divided clock PHS generated by the divided clock generation circuit 1.

  On the other hand, FIG. 6B is a waveform diagram showing an example of the operation of the frequency-divided clock generation circuit 1 when the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic frequency-divided clock PH.

  When the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic frequency-divided clock PH, the system clock FPHD at the end of the wiring is output when the both-edge detection signal PLS outputs a pulse waveform at the “H” level. 'L' level. For this reason, the TRG signal that is the output of the AND gate 122 of the phase determination circuit 12 is at the ‘L’ level. For this reason, the RS flip-flop 123 of the phase determination circuit 12 remains in the reset state, which is the initial state, and the output signal SEL of the RS flip-flop 123 remains “L”.

  When the output signal SEL of the RS flip-flop 123 is ‘L’, the selection circuit 14 selects the basic frequency-divided clock PHT and outputs it as the frequency-divided clock PHS.

  That is, when the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic frequency-divided clock PH, the basic frequency-divided clock PH that changes in synchronization with the fall of the system clock FPH is generated as the frequency-divided clock. This is output as the divided clock PHS generated by the circuit 1.

  Next, an operation example of the semiconductor integrated circuit on which the divided clock generation circuit 1 of the present embodiment is mounted will be described.

  FIG. 7 is a schematic diagram illustrating an example of the configuration of the semiconductor integrated circuit 100 in which the divided clock generation circuit 1 according to the present embodiment distributes the divided clock PHS to the internal circuit 200.

  The system clock FPH supplied to the semiconductor integrated circuit 100 is distributed to the internal circuit 200 through the clock wiring. At this time, a delay occurs in the system clock FPHD at the end of the wiring due to the influence of the wiring resistance R1 and the load capacitance C1.

  The frequency-divided clock generation circuit 1 receives the system clock FPH and the system clock FPHD at the end of the wiring, and outputs the frequency-divided clock PHS. When the divided clock PHS is also distributed to the internal circuit 200, a delay occurs at the end of the wiring due to the influence of the wiring resistance R2 and the load capacitance C2. This divided clock at the end of the wiring is PHD.

  The system clock FPHD at the wiring end and the frequency-divided clock PHD at the wiring end are input to the AND gate 201 of the internal circuit 200 and become the clock of the flip-flop 202, for example.

  FIG. 8 is a waveform diagram showing how the AND gate 201 outputs the clock signal of the flip-flop 202.

  FIG. 8A shows an example of the operation when the delay time due to the wiring delay of the system clock FPH is small.

  At this time, the phase of the system clock FPHD at the end of the wiring is advanced with respect to the phase of the basic frequency-divided clock PH generated inside the frequency-divided clock generating circuit 1, so that it is output from the frequency-divided clock generating circuit 1. The frequency-divided clock PHS outputs a signal that changes in synchronization with the falling edge of the system clock FPH.

  If the wiring delay of the frequency-divided clock PHS is about the same as the wiring delay of the system clock FPH, the frequency-divided clock PHD at the end of the wiring is a signal whose phase is always delayed with respect to the system clock FPHD at the end of the wiring. Therefore, a glitch is not generated in the output of the AND gate 201, and a normal clock signal is output.

  On the other hand, FIG. 8B is an example showing the operation when the delay time due to the wiring delay of the system clock FPH is large.

  At this time, the phase of the system clock FPHD at the end of the wiring is delayed from the phase of the basic frequency-divided clock PH generated inside the frequency-divided clock generating circuit 1, and therefore output from the frequency-divided clock generating circuit 1. The divided clock PHS outputs a signal that changes in synchronization with the falling edge of the system clock FPHD at the end of the wiring. The frequency-divided clock PHS is further delayed by the wiring delay and becomes the frequency-divided clock PHD at the wiring end. That is, the divided clock PHD at the wiring end is a signal whose phase is always delayed with respect to the system clock FPHD at the wiring end.

  Therefore, also in this case, a normal clock signal is output without causing a glitch in the output of the AND gate 201.

  On the other hand, as shown in FIG. 8C shown as a reference, when the delay time due to the wiring delay of the system clock FPH is large, the frequency-divided clock PHS synchronized with the falling edge of the system clock FPH is generated. Then, a phase reversal phenomenon occurs in which the phase of the divided clock PHD at the wiring end is earlier than the phase of the system clock FPHD at the wiring end, and a glitch occurs in the output of the AND gate 201.

  According to this embodiment, it is possible to prevent the occurrence of a phase inversion phenomenon between the system clock and the divided clock at the end of the clock wiring regardless of the wiring delay of the clock wiring. it can.

The circuit diagram which shows the example of a structure of the frequency-divided clock generation circuit based on the Example of this invention. The circuit diagram which shows the example of a structure of the frequency divider of the Example of this invention. The circuit diagram which shows the example of a structure of the both-edge detection circuit of the Example of this invention. The wave form diagram which shows the example of operation | movement of the both-edge detection circuit of the Example of this invention. The circuit diagram which shows the example of a structure of the synchronous delay circuit of the Example of this invention. The wave form diagram which shows the example of operation | movement of the frequency-divided clock generation circuit which concerns on the Example of this invention. The schematic diagram which shows the example of a structure of the semiconductor integrated circuit in which the frequency-division clock generation circuit based on the Example of this invention is mounted. FIG. 8 is a waveform diagram showing an example of operation of the semiconductor integrated circuit shown in FIG.

Explanation of symbols

1 Divided clock generation circuit 11 Divider 12 Phase determination circuit 13 Synchronous delay circuit 14 Selection circuit 121 Both-edge detection circuits 122 and 1214 AND gate 123 RS flip-flops 111, 112, 114, 117, 119,
131, 132, 133, 135, 137,
1211, 1212, 1213 Inverters 113, 115, 116, 118, 134, 136 Clocked inverter 120, 138 Buffer 1215 NOR gate 1216 OR gate

Claims (5)

A frequency-divided clock generation circuit for distributing a divided clock obtained by dividing a system clock distributed to an internal circuit of a semiconductor integrated circuit to an internal circuit of the semiconductor integrated circuit,
Frequency dividing means for dividing the system clock and outputting it as a basic divided clock;
Phase determining means for determining whether the phase of the system clock at the wiring end for distributing the system clock to the internal circuit is delayed or advanced with respect to the phase of the basic frequency-divided clock;
Synchronous delay means for delaying the basic frequency-divided clock after synchronizing with the system clock at the end of the wiring, and outputting as a delay-divided clock;
Selecting means for selecting the delayed divided clock when the judgment of the phase judging means is a phase delay, selecting the basic divided clock when the judgment is a phase advance, and outputting as a divided clock; A frequency-divided clock generation circuit comprising: The phase determination means is
Both edge detection circuits for detecting rising and falling edges of the basic frequency-divided clock;
An AND gate for calculating a logical product of the outputs of the both edge detection circuits and the system clock at the end of the wiring;
An RS flip-flop having an output of the AND gate as a set input signal and a system reset signal as a reset input signal;
The frequency-divided clock generation circuit according to claim 1, wherein an output of the RS flip-flop is output as the determination signal.   3. The frequency-divided clock generation circuit according to claim 1, wherein the frequency dividing unit includes a frequency-dividing circuit using a master-slave type flip-flop formed by a master latch and a slave latch.   4. The frequency-divided clock generation circuit according to claim 3, wherein a delay of the synchronization delay means is equal to a delay of the slave latch.   5. The frequency-divided clock generation circuit according to claim 4, wherein the synchronization delay means includes a latch having the same configuration as the slave latch.

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