JP2005109955A - Asynchronous communication circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the improvement of communication performance by avoiding the occurrence of a metastable state in a latch circuit in an asynchronous communication circuit required when the transmission/reception of data is executed between semiconductor integrated circuits housing a synchronous circuit mutually operated with different frequencies. <P>SOLUTION: The asynchronous communication circuit has the following constitution. Clocks 3, 4 on the transmission side and the reception side, which are not synchronized with each other, are monitored with a phase comparator 5. When a phase difference between both of the clocks is less than a fixed value, the phase difference is secured by shifting the phase of either of the clocks or data transfer is temporarily stopped. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an asynchronous communication circuit required when data is transmitted and received between circuits operating at different frequencies, and more particularly, asynchronous communication in which a metastable state is avoided in a latch circuit and communication performance is improved. Regarding the circuit.

  One of the problems of the synchronous circuit is a metastable state of a latch circuit that is generated by an asynchronous external input signal called a metastable (see paragraphs (0002) to (0003) of Patent Document 1). This metastable state is a danger zone surrounded by a setup time and a hold time based on the rising edge (or falling edge) of the clock defined in the latch circuit. This metastable state is due to an abnormal operation of the latch circuit that occurs when asynchronous input data changes, and a short pulse called a runt pulse occurs or a slew rate is lost and a steep output waveform cannot be obtained. Cause a malfunction that interrupts the system, such as oscillation, oscillation, and slow output response.

  In order to avoid a malfunction of the circuit due to such a metastable state, a setup time and a hold time for data input with respect to the clock input of the normal latch circuit are defined. Although these restrictions are relieved remarkably by using a flip-flop (that is, a double latch structure) instead of a latch, restrictions on the setup time and the hold time still exist.

  For this reason, when data is transferred using the latch circuit in two systems having different clock frequencies, a waiting time in consideration of the time for metastable is required. For example, in order to reduce the period of metastable, a method of continuously transmitting one transmission data by a plurality of cycles is adopted.

  In particular, when the phase relationship between the two clocks is not guaranteed at all, it is necessary to set the data transfer rate on the transmission side to be about 1/2 to 1/4 lower than the data sampling rate on the reception side. In general, it is difficult to guarantee the phase relationship between the two types of clocks generated by the two independent PLL circuits, and therefore the phase relationship between the two clocks is often not guaranteed at all.

Hereinafter, a conventional asynchronous communication circuit will be described with reference to the block diagram of FIG.
In FIG. 2, 1 is a clock generation circuit for generating a clock signal 3 for data transmission, 2 is a clock generation circuit for generating a clock signal 4 for data reception, and 7 is a clock signal 3 from a flip-flop 7a at the final stage. Data transmission means 8 for outputting data including a synchronization signal and the like as the transmission data signal 6 in synchronization, and data including the synchronization signal and the like from the transmission data signal 6 in synchronization with the clock signal 4 by the first flip-flop 8a The data receiving means 10 for receiving 10 is a received data signal.

  In the circuit configuration as described above, when the clock signals 3 and 4 have a combination of different frequencies, the phase difference between the clock signals 3 and 4 changes every cycle, and the phase difference between the clock signals 3 and 4 has a predetermined value. Since this is not always maintained, a metastable state may occur on the receiving circuit side. For this reason, the lower frequency side of the clock signals 3 and 4 cannot exchange data at a constant cycle rate, and the throughput of data transmission / reception decreases accordingly.

  Next, the operation of the conventional asynchronous circuit having the above configuration will be described with reference to FIG.

  FIG. 4 is a timing chart for explaining the operation of the conventional asynchronous circuit. In FIG. 4, 3 is an operation clock signal on the data transmission side, 4 is an operation clock signal on the data reception side, 6 is a transmission data signal, and 10 is a reception data signal.

  As shown in FIG. 4, since there is no phase difference between the clock signal 3 and the clock signal 4 in the period 404, a metastable state may occur in the data transfer between the two. Therefore, in order to avoid this problem, for example, when transmitting a sequence of three data (d1, d2, d3), two cycles (401 to 402, 403 to 404, 405) are always used to transmit one data. To 406).

As a result, only three data (d1 to d3) can be received during a total of five cycles of the clock signal 4 on the receiving side. That is, in this example, the reception efficiency is about 60%.
JP 2000-261310 A (2nd page, FIG. 6)

  As described above, when data is transferred using a latch circuit in two systems having different clock frequencies, particularly when the phase relationship between the two clocks is not guaranteed at all, the data sampling rate on the receiving side is not affected. Therefore, the data transfer rate on the transmission side needs to be set as low as about 1/2 to 1/4. That is, there is a great restriction on the upper limit of data transfer. Therefore, in order to ensure the same bandwidth as in the case of synchronous communication using a single clock, the bus width is increased or a higher-speed clock is required.

  However, such a method has a drawback that the number of pins of the LSI increases and the cost becomes high, and the clock design becomes difficult.

  The present invention has been made in order to solve the above-described problems. When data is transmitted and received between asynchronous circuits, a metastable state caused by a phase difference between different clocks is always avoided and high. An object of the present invention is to provide an asynchronous communication circuit capable of obtaining communication performance.

  In order to solve the above-mentioned problem, an asynchronous communication circuit according to claim 1 of the present invention includes a first clock generation means for generating a first clock signal and a second clock for generating a second clock signal. Data receiving means for receiving transmission data output by the data transmission means in synchronization with the generation means, data transmission means for outputting transmission data in synchronization with the first clock signal, and data transmission means Means for comparing the phase of the first clock signal and the phase of the second clock signal, and when the phase difference is less than a predetermined value, the phase difference is greater than or equal to a predetermined value. And a phase comparison means for outputting a control signal for shifting the phase of the clock signal to the first clock generation means.

  According to a second aspect of the present invention, there is provided an asynchronous communication circuit comprising: a first clock generating unit that generates a first clock signal; a second clock generating unit that generates a second clock signal; Data transmitting means for outputting transmission data in synchronization with the first clock signal, data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal, and the first The phase of the second clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the phase of the second clock signal is set so that the phase difference is greater than or equal to the predetermined value. And a phase comparison means for outputting a control signal for shifting to the second clock generation means.

  According to a third aspect of the present invention, there is provided an asynchronous communication circuit comprising: a first clock generating unit that generates a first clock signal; a second clock generating unit that generates a second clock signal; Data transmitting means for outputting transmission data in synchronization with the first clock signal, data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal, and the first When the phase difference between the clock signal and the second clock signal is less than a predetermined value, a control signal is output to the data transmission means to temporarily stop data transmission. Phase comparison means.

  According to a fourth aspect of the present invention, there is provided an asynchronous communication circuit comprising: a first clock generating unit that generates a first clock signal; a second clock generating unit that generates a second clock signal; Data transmitting means for outputting transmission data in synchronization with the first clock signal, data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal, and the first The phase of the clock signal of the second clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the first clock signal or the second clock signal is temporarily stopped. Phase comparison means for outputting a control signal to the first clock generation means or the second clock generation means.

  According to a fifth aspect of the present invention, the asynchronous communication circuit includes a first clock generation unit that generates a first clock signal, a second clock generation unit that generates a second clock signal, and the first clock generation unit. Data transmitting means for outputting transmission data in synchronization with the first clock signal, data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal, and the first A control signal indicating that the same transmission data is continuously output for two cycles when the phase difference is less than a predetermined value, and the phase of the second clock signal is compared with the phase of the second clock signal. And a phase comparison means for outputting the signal.

  According to a sixth aspect of the present invention, there is provided an asynchronous communication circuit comprising a first clock generating means for generating a first clock signal, a second clock signal, and a clock obtained by delaying the second clock signal. Second clock generation means for generating a signal, data transmission means for outputting transmission data in synchronization with the first clock signal, the second clock signal, and the second clock signal are delayed In synchronization with the clock signal, the data receiving means for receiving the transmission data output by the data transmitting means, the phase of the first clock signal and the phase of the second clock signal are compared, and the phase difference Is equal to or greater than a predetermined value, a control signal for selecting data received in synchronization with the second clock signal as reception data is output to the data receiving means, and the phase difference is predetermined. Phase comparison means for outputting to the data receiving means a control signal for selecting, as received data, data received in synchronization with the clock signal obtained by delaying the second clock signal when the value is less than the value; It is a thing.

  The asynchronous communication circuit according to claim 7 of the present invention is the asynchronous communication circuit according to claim 1 or 2, wherein the first or second clock generation means delays the clock signal. A circuit, and a selector that selects either the clock signal or the clock signal delayed by the delay circuit in accordance with the control signal.

  According to the asynchronous communication circuit of the first aspect of the present invention, the first clock generating means for generating the first clock signal, the second clock generating means for generating the second clock signal, and the first A data transmission means for outputting transmission data in synchronization with the clock signal, a data reception means for receiving transmission data output by the data transmission means in synchronization with the second clock signal, and the first Comparing the phase of the clock signal with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the phase of the first clock signal is shifted so that the phase difference is equal to or greater than the predetermined value. And a phase comparison means for outputting a control signal to the first clock generation means, so that the phase between the two clocks does not always approach a certain value or less. It is possible to avoid the table state, the data can be transferred per clock cycle of the lower frequency of the two clocks.

  According to the asynchronous communication circuit of the second aspect of the present invention, the first clock generation means for generating the first clock signal, the second clock generation means for generating the second clock signal, and the first A data transmission means for outputting transmission data in synchronization with the clock signal, a data reception means for receiving transmission data output by the data transmission means in synchronization with the second clock signal, and the first Comparing the phase of the clock signal with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the phase of the second clock signal is shifted so that the phase difference is greater than or equal to the predetermined value. And a phase comparison unit that outputs a control signal to the second clock generation unit, so that the phase between the two clocks does not always approach a certain value or less. It is possible to avoid the table state, the data can be transferred per clock cycle of the lower frequency of the two clocks.

  According to the asynchronous communication circuit of a third aspect of the present invention, the first clock generation means for generating the first clock signal, the second clock generation means for generating the second clock signal, and the first A data transmission means for outputting transmission data in synchronization with the clock signal, a data reception means for receiving transmission data output by the data transmission means in synchronization with the second clock signal, and the first The phase of the clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, a control signal is output to the data transmission means to temporarily stop data transmission. Since the phase comparison means is provided, it is possible to always stop data transmission for cycles that may be in a metastable state on the receiving side. Data can be transferred at the lower substantially each cycle of the clock.

  According to the asynchronous communication circuit of a fourth aspect of the present invention, the first clock generation means for generating the first clock signal, the second clock generation means for generating the second clock signal, and the first A data transmission means for outputting transmission data in synchronization with the clock signal, a data reception means for receiving transmission data output by the data transmission means in synchronization with the second clock signal, and the first Control that the phase of the clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the first clock signal or the second clock signal is temporarily stopped Since the phase comparison means for outputting the signal to the first clock generation means or the second clock generation means is provided, there is a possibility of a metastable state on the receiving side. Cycle temporarily be become always possible to stop the data transmission and reception only, it is possible to transfer data at substantially each cycle of the clock of the lower frequency of the two clocks.

  According to the asynchronous communication circuit of the fifth aspect of the present invention, the first clock generating means for generating the first clock signal, the second clock generating means for generating the second clock signal, and the first A data transmission means for outputting transmission data in synchronization with the clock signal, a data reception means for receiving transmission data output by the data transmission means in synchronization with the second clock signal, and the first When the phase of the clock signal is compared with the phase of the second clock signal and the phase difference is less than a predetermined value, a control signal is output to the data transmission means to output the same transmission data continuously for two cycles. Output phase comparison means, so that the meta data is not changed in a cycle that may be in a metastable state on the receiving side. You can always avoid data transmission and reception with the possibility of table and makes it possible to transfer data at substantially every cycle of the clock of the lower frequency of the two clocks.

  According to the asynchronous communication circuit of the sixth aspect of the present invention, the first clock generation means for generating the first clock signal, the second clock signal, and the clock signal obtained by delaying the second clock signal A second clock generation means for generating data, a data transmission means for outputting transmission data in synchronization with the first clock signal, a clock obtained by delaying the second clock signal and the second clock signal In synchronization with the signal, the data receiving means for receiving the transmission data output by the data transmitting means, the phase of the first clock signal and the phase of the second clock signal are compared, and the phase difference is When the value is equal to or greater than a predetermined value, a control signal for selecting data received in synchronization with the second clock signal as reception data is output to the data receiving means, and the phase difference is predetermined. A phase comparison means for outputting a control signal to the data receiving means to select data received in synchronization with the clock signal obtained by delaying the second clock signal as reception data when the value is less than the value; As a result, it is possible to always select data that is unlikely to be in a metastable state on the receiving side, and data can be transferred in almost every cycle of the clock with the lower frequency of both clocks. .

  According to an asynchronous communication circuit according to claim 7 of the present invention, in the asynchronous communication circuit according to claim 1 or 2, the first or second clock generation means delays a clock signal. And a selector that selects either the clock signal or the clock signal delayed by the delay circuit in accordance with the control signal, so that the clock phase relationship that may result in a metastable state is provided. It is possible to provide a means for shifting the required clock phase to eliminate.

(Embodiment 1)
Hereinafter, an asynchronous communication circuit according to Embodiment 1 of the present invention will be described with reference to FIG.
FIG. 1 is a diagram showing a configuration of an asynchronous communication circuit according to the first embodiment.

  In FIG. 1, a clock generation circuit (first clock generation means) 1 generates a data transmission clock signal 3 which is a first clock signal, and is based on a control signal 9 of a phase comparator 5. The clock signal 31 (see FIG. 3) serving as a reference and the clock signal 32 (see FIG. 3) obtained by shifting the phase of the clock signal 31 are selectively output. A clock generation circuit (second clock generation means) 2 generates a data reception clock signal 4 which is a second clock signal.

  The data transmission means 7 synchronizes the data (including the synchronization signal and the like) with the clock signal 3 and outputs it as the transmission data signal 6 by the flip-flop 7a at the final stage.

  The data reception means 8 receives data (including a synchronization signal) from the transmission data signal 6 in synchronization with the clock signal 4 by the flip-flop 8a of the first stage, and obtains the reception data signal 10.

  The phase comparator (phase comparison means) 5 has a function of detecting the phase difference between the synchronous clock signal 3 (= clock signal 31) on the transmission side and the reception side and the operation clock signal 4, and the phase difference is a predetermined value When the value is less than the value, the control signal 9 is output so as to shift the phase of the clock signal 31 to control the clock generation circuit 1. The predetermined value is a value determined experimentally to avoid a metastable state (metastable state) of the latch circuit, and may be determined including a margin.

Next, the clock generation circuit 1 that generates the clock signal 3 for data transmission in the asynchronous communication circuit according to the first embodiment will be described with reference to FIG.
FIG. 5 is a diagram showing a configuration example of the clock generation circuit 1.

  As shown in FIG. 5, the clock signal 31 generated by the oscillation circuit 54 is connected to one input of the selector 55 and also input to the delay circuit 51, and the clock signal 32 delayed by the delay circuit 51 is obtained. The other input of the selector 55 is connected. The control signal 9 controls the selector 55 to select one of the clock signal 31 and the clock signal 32 and outputs it to the clock terminal 3.

  With the above configuration, based on the control signal 9, the original clock signal 31 generated by the oscillation circuit 54 and the delay clock 32 obtained by delaying the clock signal 31 can be selectively output. It is possible to shift the clock phase necessary to eliminate the clock phase relationship that may result in a table state.

Next, the operation of the asynchronous communication circuit according to the first embodiment will be described with reference to FIG.
FIG. 3 is a timing chart for explaining the operation of the asynchronous communication circuit according to the first embodiment. In FIG. 3, 3 is an operation clock signal on the data transmission side, 4 is an operation clock signal on the data reception side, 6 is a transmission data signal, 9 is a control signal based on the phase comparison result, 10 is a reception data signal, and 31 is a transmission side. The reference clock signal 32 is a clock signal obtained by delaying the clock signal 31. In periods 301 to 303, the phase difference between the rising edges of the clock signal 4 and the clock signal 31 is a predetermined value or more. In the period 304, the phase difference between the rising edges of the clock signal 4 and the clock signal 31 is a predetermined value. The case where it is less than is shown.

  As shown in FIG. 3, in the period 301 to 303, when the phase difference between the rising edge of the clock signal 31 on the transmission side and the rising edge of the operation clock signal 4 on the reception side is a predetermined value or more, The phase comparator 5 outputs a control signal indicating that the clock signal 31 is used as it is as the transmission clock 3, and transmits and receives data without delaying the transmission clock.

  On the other hand, when the phase difference between the rising edge of the clock signal 31 on the transmission side and the rising edge of the operation clock signal 4 on the reception side is less than a predetermined value in the period 304, the phase comparator 5 A control signal indicating that the clock signal 32 obtained by delaying the signal 31 is used is output. In the period 304, the phase of the clock signal 3 is shifted by the control signal 9 so that the phase difference between the clock signal 4 and the clock signal 4 becomes a predetermined value or more. Will be.

  As a result, the clock generation circuit 1 outputs the clock signal indicated by the clock signal 3 as the operation clock signal on the transmission side.

  When data is transmitted / received using the clock signal 3 and the clock signal 4 generated in this way, data can be transmitted / received for each cycle of the reception side clock having a low frequency. As shown, five data d1 to d5 can be received during a total of five cycles of the clock signal 4 on the receiving side. Therefore, in the example shown in FIG. 3, the reception efficiency is 100%.

  Thus, in the asynchronous communication circuit according to the first embodiment, the phase of the transmission clock signal is compared with the phase of the reception clock signal, and when the phase difference is less than a predetermined value, a control signal is sent to the transmission clock generation means. A phase comparator for outputting and a transmission clock for generating a transmission clock signal and for shifting a phase of the transmission clock signal so that the phase difference becomes a predetermined value or more based on a control signal of the phase comparison unit Since the generation means is provided, when transmitting and receiving data, the phase difference between the transmission side clock and the reception side clock can always be kept at a predetermined value or more. As a result, the metastable state of the synchronization circuit can be avoided, and data transmission / reception can be performed at each cycle of the clock with the lower frequency of both clocks. Can be improved.

  In the first embodiment of the present invention, as shown in FIG. 3, the phase comparator 5 compares the clock 31 with the clock 4, and the phase difference between the clock signal 31 and the clock signal 4 is less than a certain value. The clock signal 3 is switched and output from the clock signal 31 to the clock signal 32 only for the cycle of the above, but in a combination in which a cycle in which the phase difference between the two is less than a certain value occurs continuously a plurality of times Therefore, phase comparison control becomes difficult. Therefore, in such a case, after the phase difference between the clock signal 31 and the clock signal 4 becomes less than a certain value, the phase-shifted clock signal 32 is continuously output as the clock signal 3. Alternatively, after switching to the clock signal 32, the phase comparator 5 may compare the clock signal 32 and the clock 4. However, it is necessary to adjust the phase of the clock 32 after the phase shift so that it matches the phase of the clock 31.

  In the first embodiment, the clock generation circuit 1 has the configuration shown in FIG. 5 and shifts the phase of the clock on the transmission side. However, the clock generation circuit 2 has the configuration shown in FIG. As shown in FIG. 6, the control signal 9 from the phase comparator 5 may be input to the clock generation circuit 2 to shift the phase of the receiving clock, The same effect as the configuration of FIG. 1 can be obtained.

  In the first embodiment, the clock oscillation circuit 54 is built in the clock generation circuit 1. However, the same effect can be obtained even when a clock signal is input from the outside instead of the output of the oscillation circuit 54. It is done.

  In addition, as the method of clock phase shift, the original clock signal 31 and the delayed clock signal 32 are selected using the selector 55 based on the control signal 9, but the original clock input terminal and output terminal are selected. An AND gate may be interposed instead of the selector, and the rising edge of the clock may be shifted by controlling the AND gate for a necessary period based on the control signal 9 and fixing the rising edge of the clock to Lo. good.

  In addition, when the phase comparator 5 detects that the phase difference between the clock 3 and the clock 4 is less than a certain value, the control signal 9 is used instead of shifting the phase of the clock signal on the transmission side or the clock signal on the reception side. In addition, as shown in FIG. 9, the phase comparator 5 temporarily stops the clock signal on the transmission side or the reception side by the control signal 92, thereby avoiding data transmission in a cycle in which a metastable state may occur. It is also good.

  Further, as in the first embodiment, instead of shifting the phase of the clock signal on the transmission side or the clock signal on the reception side by the control signal 9, the phase comparator 5 controls as shown in FIGS. Even if the data transmission means 7 and the data reception means 8 are instructed to temporarily stop transmission / reception of data by the signals 90 and 91, respectively, data transmission / reception in a cycle in which a metastable state can occur can be avoided. Since data transmission / reception can be performed in almost every cycle of a low-frequency clock, the data transmission / reception throughput can be increased and the performance of the communication circuit can be improved.

  Similarly, instead of shifting the phase of the transmission side clock signal or the reception side clock signal by the control signal 9, the phase comparator 5 sends the data signal to the transmission side clock by the control signal 93 as shown in FIG. Even when the data transmission means 7 is instructed to output the signal continuously for two cycles, it is possible to prevent a change in data in the vicinity of the rising edge of the clock 4, so that the occurrence of a metastable state can be avoided. Since data transmission / reception can be performed in almost every cycle of a low-frequency clock, the data transmission / reception throughput can be increased and the performance of the communication circuit can be improved.

  Similarly, instead of shifting the phase of the clock signal on the transmission side or the clock signal on the reception side by the control signal 9, the reception side uses the clock 4 and the clock 4a obtained by delaying the clock 4 in advance as shown in FIG. At each timing, the transmission data 6 is once latched by the flip-flops 8a and 8b, and the metastable state is generated by selecting one of the latched signals by the selector 8c switched by the control signal 94. You may select the data that is not.

  That is, the clock generation circuit 2 generates a clock signal and a clock signal obtained by delaying the clock signal, and the data receiving unit 8 receives transmission data in synchronization with the clock signal and the clock signal obtained by delaying the clock signal. When the phase comparator 5 controls the data receiving means 8 and the phase difference between the phase of the first clock signal and the phase of the second clock signal is greater than or equal to a predetermined value The data received in synchronization with the second clock signal is selected as reception data, and when the phase difference is less than a predetermined value, the data is received in synchronization with the clock signal obtained by delaying the second clock signal. By selecting the data to be received as received data, it is possible to select data for which no metastable state has occurred. Because data can be transmitted and received in substantially every cycle, increasing the throughput of data transmission and reception, thereby improving the performance of the communication circuit.

  As described above, the asynchronous communication circuit according to the present invention avoids a metastable state caused by a phase difference between both clocks when data is transmitted and received between circuits having different clock frequencies, and has a high data transfer throughput. It is useful as an asynchronous communication circuit that needs to improve communication performance.

It is a figure which shows one structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the structure of the conventional asynchronous communication circuit. It is a figure which shows the timing chart explaining operation | movement of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the timing chart explaining the operation | movement of the conventional asynchronous communication circuit. It is a figure which shows one structural example of the clock generation circuit in the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the other structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the further another structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the further another structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the further another structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the further another structural example of the asynchronous communication circuit by Embodiment 1 of this invention. It is a figure which shows the further another structural example of the asynchronous communication circuit by Embodiment 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Clock generation circuit for data transmission 2 Clock generation circuit for data reception 3 Operation clock signal on data transmission side 4 Operation clock signal on data reception side 5 Phase comparator 6 Transmission data signal 7 Data transmission means 8 Data reception means 9, 90 to 94 Control signal based on phase comparison result 10 Received data signal d1 to d5 Transmitted and received data 31 Clock signal that is the source of transmission clock 3 32 Signal delayed from clock signal 31 54 Oscillator 51 Delay circuit 55 selector

Claims (7)

First clock generating means for generating a first clock signal;
Second clock generating means for generating a second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal;
The phase of the first clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the first clock signal is set so that the phase difference is equal to or greater than a predetermined value. Phase comparison means for outputting to the first clock generation means a control signal for shifting the phase of
An asynchronous communication circuit characterized by that. First clock generating means for generating a first clock signal;
Second clock generating means for generating a second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal;
The phase of the first clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, the second clock signal is set so that the phase difference is equal to or greater than a predetermined value. Phase comparison means for outputting a control signal for shifting the phase to the second clock generation means,
An asynchronous communication circuit characterized by that. First clock generating means for generating a first clock signal;
Second clock generating means for generating a second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal;
The phase of the first clock signal is compared with the phase of the second clock signal, and when the phase difference is less than a predetermined value, a control signal for temporarily interrupting data transmission is sent to the data transmission Phase comparison means for outputting to the means,
An asynchronous communication circuit characterized by that. First clock generating means for generating a first clock signal;
Second clock generating means for generating a second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal;
The phase of the first clock signal and the phase of the second clock signal are compared, and when the phase difference is less than a predetermined value, the first clock signal or the second clock signal is temporarily A phase comparison means for outputting a control signal for stopping to the first clock generation means or the second clock generation means,
An asynchronous communication circuit characterized by that. First clock generating means for generating a first clock signal;
Second clock generating means for generating a second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal;
The phase of the first clock signal and the phase of the second clock signal are compared, and when the phase difference is less than a predetermined value, a control signal for outputting the same transmission data continuously for two cycles is output. A phase comparison means for outputting to the data transmission means,
An asynchronous communication circuit characterized by that. First clock generating means for generating a first clock signal;
Second clock generation means for generating a second clock signal and a clock signal obtained by delaying the second clock signal;
Data transmission means for outputting transmission data in synchronization with the first clock signal;
Data receiving means for receiving transmission data output by the data transmitting means in synchronization with the second clock signal and a clock signal obtained by delaying the second clock signal;
The phase of the first clock signal is compared with the phase of the second clock signal, and when the phase difference is equal to or greater than a predetermined value, data received in synchronization with the second clock signal is received. A control signal for selection as data is output to the data receiving means, and when the phase difference is less than a predetermined value, the data received in synchronization with the clock signal obtained by delaying the second clock signal An asynchronous communication circuit, comprising: phase comparison means for outputting a control signal for selection as reception data to the data reception means. In the asynchronous communication circuit according to claim 1 or 2,
The first or second clock generation means includes:
A delay circuit for delaying the clock signal;
An asynchronous communication circuit comprising: a selector that selects either the clock signal or the clock signal delayed by the delay circuit in accordance with the control signal.

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