JP2007248103A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a PLL circuit for easily generating a PLL clock signal having an arbitrary number of clocks with a logic circuit. <P>SOLUTION: A PLL control signal is input into a flip-flop 7 and is latched in rising a reference clock, thereby generating a PLL clock signal 1 synchronized with the reference clock. Further, the PLL control signal 1 is input into a flip-flop 8 and is latched in rising a dividing signal A, thereby generating a synchronous control signal synchronized with a VCO signal. The synchronous control signal, an arbitrary signal B output from a frequency divider 6, and the VCO signal are input into a PLL clock signal generating signal 9, and a PLL clock signal of a desired clock number can be obtained easily. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a PLL circuit for testing at an actual operation speed.

  Conventionally, with the recent increase in LSI speed and integration, defective products cannot be rejected with a low-speed DC-SCAN pattern. Therefore, the LSI is tested at a speed equivalent to the operating speed for actual use (hereinafter referred to as the LSI). , Called "actual speed test"). That is, at the LSI manufacturing stage, for some reason, the signal propagation speed of a part of the internal circuit becomes slow, and even if it operates logically, it may not operate at the actual speed. Therefore, such a defective product cannot be rejected only by the test using the low-speed DC-SCAN pattern. Therefore, verification by the actual speed test is required.

  However, if all the tests are performed in the actual speed test, an expensive high-speed LSI tester is used, resulting in an increase in manufacturing cost of a semiconductor integrated circuit (hereinafter referred to as “LSI”).

  Therefore, as a technology related to a conventional test circuit and a test method for performing an actual speed test using an LSI tester that operates at a low speed and capable of removing the above defective products without causing an increase in manufacturing cost. For example, it is disclosed by patent document 1 (Unexamined-Japanese-Patent No. 2002-196046).

  In this prior art, first, the internal state of the LSI is set at a low speed by a low-speed external clock signal B (details will be described later), and then compared with the external clock B generated inside the tester. Is switched to a high-speed basic clock ("PLL clock signal A" which will be described later), and the LSI is operated at a speed used in normal use. Then, it returns to the external clock B again and verifies whether the LSI operates normally at a low speed.

  As a result, it is possible to intensively verify a particularly severe part in the LSI chip.

  First, the system configuration of a conventional LSI test circuit will be described below with reference to FIG.

  FIG. 3 is a system block diagram showing a schematic configuration of a conventional LSI test circuit system.

  As shown in FIG. 3, the conventional LSI test circuit includes an LSI 21 to be tested, an LSI tester 26, a PLL control unit 27, an external clock supply unit 28, and a clock switching signal control controlled by the LSI tester 26. And means 29.

  The LSI 21 includes an internal circuit 22, a PLL circuit 23, and a switching circuit 25 as internal configurations.

  In the LSI tester configured as described above, and in the LSI 21, the PLL circuit 23 includes a PLL control signal 24 output from the LSI tester 26 via the PLL control means 27, and a reference clock output from the outside of the LSI 21. Based on the above, a PLL clock signal A is generated and supplied to the switching circuit 25 of the LSI 21.

  The PLL control signal 24 is a control signal for designating a time domain range in which the LSI 21 performs an actual speed operation, as shown in FIG. 4 to be described later. In order to verify at an actual speed within the active period of the control signal. PLL clock signals A having the number of clocks necessary for the above are generated.

  On the other hand, the low-speed external clock signal B is supplied from the LSI tester 26 to the switching circuit 25 of the LSI 21 via an external clock signal input terminal (not shown) provided in the LSI 21.

  Then, either the PLL output signal A or the external clock signal B is selected by the switching circuit 25 based on the clock switching control signal output from the LSI tester 26 and supplied to the internal circuit 22. The

  In the time domain in which the external clock signal B is selected, the LSI 21 is subjected to the initial state setting of the registers and the verification of the operation result by the actual speed operation. The time domain in which the PLL clock signal A is selected is a time domain in which the LSI 21 operates at the actual speed.

  In this way, low speed initial value setting → real speed operation → low speed result reading is automatically performed, and the result of the real speed operation is verified at a low speed.

  Next, the operation of the LSI 21 in the conventional LSI test circuit system configured as described above will be described in detail with reference to FIGS.

  FIG. 4 is an example of a timing chart showing the operation of the above-described conventional test circuit system.

  First, the clock switching control signal is “L” (see FIG. 4), the switching circuit 25 selects the external clock signal B, and the initial state setting of the LSI 21 is performed. The PLL control signal from the PLL control means 27 is “L”. Thereby, the PLL 23 is in a disabled state, and no PLL clock signal A is generated. In the initial state setting state of the LSI 21, the internal circuit 22 of the LSI chip is set to a desired initial state by the external clock signal B and the data signal from the LSI tester 28.

  Next, the actual speed operation is performed. In the actual speed test, the clock switching control signal becomes “H” (see FIG. 4), and the switching circuit 25 selects the PLL clock A and supplies it to the internal circuit 22 of the LSI 21. Here, the PLL control signal from the PLL control means 27 also becomes “H”, the PLL circuit 23 becomes active, generates the PLL clock A for the desired number of clocks, and the LSI 21 operates at the actual speed.

  Finally, the PLL control signal 24 becomes low level again, the switching circuit 25 selects the external clock signal B supplied from the LSI tester 26, and the internal result of the LSI 21 is investigated.

  As described above, when the PLL control signal is in the active state, the PLL circuit 23 generates a PLL clock signal having a desired number of clocks. This generation operation will be described with reference to FIG.

  FIG. 5 is a timing chart showing the operation of generating a PLL clock signal by the PLL circuit 23.

  Since the PLL control signal 24 is input from an external LSI tester 26, it is generally an asynchronous signal for the PLL circuit 23. Therefore, the VCO output signal that is the PLL original output signal that is the original output of the PLL 23 and the PLL control signal 24 are in an asynchronous relationship.

Therefore, a counter (not shown) is provided in the PLL circuit 23 in order to output a PLL clock signal having a desired number of clocks and a VCO output signal and a PLL control signal. This counter counts the VCO output signal only when the PLL control signal 24 is at a high level. Then, a pulse control circuit (not shown) generates a pulse control output signal that outputs a high level only when the count value counted by the counter is within a certain count range. As a result, the PLL clock output signal having the desired number of clocks is output. As a result, it is possible to supply the LSI 21 with a desired number of actual speed clocks from the PLL circuit 23.
JP 2002-196046 A

  However, in the conventional LSI test circuit that performs the actual speed test, the PLL control signal and the VCO output signal are asynchronous, so that a logic circuit (for example, AND logic operation) of the VCO output signal and the PLL control signal is simply used. Thus, a PLL clock signal having a desired number of clocks cannot be generated, and a counter circuit including a counter is required in the PLL circuit. If the desired number of clocks is two clocks as in the above example, the bit length of the counter is several bits, and there is no problem in terms of the bit length of the counter, but the period of operation at the actual speed is several clocks. Is not limited.

  That is, the conventional test circuit has a problem that the period of operation at the actual speed depends on the bit length of the counter.

  Further, since the counter circuit needs to generate a PLL clock signal having an arbitrary number of clocks from the counter value, there is a problem that the peripheral circuit scale for setting the start point of the count value, the clock width, and the like becomes large.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of easily generating a PLL clock signal having an arbitrary number of clocks by a logic circuit.

  In order to solve the above problems, a semiconductor integrated circuit according to the present invention has the following features.

  A semiconductor integrated circuit according to the present invention includes a PLL circuit that inputs a reference clock from the outside and generates a clock for generating a clock for performing an actual speed operation, and a divided clock obtained by dividing the master clock; A semiconductor integrated circuit comprising: an external clock that is slower than the master clock; and a switching circuit that switches between the master clock and a clock that performs a low-speed operation and a high-speed operation using an external switching control signal. Is a latch circuit that receives an external control signal for determining the generation time width of the master clock and latches it with the divided clock, the output signal of the latch circuit, the master clock, and the divided clock And a generation circuit for generating a clock for performing the actual speed operation having an arbitrary number of clocks. And butterflies.

  In the semiconductor integrated circuit according to the present invention, the generation circuit is a logic circuit that performs a logical operation.

  Further, in the semiconductor integrated circuit according to the present invention, when the control signal from the outside for determining the generation time width of the master clock is asynchronous with the reference clock, the PLL circuit further includes the control signal. A latch circuit for inputting a signal and latching with the reference clock is provided, and an output signal of the latch circuit in which the control signal and the reference signal are synchronized is used as a control signal again.

  The semiconductor integrated circuit according to the present invention is characterized in that a lock detect signal indicating a lock state output from the PLL circuit is output to the outside to determine whether or not the test can be performed. .

  As described above, according to the semiconductor integrated circuit of the present invention, the control signal synchronized with the VCO output signal that is the output signal of the PLL circuit can be generated from the PLL control signal. It is possible to generate a PLL clock signal by masking the VCO output signal for a desired period, and to perform an LSI test at an actual speed by an inexpensive LSI tester.

  In addition, since a PLL clock signal having various numbers of clocks of the PLL clock signal can be generated, the actual speed test period is not limited and various test patterns can be created. This leads to an increase in the failure detection rate of the LSI, and as a result, the market failure rate can be lowered, and the cost when a market defective product appears can be suppressed in advance.

  Further, according to the semiconductor integrated circuit of the present invention, it is possible to externally determine whether or not the test is possible by causing the tester to output a lock detect signal indicating the locked state of the PLL circuit.

  Hereinafter, an embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the accompanying drawings.

  The configuration of the semiconductor integrated circuit according to the present invention is basically the same as the semiconductor integrated circuit 21 in the system block diagram of the conventional LSI test circuit system, except for the PLL circuit 23 of the semiconductor integrated circuit 21 shown in FIG. The configuration of the test circuit system including the LSI tester 26 that performs the operation test of the semiconductor integrated circuit 21 is basically the same.

  Therefore, the basic concept of the test operation of the LSI test circuit system that performs the actual speed test (high-speed test) using the low-speed LSI tester 26 and the basic operation of the semiconductor integrated circuit 21 are omitted.

  First, the configuration of the PLL circuit 10 which is a characteristic part of the semiconductor integrated circuit according to the present invention will be described.

  FIG. 1 is a block diagram showing a configuration of a PLL circuit of a semiconductor integrated circuit according to the present invention.

  As shown in FIG. 1, a PLL circuit 10 includes a PLL circuit body 1, a flip-flop circuit 7 that latches a PLL control signal supplied from the outside with a reference clock, and a PLL control signal 1 that is an output of the flip-flop circuit 7. From the flip-flop circuit 8 at the falling edge of the frequency-divided signal A, the synchronization control signal output from the flip-flop circuit 8, the frequency-divided signal B output from the PLL circuit body 1, the VCO output signal, etc. And a PLL clock signal generation circuit 9 for generating

  The PLL circuit body 1 includes a phase comparator 2 that compares the phases of the reference clock and the frequency-divided signal that is the output of the frequency divider 6, and a pull-in current or a sweep-out current based on the comparison result of the phase comparator 2. A charge pump circuit 3 that generates AC, a loop filter (hereinafter referred to as “LPF”) 4 that cuts AC components, a voltage control oscillator (hereinafter referred to as “VCO”) 5, and a VCO 5 that matches the frequency of the reference clock. And a frequency divider 6 for frequency-dividing the output of.

  In the PLL circuit 10 configured as described above, the VCO output signal that is the output of the VCO 5 is supplied to the frequency divider 6, output from the PLL circuit 1, and also supplied to the PLL clock signal generation circuit 9.

  As described above, the frequency-divided signal A of the frequency divider 6 is input to the phase comparator 2 and output from the PLL circuit 1 and becomes a latch signal of the flip-flop 8. The output of the flip-flop circuit 8 is supplied to the PLL clock signal generation circuit 9 as a synchronization control signal.

  A PLL clock signal that is an output signal of the PLL clock signal generation circuit 9 is supplied to the switching circuit 25 of the LSI 21.

  Further, the phase comparator 2 outputs a lock detect signal (hereinafter referred to as “LD signal”) indicating whether or not the PLL circuit 1 is locked. The LSI tester 26 receives this LD signal, can monitor the lock state of the PLL circuit 10, and can also be used as a test start condition.

  Next, the operation of the PLL circuit 10 will be described using the time chart shown in FIG.

  FIG. 2 is a time chart showing the operation of the PLL circuit 10 in the semiconductor integrated circuit according to the present invention.

  FIG. 2 shows an operation when a sufficient time has elapsed since the PLL circuit 1 is in a locked state. Although not shown, the LD signal is in an active state (here, active state = logic level “High”). And).

  At this time, as described above, the PLL control signal output from the LSI tester 26 is asynchronous with the reference clock.

  Further, the phase relationship between the divided signal A obtained by dividing the VCO output signal and the phase of the reference clock is not constant due to the jitter of the PLL loop system as shown in FIG. That is, the reference clock A may be earlier or later than the frequency-divided signal A, and is not completely synchronized. Of course, the VCO output signal is not completely synchronized.

  Under the above situation, it is necessary to provide a complicated counter circuit as in the prior art from the PLL control signal, and it is difficult to generate a PLL clock signal having a desired number of clocks used at the time of testing by a simple logic circuit. ing.

  However, since the frequency of the reference clock is generally low and the period is relatively long, the edge of the frequency-divided signal A does not deviate significantly from the reference clock if the PLL main body 1 holds the locked state. . Using this property, the PLL control signal 1 supplied from the LSI tester 26 is once input to the flip-flop 7 and latched at the rising edge of the reference clock, thereby generating the PLL control signal 1 synchronized with the reference clock. Further, the PLL control signal 1 is input to the flip-flop 8 and latched at the falling edge of the divided signal A, thereby generating a synchronous control signal synchronized with the VCO signal. As shown in FIG. 2, this synchronization control signal, an arbitrary divided signal B output from the frequency divider 6, and the VCO signal are input to the PLL clock signal generation signal 9, and the desired number of clocks can be easily obtained. Can be obtained (in FIG. 2, a PLL clock signal of 4 clocks is generated).

  Therefore, if this synchronization control signal is used, the VCO signal, which is the basic clock of the LSI, can be easily masked for a desired period, and the actual speed test can be performed using the PLL clock signal generated by the masking. become.

  In the description of the operation of the embodiment of the present invention, as the operation of the phase comparator 2, the phase of the input reference clock and the rising edge of the divided signal A is compared. If the phase comparator 2 compares the falling edge of the input signal, the flip-flop 8 that creates the synchronization control signal latches at the rising edge of the divided signal.

  It should be noted that the semiconductor integrated circuit according to the present invention is not limited to the above-described embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the PLL circuit in the semiconductor integrated circuit which concerns on this invention. 3 is a time chart showing the operation of the PLL circuit 10 in the semiconductor integrated circuit according to the present invention. It is a block diagram which shows the conventional test system structure. It is a timing diagram which shows the operation | movement in the conventional test system. 7 is a timing chart showing an operation of generating a PLL clock signal by a conventional PLL circuit 23.

Explanation of symbols

1 PLL circuit body 2 Phase comparator 3 Charge pump circuit 4 LPF
5 VCO
6 frequency divider 7 flip-flop 8 flip-flop 9 PLL output signal generation circuit 10 PLL circuit 21 semiconductor integrated circuit 22 internal circuit 23 PLL circuit 24 PLL control signal 25 switching circuit 26 LSI tester 27 PLL control means 28 external clock supply means 29 clock Switching control means

Claims (4)

A master circuit that inputs a reference clock from outside and generates a clock for performing an actual speed operation, a PLL circuit that generates a divided clock obtained by dividing the master clock, and an external clock that is slower than the master clock And a switching circuit that switches between the master clock and a clock that performs a high-speed operation and a low-speed operation by an external switching control signal,
The PLL circuit receives an external control signal for determining the generation time width of the master clock, and latches with the divided clock;
A generation circuit for generating a clock for performing the actual speed operation having an arbitrary number of clocks from an output signal of the latch circuit, the master clock, and the divided clock;
A semiconductor integrated circuit comprising:   The semiconductor integrated circuit according to claim 1, wherein the generation circuit is a logic circuit that performs a logical operation.   When the control signal from the outside for determining the generation time width of the master clock is asynchronous with the reference clock, the PLL circuit further inputs the control signal and latches with the reference clock 3. The semiconductor integrated circuit according to claim 1, further comprising a latch circuit, wherein an output signal of the latch circuit in which the control signal and the reference signal are synchronized is used as a control signal again.   4. The method according to claim 1, wherein a lock detect signal indicating a lock state output from the PLL circuit is output to the outside to determine whether or not the test can be performed. The semiconductor integrated circuit according to Item.

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