JPH1114704A - Semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently execute the evaluation and debugging of a device to be tested (DUT) by changing the multiple of a phase locked loop(PLL) circuit to arrest the outputs of time and clock so that generation of a test pattern is not advanced. SOLUTION: A clock 100 of 25 MHz is generated from a timing generator 10. A logic data 200 is shaped into a desired pulse by the timing pulse of the generator 10. Consequently, the pattern output of a format control forms a clock 300 having a period of 40 ns. When the multiple of a PLL circuit 40 is then changed from 1 to 2, the output period forms a clock of 20 ns. The lockup output 420 of the PLL circuit 40 is low until the stable state of phase error is detected and locked up by an LPF and is high after it is locked up. Since no clock is outputted until the PLL circuit is locked up, nor is any test executed, evaluating and debugging works of a DUT 81 can be efficiently performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for testing a device under test with a clock whose frequency is changed by a multiple of a PLL circuit.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. As shown in FIG. 4, the main parts of the conventional device are a timing generator 10, a pattern generator 20, a format control 30, a PLL,
The circuit 40, the driver 50, the comparator 60, the digital compare 70, and the performance board 80 are used to test the DUT 81 of the device under test. First, the operation of each component will be described.

A timing generator (Timing Generat)
or) generates a timing pulse in addition to the basic clock.

A pattern generator (Pattern Generato)
r) generates pre-programmed logical data in synchronization with the basic clock.

Format control (Format Contr)
ol) is a circuit that outputs a test waveform in which the pulse width and the phase delay are shaped by the logic data of the test pattern and the clock signal.

As shown in FIG. 3, a PLL (Phase-Locked Loop) circuit detects a phase difference so that the oscillation frequency and phase of the voltage controlled oscillator VCO always coincide with the frequency and phase of the input signal. This is a circuit that oscillates by feedback as a control voltage of the VCO. When the output of the VCO is frequency-divided by 1 / n and compared with the input frequency Fi, a frequency of nFi multiplied by n as the output frequency Fo is obtained.

A driver is a circuit that amplifies a device under test (hereinafter referred to as a DUT) to a voltage for applying a test signal.

[0008] The performance board exchanges signals with a board serving as an interface between the semiconductor test apparatus and the DUT.

[0009] The comparator is a circuit for comparing the output signal of the DUT with a comparison voltage.

[0010] Digital Compare
Is a circuit for comparing the comparison result of the comparator with the logic data of the pattern generator as an expected value and determining whether the result is acceptable or not.

Next, the operation of changing the clock cycle by changing the multiple of the PLL circuit 40 will be described with reference to the timing chart of FIG. As shown in FIG. 5A, the timing generator 10 to 25 MH
A clock 100 having a z (cycle of 40 ns) is generated.

In the format control 30,
For example, as shown in FIG. 5B, the logical data 200 of the pattern generator 20 is converted into 1, 1, 1, 1,.
・Then, as shown in FIG. 5C, the logic data 200 is shaped into a desired pulse by the timing pulse of the timing generator 10. As a result, the pattern output of the format control 30 has a period of 40n.
s clock 300. Then, assuming that the multiple of the PLL circuit 40 is 1, the output 400 has a period of 40 ns as shown in the first half of FIG.

Next, when the multiplier of the PLL circuit 40 is changed from 1 to 2 times, the output cycle becomes a clock of 20 ns as shown in the latter half of FIG. 5D. However, as shown in the middle of FIG.
Time to lock up, for example, 5ms to 10m
During s, the period becomes unstable. Here, the time until lock-up is the time from when the multiple of the PLL circuit 40 is switched to when the frequency or cycle after switching is settled.

Therefore, an unstable clock is output from the driver 50 and applied to the DUT 81 until the PLL circuit 40 locks up. Therefore, as shown in FIG. 5E, the output 600 obtained by comparing the output of the DUT 81 with the comparator 60 is indeterminate during the time until the PLL circuit 40 locks up, and the DUT 81
Evaluation and test program debugging efficiency are not good.

[0015]

As described above, when the DUT is tested by changing the frequency of the clock to a desired value by changing the multiple of the PLL circuit, the period until the PLL circuit locks up is reduced. It is unstable, and there is a practical inconvenience that the evaluation efficiency of the DUT and the debugging efficiency of the test program are not good. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to prevent the output of a clock and prevent the generation of a test pattern from proceeding until lock-up is performed by changing a multiple of a PLL circuit. It is an object of the present invention to provide a semiconductor test apparatus as described above.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a semiconductor test apparatus for testing a device under test with a clock whose frequency is changed by a multiple of a PLL circuit. A gate means for blocking a clock from the PLL circuit until lock-up occurs when the lock-up occurs, and a match detecting means for detecting when the lock-up output matches an expected value. The gist of the semiconductor test apparatus is as follows.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, a main part of the present invention is a timing generator 10 and a pattern generator 2.
0, format control 30 and PLL circuit 4
0, a driver 50, a comparator 60, a digital compare 70, and a performance board 80, and an AND gate 41, a comparator 61, and a digital compare 71 are added to the conventional configuration. The operation of the same components as in the description of the related art is the same as in the description of the related art, and thus the description is omitted.

The operation of changing the clock cycle by changing the multiple of the PLL circuit will be described with reference to the timing chart of FIG. As shown in FIG. 2A, the timing generator 10 outputs 25 MHz.
A clock 100 having a period of 40 ns is generated.

In the format control, for example, as shown in FIG. 2B, the logical data 200 of the pattern generator is set to 1, 1, 1, 1,... Then, as shown in FIG.
00 is shaped into a desired pulse by the timing pulse of the timing generator 10. As a result, the pattern output of the format control is a clock 300 having a period of 40 ns. Also, the multiple of the PLL circuit 40 is set to 1
As shown in the first half of FIG. 2D, the output 400 is 40 ns.

Next, when the multiple of the PLL circuit 40 is changed from 1 to 2 times, the output cycle becomes a clock of 20 ns as shown in the latter half of FIG. 2D. However, as shown in the middle of FIG.
Time to lock up, for example, 5ms to 10m
During s, the period becomes unstable.

Therefore, an unstable clock is supplied to the driver 50.
As shown in (e) of FIG.
An AND gate 41 is provided in a stage preceding the driver 50, and a PLL is provided.
The lock-up output 420 of the circuit 40 is connected to the AND gate 41.
Gate signal. Here, the lock-up output 420 of the PLL circuit 40 shown in FIG. 3 is at an L (Low) level until the LPF detects a stable state of the phase error and locks up.
(High) level.

Therefore, as shown in the middle of FIG. 2F, the lock-up output 420 is at the L (Low) level until the PLL circuit 40 locks up. DU through 50
No clock is output to T81.

Further, while the clock is not output to the DUT 81, it is necessary not to advance the counter of the pattern generator 20 or the like. Then, (g) of FIG.
As shown in FIG.
The value 0 is compared with the H (High) level by the comparator 61 to obtain an output 610.

When the output 610 matches the logical data 200 of the expected value, a match output 710 is output from the digital compare 71 to the pattern generator 20.
Here, a match means that a dummy cycle is generated until the output of the DUT reaches a specific state, and a match is made when the output of the DUT reaches a specific state, and the test is executed after the match state. Therefore, the match output 710 is used as a start signal for the counter of the pattern generator 20 or the like. Then, the comparator 6 with the clock multiplied by 2
As for the output 600 of 0, the digital comparison 70 starts the pass / fail judgment of the test result.

As a result, no clock is output until the PLL circuit locks up, and no test is executed, so that the DUT 81 can be evaluated and the test program can be debugged efficiently.

In the present embodiment, the multiple of the PLL circuit is switched between 1 and 2 for the sake of simplicity of explanation, but the switching between the desired multiples is similarly performed. it can.

[0027]

The present invention is embodied in the form described above and has the following effects. That is,
The clock is not output until the PLL circuit locks up, and the logical data from the pattern generator can be started in synchronization with the clock output, so that the DUT evaluation and the test program debugging work can be performed efficiently. There is an effect that can be implemented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor test apparatus according to the present invention.

FIG. 2 is a timing chart of the semiconductor test apparatus of the present invention.

FIG. 3 is a block diagram of a PLL circuit.

FIG. 4 is a block diagram of a conventional semiconductor test apparatus.

FIG. 5 is a timing chart of a conventional semiconductor test apparatus.

[Explanation of symbols]

 Reference Signs List 10 timing generator 20 pattern generator 30 format control 40 PLL circuit 41 AND gate 50 driver 60, 61 comparator 70, 71 digital compare 80 performance board 81 DUT

Claims (1)

[Claims] 1. A semiconductor test apparatus for testing a device under test with a clock whose frequency is varied by a PLL circuit.
A semiconductor test apparatus comprising: gate means for blocking a clock from the PLL circuit; and match detection means for detecting when an output of a lockup matches an expected value.