JP2003248037A - Pll testing circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To verify locking operation by operating a PLL by the same frequency as that at actual operation, even when the maximum output clock frequency of a low-speed and general-purpose tester is lower than the frequency of the reference clock of the PLL in actual operation. <P>SOLUTION: This PLL testing circuit is provided with a frequency divider for dividing the frequency of an internal clock outputted from the PLL and outputting a frequency-divided clock, an output switch for selectively outputting the internal clock outputted from the PLL or the frequency-divided clock outputted from the frequency divider according to a test mode signal, and a frequency-measuring device for measuring the frequency of the internal clock outputted from the PLL and outputting the result of the measurement. As a result this, the PLL is operated at the speed of the actual operation at test mode to measure the frequency of the internal clock outputted from the PLL. By outputting the result of the measurement to the outside, whether the internal clock has a specific frequency is verified easily and externally. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to a high-speed PLL (Ph
ase Locked Loop: a test circuit for operating and testing an actual phase-locked loop).

[0002]

2. Description of the Related Art In a PLL, for example, a reference clock (REFCLK) having a predetermined frequency input from the outside and a phase and frequency of an internal clock output from the PLL itself are controlled to match each other. By using the PLL, it is possible to generate an internal clock whose phase and frequency are synchronized (locked) with respect to the reference clock.

By the way, when testing a PLL, there is a method of inputting a reference clock having the same frequency as in actual operation and confirming whether or not the PLL locks at a predetermined frequency according to specifications. However, with the recent increase in the operating speed of LSIs, the operating frequency of the PLL has also become extremely high, and in a low-speed, low-priced general-purpose tester, a high-speed reference clock that is the same as the actual operating speed of the PLL is supplied to the PLL. I can't. Therefore, there is a problem that the PLL cannot be tested at the actual operation speed.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to solve the problems based on the above-mentioned prior art, and when the maximum output clock frequency of a low-speed general-purpose tester is lower than the reference clock frequency during actual operation of the PLL. Even in that case, it is an object of the present invention to provide a PLL test circuit capable of confirming the lock operation by operating the PLL at the same frequency as the actual operation.

[0005]

To achieve the above object, the present invention divides an internal clock output from a PLL and outputs a divided clock according to a divider and a test mode signal. , An output switch that selectively outputs the internal clock output from the PLL or the divided clock output from the frequency divider, and the frequency of the internal clock output from the PLL, and the measurement result is displayed. A PLL test circuit comprising a frequency measuring device for outputting, wherein the PLL performs a multiplication operation by comparing an output signal of the output switching device with a reference clock input from the outside. is there.

Here, the frequency divider outputs a plurality of frequency division clocks having different frequency division ratios, and the output switching device outputs the internal clock output from the PLL or the frequency division clock according to the test mode signal. It is preferable to selectively output one of the plurality of divided clocks output from the frequency divider.

Further, it is preferable that the frequency divider can change the frequency of the divided clock in accordance with the test mode signal.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION The PLL test circuit of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a conceptual diagram of the configuration of an embodiment of the PLL test circuit of the present invention. The PLL test circuit 10 shown in the figure tests whether or not the PLL 12 locks at the actual operation speed, and outputs the test result. Basically, the frequency divider 14, the output switcher 16, and the The frequency measuring device 18 is provided. The figure also shows the PLL 12 to be tested and the buffer 20 that buffers and outputs the output signal of the output switcher 16.

First, the PLL 12 outputs an internal clock whose phase and frequency are synchronized with a reference clock REFCLK input from the outside. In the case of this embodiment, PLL1
The multiplication number of 2 is twice the reference clock REFCLK.
For example, when the 100 MHz reference clock REFCLK is input, the 200 MHz internal clock is output. Any known PLL 12 can be used, and the multiplication rate thereof is not limited at all.

Next, in the PLL test circuit 10, the frequency divider 14 is initialized by the reset signal RESET and then outputs a divided clock obtained by dividing the internal clock output from the PLL 12 by a predetermined dividing ratio. To do. In the case of the present embodiment, the frequency division ratio of the frequency divider 14 is set to four times the internal clock output from the PLL 12. For example, when the PLL 12 outputs an internal clock of 200 MHz, the frequency divider 1
From 4, a divided clock of 50 MHz is output.

In the present embodiment, the frequency division ratio of the frequency divider 14 is fixed at 4 times in the following description, but the present invention is not limited to this, and the frequency division of the frequency divider 14 may be performed as necessary. The period ratio may be set to 1 time, or may be set to 2 times or more. Further, the frequency division ratio of the frequency divider 14 may not be fixed, and may be appropriately changed by a signal for setting the frequency division ratio. Also,
The number of frequency-divided clocks output from the frequency divider 14 is not limited to one, and a plurality of frequency-divided clocks having different frequency division ratios may be output in parallel.

Then, the output switch 16 selectively outputs the internal clock output from the PLL 12 or the divided clock output from the frequency divider 14 in accordance with the test mode signal TESTMODE. In the case of the present embodiment, the output switch 16 outputs the internal clock output from the PLL 12 when the test mode signal TESTMODE is at the low level, and the test mode signal TESTMODE is output.
When is at a high level, the divided clock output from the frequency divider 14 is output.

A signal ICL output from the output switch 16
K is input to the user logic (not shown) via the buffer 20 and fed back to the PLL 12. In the PLL 12, the reference clock REFCLK input from the outside and the signal output from the output switch 16 and fed back via the buffer 20 are compared, and the phase and frequency synchronized with the reference clock REFCLK from the PLL 12 is internally generated. The clock is output.

Here, the test mode signal TESTMOD
E is a signal for determining the operation mode of the PLL test circuit 10. In this embodiment, the PLL test circuit 10 is set to the normal operation mode when the test mode signal TESTMODE is at low level, and the test mode signal TE
When STMODE is at high level, the test mode is set. The test mode signal TESTMOD in the illustrated example
E is a 1-bit signal, but is not limited to this and may be a 2-bit signal or more.

The output switching device 16 may have any conventionally known structure as long as it can selectively output one of a plurality of input signals in accordance with the switching signal. Is. As described above, when the frequency divider 14 outputs a plurality of divided clocks, the output switcher 16
Depending on the test mode signal TESTMODE of a plurality of bits, one of the internal clock output from the PLL 12 or the plurality of divided clocks output from the frequency divider 14 is selectively output.

Finally, the frequency measuring device 18 is
It detects whether or not the internal clock output from is a predetermined frequency, and outputs the detection result VCOOUT to the outside. In the case of the present embodiment, the detection result VCOOUT is a 1-bit signal.
This means that the internal clock output from 2 has a predetermined frequency, and conversely, if it is at a low level, it does not have a predetermined frequency.

The specific configuration of the frequency measuring instrument 18 is not limited at all, and various types for realizing the above functions can be used. The detection result VCOOUT may be a 1-bit signal as in this embodiment, or may be a signal of a plurality of bits, for example, a signal representing the frequency of the internal clock may be encoded and output.

Next, the operation of the PLL test circuit 10 will be described.

In the case of this embodiment, as described above, the PLL 12
And the frequency division ratio of the frequency divider 14 is quadrupled. In addition, when the PLL 12 is actually operating, P
The frequency of the reference clock REFCLK input to the LL12 is 100 MHz, the maximum output frequency of the general-purpose tester that tests the PLL12 is 30 MHz, and the reference clock R input from the general-purpose tester to the PLL12 during the test operation is set.
The frequency of EFCLK is set to 25 MHz which does not exceed the maximum output frequency of 30 MHz.

First, the test mode signal TESTMODE
Is low, the PLL test circuit 10 is in the normal operation mode. In this case, the reference clock REFCLK of 100 MHz is input from the outside, and the PLL 12 outputs
An internal clock of 200 MHz, which is double the frequency, is output. The internal clock output from the PLL 12 is output from the output switch 16 and is supplied to the user logic via the buffer 20 and fed back to the PLL 12.

As a result, the reference clock and the fed back internal clock are repeatedly compared in the PLL 12, and the phases and frequencies of the reference clock and the internal clock output from the PLL 12 are synchronized.

On the other hand, the test mode signal TESTMODE
Is high, the PLL test circuit 10 is in the test mode. In this case, the 25 MHz reference clock REFCLK is input from the general-purpose tester. Also, the frequency divider 1
From 4, the internal clock output from the PLL 12 is 4
The divided clock that has been divided is output, and the output switch 1
6, supplied to the user logic via the buffer 20, and fed back to the PLL 12.

As a result, the phase and frequency of the PLL 12 are synchronized with the reference clock REFCLK, and the PLL
An internal clock of 200 MHz having a frequency of 2 times the multiplication rate of 12 times 4 times the frequency division rate of the frequency divider 14 = 8 times is output.
Further, the frequency measuring device 18 measures the frequency of the internal clock output from the PLL 12, and the frequency is 2
If it is 00 MHz, a high level is output as the measurement result VCOOUT, and if it is not 200 MHz, a low level is output.

In other words, the reference clock REFC input from the general-purpose tester to the PLL 12 in the test mode.
If the frequency of LK is 1 / n of the frequency of the reference clock REFCLK at the time of actual operation of the PLL 12, the frequency divider 14
The PLL 12 can be operated at the actual operation speed by increasing the frequency division ratio of n times. The frequency division ratio of the frequency divider 14 depends on the speed at which the PLL 12 is operated.
It may be appropriately determined according to the frequency of the reference clock REFCLK.

In this way, in the PLL 12 to which the PLL test circuit 10 of the present invention is applied, even when the maximum output clock frequency of the low-speed general-purpose tester is lower than the reference clock frequency during actual operation of the PLL 12, PLL1
2 can be operated at the same frequency as in actual operation.
Further, whether or not the PLL 12 can normally perform the lock operation can be easily confirmed externally by the measurement result VCOOUT by the frequency measuring device 18.

The PLL test circuit of the present invention is basically as described above. Although the PLL test circuit of the present invention has been described above in detail, the present invention is not limited to the above-described embodiments, and it goes without saying that various improvements and modifications may be made without departing from the spirit of the present invention. is there.

[0028]

As described above in detail, the PL of the present invention is used.
The L test circuit divides the internal clock output from the PLL at a predetermined frequency division ratio corresponding to the frequency of the reference clock input from the general-purpose tester to generate a divided clock.
By feeding back to, the PLL is operated at the actual operation speed, the frequency of the internal clock output from the PLL is measured, and the measurement result is output. As a result, according to the PLL test circuit of the present invention, even if the frequency of the reference clock input from the general-purpose tester is lower than the frequency of the reference clock during the actual operation of the PLL, the PLL operates at the actual operation speed. It can be operated, and it can be easily confirmed from the outside whether or not the PLL is correctly locked at the actual operation speed.

[Brief description of drawings]

FIG. 1 is a configuration conceptual diagram of an embodiment of a PLL test circuit of the present invention.

[Explanation of symbols]

10 PLL test circuit 12 PLL 14 frequency divider 16 output switch 18 Frequency measuring instrument 20 buffers

Continued front page    F-term (reference) 2G029 AA02 AB06 AC04                 2G036 AA19 BA46 CA10                 2G132 AA12 AB01 AC03 AD04 AG08                       AK07 AK15 AL11                 5J106 AA04 CC52 DD09 DD17 FF07                       KK32

Claims (3)

[Claims] 1. A frequency divider for dividing an internal clock output from a PLL and outputting the divided clock, and an internal clock output from the PLL or the frequency divider according to a test mode signal. An output switching device that selectively outputs the divided clock that is output, and a frequency measuring device that measures the frequency of the internal clock output from the PLL and outputs the measurement result. A PLL test circuit which performs a multiplying operation by comparing a reference clock generated and an output signal of the output switch. 2. The frequency divider outputs a plurality of frequency-divided clocks having different frequency division ratios, and the output switching device outputs the internal clock or the frequency-divided clocks from the PLL according to the test mode signal. The PLL test circuit according to claim 1, wherein one of the plurality of divided clocks output from the frequency divider is selectively output. 3. The PLL test circuit according to claim 1, wherein the frequency divider can change the frequency of the divided clock in accordance with the test mode signal.