KR101775636B1 - Circuit for generation signal with frequency synthesizer - Google Patents

Abstract

The present invention relates to a clock signal generation circuit having a frequency synthesizer. The clock signal generation circuit prevents that a normal counter operation is impossible since a current clock signal and a rising section of a next clock signal are combined due to a big logic delay value when a large phase shift with respect to a multiphase clock signal occurs at one time when generating the multiphase clock signal by using an open loop fractional frequency divider using a frequency divider based on a multiphase output and a counter.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a clock signal generating circuit having a frequency synthesizer,

The present invention relates to a technique for generating a clock signal using an open-loop fractional divider using a multi-phase output and a counter-based divider in a clock signal generating circuit with a frequency synthesizer, And a clock signal generator circuit having a frequency synthesizer for preventing the current clock signal from being combined with the rising period of the next clock signal to make it impossible to perform a normal count operation when a large phase shift is performed at a time will be.

The prior art clock signal generation circuit includes a phase locked loop circuit with a frequency synthesizer and an open loop fractional divider with a counter based divider.

In the clock signal generation circuit according to the related art, when an externally supplied reference clock signal is applied to the phase locked loop circuit, an output signal having a constant frequency and multiple phases is generated from the externally supplied reference clock signal, It is supplied as an input of fractional divider.

In this state, the counter operation of the open-loop fractional frequency divider is determined according to an external control code value, and two adjacent clock signals output from the open-loop fractional frequency divider are selected by the output value of the counter, do.

Thereafter, the two clock signals are divided through an interpolation circuit, and one of the divided clock signals is selected and output according to the control code value of the interpolation counter.

The clock signal thus output is divided by the frequency divider through the counter-based switching operation and output as the final clock signal.

However, in the clock signal generation circuit according to the related art, if a large phase shift is performed for the multi-phase output at one time according to the control code, if the clock signal is shifted from the rising section to the falling section of the clock signal, The logic delay time is too long to be combined with the rising edge of the next clock signal.

In this case, since the counter counts the rising edge of the clock signal, if the clock signals are combined, the normal counting operation is not performed, thereby failing to generate a desired type of clock signal.

Domestic Publication No. 10-2010-0051926 Korean Patent No. 10-1080658

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a clock signal generating circuit using a phase locked loop circuit in which a phase locked loop circuit shifts a multi- So that it takes almost no time to return to the normal state.

Another problem to be solved by the present invention is to implement a logic using a sequential counter so as to shift the clock signal in three times in consideration of logic delay when a large phase shift is performed at a time in a clock signal generating circuit, Lt; RTI ID = 0.0 > fractional < / RTI >

Another object of the present invention is to provide a clock signal generation circuit that allows a counter-based divider to use a divided clock signal through phase shifting and interpolation, thereby allowing a clock signal generating circuit to have a wider output frequency range .

According to an aspect of the present invention, there is provided a clock signal generating circuit including a frequency synthesizer, comprising: a first counter for counting a first control code supplied from the outside using a clock signal, ; A decoder to decode the count signals and generate enable signals accordingly; A multiplexer for outputting two clock signals which are enabled by the enable signals and are phase-shifted by a '1 / multiphase number'period; A second counter for counting a second control code and outputting count signals corresponding thereto; An interpolation circuit for dividing the two clock signals into a plurality of phases and selecting one clock signal among the clock signals divided into the plurality of phases according to the count signals outputted from the second counter; A third counter for counting the clock signal output from the interpolation circuit and outputting enable signals corresponding thereto; A buffer driven by one of the enable signals output from the third counter and buffering the clock signal output from the interpolation circuit; And a first frequency divider and a second divider serially connected to divide the clock signal supplied from the buffer and output the divided clock signal as a final clock signal.

The present invention relates to a clock signal generation circuit having a frequency synthesizer, and more particularly, to a clock signal generation circuit having a frequency synthesizer, wherein when a multi-phase clock signal is generated using an open- In order to prevent the logic delay value from being large when the phase shift is made so that the current clock signal is combined with the rising period of the next clock signal to make normal counting impossible, the phase locked loop circuit shifts the multi- So that only the phase shift delay is generated and the time for returning to the normal state is almost zero.

In addition, when a large phase shift is performed on the clock signal at a time in the clock signal generation circuit, the logic using the sequential counter is implemented so as to shift in three times in consideration of the logic delay, By implementing an open loop fractional frequency divider having a high resolution, a wider frequency range can be secured.

1 is a block diagram of a clock signal generating circuit having a frequency synthesizer according to an embodiment of the present invention.
2 is a detailed block diagram of an open loop fractional divider;
3 is a detailed circuit diagram of the dump circuit.
4 is a timing chart of the dump circuit.
5 is a detailed block diagram of the first counter.
6 is a timing chart of the first counter.
7A is a detailed block diagram of the second counter.
7B is a detailed block diagram of the interpolation circuit.
8 is a timing diagram of an interpolation circuit, a decoder and a multiplexer.
9A is a block diagram for explaining the concept of the counter based divider circuit applied to the 1-3 counter.
9B is a timing diagram of the frequency divider circuit.
10A is a detailed block diagram of the third counter.
10B is a detailed circuit diagram of the buffer.
11 is a timing diagram for a third counter based dividing circuit.
12 to 16 are waveform diagrams showing simulation (HSPICE) results for confirming the operation of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a clock signal generation circuit having a frequency synthesizer according to an embodiment of the present invention. As shown in FIG. 1, the clock signal generation circuit 100 includes a phase locked loop circuit 100A and a clock signal generation unit 100B ).

The phase locked loop circuit 100A receives a reference clock signal REF_CLK from the outside and outputs a multi-phase clock signal, for example, a clock signal SOUT of 63 phases through a phase locked loop operation. When the frequency of the multiphase clock signal SOUT is varied, the phase locked loop circuit 100A shifts the phase of the multiphase clock signal SOUT while maintaining the steady state, and outputs only the phase shift delay , So that it takes almost no time to return to the normal state.

To this end, the phase locked loop circuit 100A includes a first control voltage generator 110 that does not use the reference clock signal REF_CLK, a frequency divider 120, a second control voltage using the reference clock signal REF_CLK, A generating unit 130, a multiplexer 140, and a voltage-controlled oscillator 150. [

The first control voltage generator 110, which does not use the reference clock signal REF_CLK, includes a reference voltage generator (BGR) and a regulator to control the voltage controlled oscillator according to the output signal of the reference voltage generator Thereby generating the voltage BGR_CTL.

The frequency divider 120 divides the multi-phase clock signal SOUT at a constant rate to generate a frequency division signal SDIV having a lower frequency.

The second control voltage generator 130 using the reference clock signal REF_CLK includes a phase-frequency detector (PFD), a charge pump, and a loop filter to generate a reference clock signal (PLL_CTL) for controlling the voltage-controlled oscillator according to the comparison result of the frequency divider signal REF_CLK and the dividing signal SDIV.

The multiplexer 140 selectively passes the control voltage BGR_CTL output from the first control voltage generator 110 and the control voltage PLL_CTL output from the second control voltage generator 130.

The voltage-controlled oscillator 150 outputs a multi-phase clock signal SOUT having a constant frequency according to the control voltage output from the multiplexer 140.

The clock signal generator 100B has eight channels of open-loop fraction divider 160A-160H.

The open loop divider divider 160A-160H selects two clock signals having phases adjacent to each other among the 63 phase multi-phase clock signals SOUT supplied from the voltage-controlled oscillator 150, And shifts the phase to a counter that receives the control code as input.

In the open loop divide-by-two divider 160A-160H, the two clock signals shifted in phase through the above process are divided into clock signals having eight phases again through the internal interpolation counter. The open loop fractional divider 160A-160H selects one of the clock signals having the eight phases according to the output value of the interpolation counter according to the control code value. In the open loop divide-by-two divider 160A-160H, one of the clock signals output as described above is divided and output as a final clock signal through a counter-based divider circuit.

The open loop fractional divider 160A-160H have the same configuration. 2 shows a detailed block diagram of any one of the open loop fraction divider 160A-160H, for example, the open loop divider divider 160A. As shown therein, a dump circuit 200 A first counter 210, a decoder 220, a multiplexer 230, a second counter 240, an interpolation circuit 250, a third counter 260, a buffer 270, a first frequency divider 280 And a second frequency divider 290.

The dump circuit 200 generates a first control code MUX [5: 0] synchronized with its output signal FS_OUT using an external control code, a load signal LOAD and an output signal FS_OUT of the open loop fractional frequency divider 160A. 0], the second control code INT [2: 0] and the third control code CONT, A fourth control code DIV [3: 0] is generated, and the control code thus generated is used as an input of each counter and a frequency divider.

When the first control code MUX [5: 0] is input, the first counter 210 counts the first control code MUX [5: 0] using the clock signal MUX_CLK and outputs the count signal S0- S5.

The decoder 220 decodes the count signal S0-S5 of the first counter 210 and generates an enable signal EN [62: 0] corresponding thereto.

The multiplexer 230 is enabled by the enable signal EN [62: 0] and generates two clock signals MUX_IN0, MUX_IN0, MUX_IN0, and MUX_IN0, which are phase- MUX_IN1).

The second counter 240 counts the second control code INT [2: 0] as the interpolation counter and outputs the corresponding count signals I_S0, I_S1, and I_S2.

The interpolation circuit 250 divides the clock signals MUX_IN0 and MUX_IN1 into eight phases and selects one of the clock signals divided into the eight phases according to the count signals I_S0, I_S1, and I_S2 And outputs it as a clock signal C_CLK.

The third counter 260 counts the clock signal C_CLK and outputs the enable signals EN0, EN3, EN4, and EN5 corresponding thereto.

The buffer 270 is driven by an enable signal EN0 output from the third counter 260 to buffer the clock signal C_CLK.

The first frequency divider 280 and the second divider 290 connected in series receive the fourth control code DIV [3: 0] and divide the clock signal O_CLK supplied from the buffer 270 to generate a final clock And outputs it to the signal FS_OUT.

Here, if the phase of any one of the clock signals MUX_CLK supplied to the first counter 210 is shifted by more than a predetermined value, a short clock signal MUX_CLK of less than or equal to a predetermined value generated by logic delay, May be added to the rising period of the clock signal (MUX_CLK) shifted much more than the predetermined value. In this case, since the rising edge of the corresponding clock signal MUX_CLK does not appear, the first counter 210 can not normally perform the count operation, thereby making it impossible to normally generate the count signals S0-S5 .

In order to prevent such a phenomenon, by shifting the phase to be shifted by the three clock signals MUX_CLK, even if the logic delay amount is larger than a predetermined value, the short clock signal MUX_CLK and the phase As a result, there is a sufficient margin between rising sections of the much shifted clock signal MUX_CLK, and the above problem is solved.

62 [0: 0]) using the count signal S0-S5 of the first counter 210, and outputs the enable signal EN [62: 0] The half period of the clock signal MUX_CLK is shifted first by using the corresponding enable signal, the remaining half period is shifted by using the next enable signal, and the next half period of the first counter 210 is shifted Logic is provided at the input of the first counter 210 so that one phase according to the overflow and the clock signal FLAG generated at the output of the second counter 240 is shifted.

FIG. 3 is a detailed block diagram of the dump circuit 200. As shown therein, a flip-flop (F / F 311-F / F 313) for generating a synchronized dump clock signal dump_clk, F / F 321-F / F 326 and delay logic DL301 for synchronizing the clock signal FS_OUT with the clock signal FS_OUT of the open-loop divide-by-two frequency divider 160A.

4 is a timing diagram of the dump circuit 200. Referring to FIG. 4, the operation of the dump circuit 200 will be described as follows.

The load signal LOAD input from the outside is used as the clock signal of the first flip-flop F / F 311 to output the dump enable signal dump_en (dump_en) from the first flip-flop F / F 311 at the rising edge of the load signal LOAD Quot; high ". The dump enable signal dump_en is used as the input signal of the second flip-flop F / F 312, which uses the clock signal FS_OUT of the open loop divide-by-two period 160A. The dump clock signal dump_clk output through the second flip-flop F / F 312 and the delay logic DL301 when the dump enable signal dump_en is high is the clock of the open-loop fractional frequency divider 160A And becomes " High " at the rising edge of the signal FS_OUT. The dump clock signal dump_clk is used as a clock signal of a plurality of flip-flops (F / F 321-F / F 326) having external control codes MUX_A [5] to DIV_A [0] Synchronized with the clock signal FS_OUT of the loop divide-by-two frequency divider 160A, and then input to each counter.

At the same time, the output signal of the second flip-flop F / F 312 is delayed by the delay logic DL301, and then the first flip-flop F / F 311 and the second flip-flop F / F 312 are reset to generate a dump clock signal the control code of the open loop divider divider 160A in which the external control codes MUX_A [5] to DIV_A [0] are synchronized with the rising edge of the dump clock signal dump_clk is obtained .

FIG. 5 is a detailed block diagram of the first counter 210. As shown in FIG. 5, a full adder (FA500-FA505) connected in multiple stages to output the count signals S0- (FF500-FF505).

The first counter 210 having the above-described structure is provided for each rising edge of the clock signal MUX_CLK The inputs of all the adders FA500-FA505 are added so that the phase of the clock signal MUX_CLK is shifted by the desired control code.

The enable signal EN0, EN3, and EN5 output from the third counter 260 and the flip-flops 260 and 260 output from the third counter 260 are sequentially shifted in order to shift the phase of the clock signal MUX_CLK by more than a predetermined value, The control signals WS0 to WS2 are generated using the flip-flops FF520 to FF522 and supplied to the inputs of the full adders FA500 to FA505.

Since the first counter 210 counts 63 counters in the present embodiment, only the MSB input is shifted by a full adder (FA 505) in order to shift the phase by 32 cycles when the control signal WS0 is in the rising state in the phase shift mode of the clock signal MUX_CLK. And the input of the remaining bits is blocked.

Thereafter, when the control signal WS1 is in the up state, the MSB input is prevented from being supplied to the pre-adder FA505 to shift the remaining phases, and the remaining bits are supplied to the pre-adders FA500-FA504.

The control signal WS2 is supplied to the input of the LSB pre-adder FA500 for shifting the phase by one cycle when an overflow occurs in the second counter 240 for the interpolation operation.

In addition, when overflow occurs for 63 counts of the first counter 210 or 64 counts, the phase of one cycle is further shifted to perform 63 counting operations.

6 is a timing diagram of the first counter 210, which will be described below.

When the control signal WS0 is in the rising state, the first counter 210 is set to the 32-cycle shift. Thereafter, when the rising edge of the clock signal MUX_CLK appears, the 32-period shifted clock signal MUX_CLK is output. At this time, the control signal WS0 transitions to the falling state, the control signal WS1 transitions to the rising state, and the remaining bits except the MSB input are set.

When the rising edge of the clock signal MUX_CLK appears again, the set value of the remaining bits is output. At this time, the control signal WS1 transits to the falling state and the control signal WS2 transitions to the rising state. An LSB value is set according to a flag value formed by an overflow of the first counter 210 or an overflow of the interpolation circuit 250.

Thereafter, when the rising edge of the clock signal MUX_CLK appears again, the value set to the LSB is outputted, the control signal WS2 is brought to the falling state, the control signal WS0 is brought to the rising state, The shifting count operation is repeatedly performed.

7A is a detailed block diagram of the second counter 240. As shown in FIG. 7A, a full adder (FA700-FA400) connected in multiple stages and outputting count signals I_S0, I_S1, FA 703 and a flip-flop FF700-FF703.

The second counter 240 counts the second control code INT [2: 0] using the clock signal INT_CLK and outputs the corresponding count signal IS0-IS2.

7B is a detailed block diagram of the interpolation circuit 250 and includes an interpolator 251 and a decoder and a multiplexer 252 as shown in FIG.

The interpolator 251 divides the two phase-shifted clock signals MUX_IN0 and MUX_IN1 by 8 and outputs clock signals S0-S7 corresponding thereto, as shown in Fig .

The decoder and the multiplexer 252 select one of the clock signals S0 to S7 according to the count signals IS0 to IS2 supplied from the second counter 240 and output them as the clock signal C_CLK Reference).

9A is a block diagram for explaining the concept of a counter based dividing circuit applied to the counters 210, 240 and 260. As shown in FIG. 9A, the N-bit counter 901, the transmission gate TR901, (I901) and a MOS transistor (M901). FIG. 9B is a timing chart when the divider circuit of FIG. 9A operates in the six dividing mode. FIG.

Each time the falling edge of the reference clock signal CLK_REF is inputted while the third control code CONT [N-1: 0] is input, the counter 901 counts by 1 and generates a count output FOUT corresponding thereto . When the output value overflows during operation of the counter 901, the enable signal EN becomes the rising state, thereby activating the transmission gate TR901. Thus, instead of the count output FOUT being cut off, the reference clock signal CLK_REF is output through the transmission gate TR901.

In this state, the counter 901 is initialized, receives the control code value at the falling edge of the next reference clock signal CLK_REF, and starts the count operation one by one. At this time, the enable signal EN is in a falling state, and the transmission gate 901 is inactivated. Thus, instead of interrupting the output of the reference clock signal CLK_REF, the count output FOUT is output.

The control code input to the N-bit counter 901 is expressed by the following equation (1).

Here, CNT is a target division value. For example, the 6-bit counter 901, Based frequency divider performs the 6-dividing operation, the control code CONT [5: 0] should be set to 59 according to the above-mentioned equation (1).

Referring to the timing chart of FIG. 9B, when the counter 901 counts 1 from 59 to 63 and counts 1 when 63 is counted, the count output FOUT becomes 0 when an overflow occurs. At this time, the enable signal EN rises and the transmission gate TR901 is activated as described above, whereby the reference clock signal CLK_REF is output to the count output FOUT. At this time, the input of the counter 901 is initialized and starts counting the value set in the control code at the falling edge of the next supplied reference clock signal (CLK_REF).

Accordingly, the transmission gate TR901 is activated or deactivated by the enable signal EN as described above, and the count output FOUT is divided and output by the count value of the reference clock signal CLK_REF.

10A is a detailed block diagram of the third counter 260 and includes a counter 261, an enable signal output unit 262, and a reset signal output unit 263 as shown in FIG. 10B is a detailed circuit diagram of the buffer 270. FIG.

FIG. 10A illustrates a counter-based frequency divider circuit of FIG. 9A, which has a wider output frequency range by changing the division ratio to 3 or 4 by using a control code of 1 bit. For example, the third counter 260 performs a 3-count operation when the value of the third control code CONT is 0, and a 4-count operation when the value of the third control code CONT is 1. When the third counter 260 starts the count operation and the output value becomes '000', the reset signal C_RESET rises and the third counter 260 is initialized. Accordingly, the third counter 260 counts 1 again.

The enable signal output section 262 performs logic operation on the count values S0, S1 and S2 of the counter section 261 and outputs the enable signals EN0, EN3 and EN4.

The reset signal output section 263 inverts the count values S0, S1, and S2 of the counter section 261 after performing an OR operation and outputs a reset signal C_RESET corresponding thereto. When the counter unit 261 is initialized by the reset signal C_RESET, the counter unit 261 counts 1 again.

The buffer 270 is enabled or disabled by the enable signal EN0. When enabled, the buffer 270 outputs the clock signal C_CLK output from the interpolation circuit 250 as a clock signal O_CLK.

Therefore, the frequency variable range of the clock signal FS_OUT is determined according to the count value of the second counter 240.

11 is a timing chart for a frequency divider circuit based on the third counter 260. In FIG. The third counter 260 performs a 3 or 4 count operation in accordance with the third control code CONT and when the count output value is S [2: 0] = 000, the reset signal C_RESET rises, Is initialized and accordingly starts counting from 1 again. The enable signals EN0, EN3, EN4 and EN5 are generated in accordance with the count value S [2: 0] of the counter 261 and the output path is turned on according to the enable signal EN0 / OFF to divide the clock signal C_CLK by the count value and output it.

As a result, the frequency of the clock signal output from the clock signal generation circuit 100 according to the present invention is determined by a combination of an input code of a counter for shifting the phase, a code for determining interpolation, and a division ratio of a frequency divider using a counter Is determined according to the following equation (2).

Here, T _ref is the period of the PLL's multi-phase output, M is the number of multiple phases, N is the number of interpolation, LIN is the coefficient ratio of the third counter 260, INT is the number of interpolation shifts, 1 < / RTI > In the embodiment of the present invention, T _ref = 7.8125 ns, M = 63, N = 8, LIN is 3 when cont is 0, and 4 when cont is 1.

12 to 16 are waveform diagrams showing simulation (HSPICE) results for confirming the operation of the present invention. Here, the supply voltage is 2.5 V and T _ref = 7.8125 ns, M = 63, N = 8, and LIN = 3.

FIG. 12 is a waveform diagram showing a simulation result of the dump circuit 200. FIG. The change in the external control code is not immediately applied to the counter input of the open loop divide-by-two frequency divider 160A and the change in the output signal rising edge of the open-loop divider divider 160A, which appears after the rising edge of the load signal LOAD, The control code value is applied.

FIG. 13 is a waveform diagram showing the simulation result of the first counter 210. FIG. It can be confirmed that the count output value of the first counter 210 is 62 and one phase due to the overflow is divided into three sections and 63 shifts are made. As shown in FIG. 9B, when it is required to shift by more than a half period, two periods of a half period and a remaining phase are required, and a flag due to overflow and interpolation of the first counter 210 is set to The first counter 210 must be a counter capable of counting a minimum of 3 or more.

Fig. 14 And a third control code CONT of the third counter 260 is 1, the simulation result is a waveform diagram. The third counter 260 performs a count operation in which the output value is incremented by 1 and is initialized by the reset signal C_RESET when the count output value s [2: 0] = 000, Repeat. The third counter 260 outputs the enable signals EN0, EN3, and EN5 according to the count output value. In particular, the enable signal EN0 generated when the count output value s [2: 0] = 111 acts to interrupt or connect the final output signal path, thereby performing the dividing function. The control signal WS is generated based on the enable signals EN0, EN3 and EN5 outputted from the third counter 260. This causes the third counter 260 to divide the phase shift operation into three sections It plays a role. The enable signal EN4 output from the third counter 260 serves to cause the first counter 210 to periodically display the rising edge three times.

FIG. 15 is a waveform diagram of a simulation result showing an instantaneous frequency change according to a control code change of the frequency synthesizer in the phase locked loop circuit 100A. The frequency of the multi-phase clock signal having a constant frequency is changed by the shift of the counter output value and the interpolation output value according to a control code inputted from the outside, so that it can be changed immediately without steady state arrival time according to the frequency change unlike the PLL .

16 is a timing chart showing the operation of the first counter 210 and the interpolation circuit 250 when the first counter 210 and the interpolation circuit 250 operate in accordance with the control code of the frequency synthesizer, And eye diagrams and jitter measurements for three cases.

According to the embodiment of the present invention, the frequency of the clock signal can be changed instantaneously by shifting the phase in accordance with the control code using multiple phases without time to reach the steady state in the clock signal generation circuit have. When the frequency phase of the clock signal is shifted by half a cycle or more, it is shifted three times, so that a sufficient spare time can be secured at the phase shift. In addition, a counter capable of controlling the external control code coefficient value is used to connect or disconnect the final output path to the output value, thereby having a wide frequency variable range according to the count value of the counter.

Although the preferred embodiments of the present invention have been described in detail above, it should be understood that the scope of the present invention is not limited thereto. These embodiments are also within the scope of the present invention.

100: Clock signal generation circuit 100A: Phase locked loop circuit
100B: clock signal generator 110: first control voltage generator
120: frequency divider 130: second control voltage generator
140: Multiplexer 150: Voltage controlled oscillator

Claims (11)

A phase locked loop circuit for outputting a multi-phase clock signal through a fixed loop operation; And a clock signal generator having a plurality of channels of open-loop divide-by-divider divisions, the clock signal generator comprising:
The open-loop fractional frequency divider
A first counter for counting a first control code supplied from the outside using a clock signal and generating count signals according to the first control code;
A decoder to decode the count signals and generate enable signals accordingly;
1 < / RTI > / multiphase number < RTI ID = 0.0 > A multiplexer for outputting two clock signals having a phase difference of a cycle;
A second counter for counting a second control code and outputting count signals corresponding thereto;
An interpolation circuit for dividing the two clock signals into a plurality of phases and selecting one clock signal among the clock signals divided into the plurality of phases according to the count signals outputted from the second counter;
A third counter for counting the clock signal output from the interpolation circuit and outputting enable signals corresponding thereto;
A buffer driven by one of the enable signals output from the third counter and buffering the clock signal output from the interpolation circuit; And
A first frequency divider and a second divider serially connected to divide the clock signal supplied from the buffer and output the divided clock signal as a final clock signal,
The phase locked loop circuit performs frequency conversion by shifting the phase of the multiphase clock signal while maintaining the steady state when the frequency of the multiphase clock signal is varied,
Wherein the first counter is provided with a sequential counter logic for shifting the phase by several intervals in consideration of a logic delay when the phase of any one clock signal among the clock signals is shifted by more than a predetermined value A clock signal generation circuit having a frequency synthesizer.
The apparatus of claim 1, wherein the first counter
And a plurality of flip-flops and a plurality of pre-adders connected in multiple stages to output the count signals.
3. The apparatus of claim 2, wherein the first counter
In the phase shift mode of the clock signal, only the MSB input is supplied to the highest-order full adder among the plurality of pre-adders in order to shift the phase by the corresponding period when the first control signal is in the rising state, Wherein the clock signal generating circuit comprises a frequency synthesizer.
3. The apparatus of claim 2, wherein the first counter
The MSB input is prevented from being supplied to the most significant pre-adder among the plurality of pre-adders to shift the remaining phase when the second control signal is in the up state in the phase shift mode of the clock signal, To the clock signal generating circuit.
3. The apparatus of claim 2, wherein the first counter
And when the overflow occurs in the second counter for the interpolation operation in the phase shift mode of the clock signal, supplies the input to the lowest-order all-adder of the plurality of pre-adders so as to further shift the phase by one cycle. A clock signal generation circuit comprising a synthesizer.
2. The apparatus of claim 1, wherein the second counter
And a plurality of flip-flops and a plurality of pre-adders connected in multiple stages to output the count signals.
The apparatus of claim 1, wherein the interpolation circuit
An interpolator for dividing a plurality of phase-shifted clock signals and outputting a plurality of clock signals corresponding thereto;
And a decoder and a multiplexer for selecting one of the plurality of clock signals according to the count signals supplied from the second counter and outputting the selected clock signal.
2. The apparatus of claim 1, wherein one of the first to third counters comprises:
A counter for counting by one each time a falling edge of a reference clock signal is input in a state where a control code is inputted and generating a count output according to the counter; And
And a transmission gate that is activated when an overflow of an output value occurs during operation of the counter and outputs the reference clock signal when the count output is interrupted.
9. The clock signal generation circuit as claimed in claim 8, wherein the transmission gate is activated by an enable signal output from the counter.
The apparatus of claim 1, wherein the third counter
A counter for counting a third control code and outputting count signals corresponding to the third control code;
An enable signal output unit for logically counting the count signals of the counter unit and outputting enable signals corresponding thereto; And
And a reset signal output unit for inverting and counting the count signals of the counter unit and outputting a reset signal corresponding thereto.
2. The clock signal generation circuit according to claim 1, wherein the clock signal generation circuit
The first control code and the second control code, the third control code and the fourth control synchronized with the output signal of the open loop fractional frequency divider using the external control code, the load signal, and the output signal of the open- Further comprising a dump circuit for generating a clock signal.

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