JP3248698B2 - PWM signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM signal generator used for a power supply device of an electrophotographic copying machine.

[0002]

2. Description of the Related Art The present applicant has previously proposed a method of generating a PWM signal or the like by calculation of a CPU (Japanese Patent Application No. 3-129122). This method will be described with reference to Conventional Example 1 and Conventional Example 2.

FIG. 7 is a block diagram of a "PWM signal generating apparatus" which is a first conventional example. In the figure, 201 is a self-running binary counter composed of n bits (generally an integral multiple of nibble), and 202 is a register (or accumulator) composed of the same bit length (register length). , 205 are digital comparators that compare the MSB from the corresponding LSB of each of 201 and 202 for each bit, and output “1” when the values of all bits match. The coincidence output “1” is output to a signal line 210, and is output to a T flip-flop (hereinafter, referred to as TFF) 20.
6 and at the same time, the CPU 204
Is supplied to the interrupt input terminal. 203 is ROM
Thus, the CPU 204 can access data and an execution program. The CPU 204 executes the register 2
02 is input to the signal line 209, and its operation output terminal is connected to the signal input terminal of the register 202 through the signal line 212. A system clock is supplied to the counter 201 and a clock signal input terminal of the CPU 204 via a signal line 207, and is also supplied to a digital comparator 205 for synchronization. The control signal output terminal of the CPU 204 is connected to the control signal input terminal R of the counter 201 through a signal line 213.

Next, the operation will be described with reference to the flowchart of FIG.

When the CPU 204 enters a system operable state (see S21 in FIG. 8), the PW
The control information of M, for example, the data in the period of L level of the generated signal waveform is taken out (S22) and set in the register 202 (S23). Then, the CPU 204 sends a count start signal to the counter 201 through the signal line 213 (S24). If the counter 201 is a binary up counter, for example, it counts up in synchronization with the system clock input through the signal line 207, and when the value matches the information in the register 202, the digital comparator 205 detects the match (S25). , S2
6) Output a signal of "1" on the signal line 210. In this case, the CPU 204 sends a clear signal to the TFF 206 via the signal line 214 in advance and resets it. As a result, the output signal of the TFF 206 is inverted (S2
7), the signal state of the output terminal 211 of the device changes from “L” to “H”. At the same time, the signal becomes an interrupt signal and is applied to the interrupt signal input terminal of the CPU 204. The CPU 204 detects the interrupt signal (S2
8) The data of the "H" level period in which the signal waveform is newly generated is extracted from the ROMs 1 and 203 (S29),
The sum of the data and the data in the “L” level period on the register 203 read by the signal line 209 is obtained, and the result is reset in the register 202 (S30). At that time, the sum carry data is discarded. The same operation is repeated, and if there is a coincidence output, the state of the output signal of the TFF 206 is inverted, data of the next “L” level period is read out, the sum of the data with the data of the register 202 is obtained, and the result is obtained. Set in the register 202 (S31 to S3
6). By repeating the above operation, a desired signal waveform can be obtained at the output terminal 211.

It is assumed that the bit length of the counter 201 is long enough to generate a pulse having a cycle longer than one cycle of the signal to be generated.

FIG. 9 is a block diagram of a second conventional example. This conventional example is a modification of the conventional example 1 and generates two output signal waveforms.

[0008] This conventional example is different from the conventional example 1 in that the RAM 3
00, the selector 301, and the TFFs 302 and 303 are different.

Output line 2 of digital comparator 205
Reference numeral 10 denotes a selector 30 as well as an input terminal of the CPU 204.
1 signal input terminal. A signal select terminal of the selector 301 is connected to a select signal output terminal of the CPU 204 through a signal line 304. One of the output terminals of the selector 301 is connected to the T input terminal of the TFF 302, and the other is connected to the T input terminal of the TFF 303.
Outputs of the TFFs 302 and 303 are supplied to output terminals 305 and 306 of the device, respectively. Also, TFF
Reset terminals 302 and 303 are connected to the CPU 204 via a signal line 214. RAM 300 is a CP
It is connected to the U 204 by a bus, and has a structure in which the CPU 204 can read and write at an arbitrary timing. The other circuits are the same as in the first conventional example, and the description is omitted.

Next, the operation will be described. FIG. 10 is a time chart showing the operation.

[0011] After the system reset, the CPU 204 takes out the data 1 in the L level period of the first signal waveform and sets it in the register 202 at the timing of time t1. Assuming that one cycle of the clock of the counter 201 is T, the digital comparator 205 compares the value of the counter 1 with the value of the register data 2 at the timing T1 of t1 + T / 4, and the selector 301 switches at that timing. The result of the match comparison on the signal line 310 is set in the TFF1 · 302 in synchronization with the signal. At timing t2 of t1 + 2 / 4T, the CPU 204 stores the data 1 of the register 202 in the RAM 300 through the signal line 209, and stores the data 2 of the second signal waveform during the L level period in the ROM.
1 and set in the take-out register 202.
At timing T2 of t1 + 3 / 4T, the CPU 204 switches the selector 301, and sets the signal line 210 to TFF2 • 20.
3 and supplies the result of the match comparison on the signal line 310 to the TFFs 2 and 303 in synchronism therewith.

At time t3 of t1 + T, the counter 2
01 indicates that the counter value is counted up by one,
04 stores the data 2 in the register 202 in the RAM 300, and at the same time, sets the data 1 stored in the RAM 300 in the register 202 at the timing of t2.
Similarly to t1 to t3, the comparison judgment of the next one cycle starts (the ROM reading at t1 is changed to the RA reading at t3).
M reading). Then, the above operation is continued until the determination signal on the signal line 210 is inverted. Each time the comparison result on the signal line 210 is inverted, the output signal of the TFF 302/303 selected at that timing is inverted, and at that time tn, the CPU 204 reads the data of the register 202, N that determines the timing of the output inversion of the TFF
Is accessed, added to the data from the register 202 and stored in the RAM 300, and the operation described above is continued.

FIG. 11 is an operation flowchart of a modification of the second conventional example. This modification uses n TFFs and n selectors having channel switching capability, divides one cycle into 2n, executes the same procedure as in the conventional example 2 for n data, and generates n PWM signal waveforms. , And a detailed description is omitted.

[0014]

In the above-mentioned conventional method, since the PWM signal is generated by the software of the CPU, there are the following problems a, b, and c.

A. Low frequency PWM of about 1K to 5KHz
Only signals can be generated.

B. If a CPU is exclusively used for generating a PWM signal, unnecessary hardware circuits are wasted.

C. It is difficult to control a switching power supply or the like, which has a slow response and requires a high-frequency PWM signal and a high-speed response.

The present invention has been made in order to cope with such a situation, and has as its object to generate a PWM signal capable of obtaining a plurality of control operations at a high frequency.

[0019]

In order to achieve the above object, according to the present invention, a PWM signal generator is provided by the following (1) to (1).
The configuration is as shown in (5).

(1) A counter for counting a predetermined clock pulse, register means for setting required data, and a count value of the counter and the register means are provided in the register means .
Comparing the constant data, and a digital comparator issuing a coincidence output whenever they are consistent, each time matching the output of the digital comparator, and an output inverting means for inverting the state of the output signal of the apparatus, also the comparator a of each of the coincidence output, PWM signal generator with a setting means for setting the required data in the register means, the setting means, Oyo oN width of the PWM signal
ON data and OFF data representing the
It has a latch that is activated and an adder that operates in a time-sharing manner.
The adder adds the data to the register
Exchanges the ON data or OFF data set in the
The required data is calculated by adding each other , and the calculated required
PW for setting the data of
M signal generator.

(2) The setting means includes a first PWM signal
ON and OFF data representing the ON width and OFF width of the
A first latch in which data is set, and a second PWM signal
ON data and ON data representing the ON width and OFF width of the signal, respectively.
And a second latch Fudeta is set, the A <br/> said first and second data in said register by Zehnder
ON data or OFF data set in the latch of
And the first and second PWM signals are respectively added to the first and second PWM signals.
The P according to (1), wherein the corresponding data is calculated.
WM signal generation device.

[0022] (3) setting means, in response to information from an external circuit, by adding a predetermined value to the data of the register means to calculate the required data by the adder, PWM signal
The PWM signal generation device according to the above (1) or (2), which controls the ON width and / or the OFF width of the PWM signal.

(4) The PWM signal generating apparatus according to (1) or (2), wherein the setting means controls the ON width of the PWM signal in accordance with the carry output of the adder.

[0024] (5) setting means, said <br/> register means data by adding on the data representing the ON width of the calculated required data for on-width control by said adder, and said <br The data of the register means includes ON data representing the ON width.
The PWM according to ( 1) or (2), wherein required data for off-width control is calculated by adding data obtained by inverting the above.
Signal generator.

[0025]

According to the above-mentioned constitutions (1) to (5), required data in a plurality of different control operations are calculated by the adder and set in the register means to generate a required PWM signal. In the configuration of (2), a plurality of PWM signals are generated, and in the configuration of (3), the on-width and / or off-width of the generated PWM signal is controlled.
In the configuration (1), the ON width of the generated PWM signal is limited, and in the configuration (5), the PWM of a constant frequency is used.
A signal is generated.

[0026]

The present invention will be described below with reference to examples.

(Embodiment 1) FIG. 1 shows a first embodiment of the "PW
1 is a block diagram of an “M signal generation device”.
6 to 8 are 8-bit latches (registers) whose output terminals are connected to buses 6 through clocked buffers 11 to 16, respectively.
5 is connected. The outputs of the latches 1 and 2 are inverted by inverters 55 and 54, respectively.
It is supplied to a bus 64. Output terminals of latches 7 and 8 are connected to bus 6 through clocked buffers 19 and 20, respectively.
4 is connected. The input terminals of the latches 1 to 8 are connected to the bus 75, respectively.

The bus lines 64 and 65 are respectively connected to different sets of input terminals of an adder (adder) 63, and the output terminals of the adder 63 are connected to latches 9 and 10 via a bus 66.
And a bus 75 through a clocked buffer 74. The bus 75 is connected to the CPU bus 73 through the clocked buffer 25.

The output terminals of the latches 9 and 10 are connected to the bus 69 via the clocked buffers 23 and 24 via the buses 67 and 68, respectively, and are connected to the bus 64 via the clocked buffers 22 and 21 respectively. .
Reference numeral 26 denotes an UP free-run counter. The count output terminal is connected to one set of input terminals of the digital comparator 27 via a bus 70. The other set of input terminals of the digital comparator 27 is connected to the bus 69.

Reference numerals 29 and 30 denote synchronous T flip-flops (hereinafter, T flip-flops are referred to as TFFs), which perform a toggle operation. The respective Q output terminals are P
It is connected to WM1.OUT and PWM2.OUT.
The clock input terminal is connected to the TSET bar signal line, and the data input terminals are connected to the output terminals of the two-input AND gates 41 and 42, respectively. One of the input terminals of the two-input AND gates 41 and 42 is connected to the output terminal of the digital comparator 27. 2
The remaining input terminals of the input AND gates 41 and 42 are SU
It is connected to the M1O and SUM2O signal lines.

Reference numerals 31 and 32 denote D latches. The data input terminal D is connected to the carry output terminal of the adder 63. The latch signal input terminals are connected to the output terminals of the two-input AND gates 38 and 39, respectively. One input terminal of each of the two-input AND gates 38 and 39 has
The TSET signal line applied to the clock input terminal of the adder 63 is connected, and the other input terminal
OFS and PM2OFS signal lines are connected.

The Q output terminals of the D latches 31 and 32 are connected to one input terminals of two-input AND gates 35 and 36 and input terminals of inverters 56 and 57, respectively.

An analog comparator 51 has an input terminal connected to an output terminal of a reference power supply 52 having one end grounded, and an input terminal to which a signal FBIN1 of a control information detection circuit of an external control circuit is input. . The output terminal of the analog comparator 51 is connected to the data input terminal of the DFF 28, and the Q bar output terminal is connected to the two-input gate 33.
And the Q output terminal is connected to one input terminal of the two-input gate 34. The other input terminals of the two input gates 33 and 34 are both connected to PM
It is connected to one ONS signal line.

The output terminals of the two-input gates 33 and 34 are connected to one input terminal of the two-input OR gates 81 and 82, respectively, and at the same time, UP1 and D of the 1H detection circuit 61 are connected.
Each is also connected to the W1 signal input terminal.

Reference numeral 51-2 denotes an analog comparator. Like the comparator 51, an output terminal of a reference power supply 52-2 having one end grounded is connected to its-input terminal, and a + input terminal is used to detect control information of an external control circuit. Circuit signal FBIN2
Is entered. The analog comparator 51-
2 is connected to the data input terminal of the DFF 28-2, the Q bar output terminal of the DFF 28-2 is connected to one input terminal of the 2-input AND gate 33-2, and the Q output terminal is connected to the 2-input AND gate. 34-2 is connected to one input terminal. In addition, a two-input AND gate 33-2,
The other input terminal of 34-2 is connected to the PM2ONS signal line. Also, a two-input AND gate 33
Output terminals of −2 and 34-2 are connected to one input terminals of two-input OR gates 81 and 82, respectively, and at the same time, are connected to UP2 and DW2 signal input terminals of the 1H detection circuit 62, respectively.

The output terminals of the two-input OR gates 81 and 82 are connected to the signal control terminals of the clocked buffers 20 and 19, respectively.

One input terminals of the two-input AND gates 35 and 36 are connected to signal lines of CHG1ON and CHG2ON, respectively, and output terminals thereof are connected to control terminals of the clocked buffers 11 and 12, respectively.

The control signal input terminals of the PWM1 and PWM2 latches 9 and 10 are 2-input AND gates 40 and 37, respectively.
Output terminal. One input terminals of the two-input AND gates 40 and 37 are both connected to a TSET signal line, and the other input terminals are CHG1 and C
The signal line of HG2 is connected.

Reference numerals 47 and 48 denote two-input AND gates, one of which has CHG1ON and CHG2ON, respectively.
Are connected. The other input terminal is connected to the output terminals of the inverters 56 and 57, respectively. 49 and 50 are three-input OR gates, one input terminals of which are connected to the output terminals of two-input AND gates 47 and 48, respectively. The other two input terminals respectively have a three-input OR gate 49 and PM1OFS, PM1O
The NS signal line is connected to the 3-input OR gate 50 by PM2O.
The signal lines of FS and PM2ONS are connected. The output terminals of the three-input OR gates 49 and 50 are connected to the control terminals of the clocked buffers 13 and 14, respectively.

A TSET signal line is connected to one input terminal of each of the two-input AND gates 43 and 44.
The other input terminals are PM1ONS and PM2, respectively.
The ONS signal line is connected. Output terminals of the two-input AND gates 43 and 44 are connected to one input terminals of two-input OR gates 45 and 46, respectively. The other input terminals of the two-input OR gates 45 and 46 are connected to ON1SET and ON2SET signal lines, respectively. The output terminals of the two-input OR gates 45 and 46 are
They are connected to the latch input terminals of the latches 3 and 4, respectively.

The latch control terminals of the latches 1, 2, 5, and 6 have MAXSET1, MAXSET2, CPU
The signal lines of SET1 and CPUSET2 are connected.
Also, clocked buffers 15, 16, 17, 18, 2
PM1OF0, PM2OF0, PM2OFS, PM1
OFS, CHG2, CHG1, SUM1O, SUM2O
Are connected.

The Q output and Q bar output terminals of the D latch 80 are connected to the control terminals of the clocked buffers 25 and 74, respectively. Reference numeral 80 denotes a CPU flag. An address signal is input to a latch input terminal of the CPU, and a signal line is connected to a data input terminal so that data set to the flag can be set from the CPU.

Reference numeral 53 denotes a timing generation circuit for generating signals of the above-described signal lines, and 58, 59, and 60 are some of the components. 81 is a basic clock input terminal,
The input terminal of the divide-by-2 circuit 59 and the input terminal of the delay circuit 60 are connected. The output terminal of the delay circuit 60
At the same time as being connected to the TSET signal line, it is also connected to the input terminal of the inverter 58. The output terminal of the divide-by-2 circuit 59 is connected to the clock input terminal of the free-run counter 26. The output terminal of the inverter 58 is connected to the TSET bar signal line. Further, the timing circuit 53 has an input terminal from the Q output signal of the DFFs 29 and 30. Note that the delay time that can be generated by the delay circuit 60 is a time equal to or less than a half cycle of 0 to φ.

Numerals 61 and 62 denote digital value 1H detection circuits, the input terminals of which are connected to the output buses of the latches 3 and 4, respectively. The output signals of the DFFs 28 and 28-2 are input to both control signal input terminals as described above. Output signal lines of the 1H detection circuits 61 and 62 are connected to reset input terminals of the latches 3 and 4, respectively. The inverters 54, 55, 104
The details are configured as shown in FIG.

Next, the operation of this embodiment will be described.

The operation will be described with reference to FIG. 3 showing the basic timing and FIG. 4 showing the outline of the processing sequence. Although not shown in the block diagram of FIG. 1, all the latches, flip-flops, and counters are reset to 0H (hexadecimal zero) at the start of the operation of this embodiment.

The UP free-run counter 26 counts from 0 to 1
It counts up by one and operates to become 0 when it reaches FFH. The basic principle of the pulse generation is the same as that of the conventional example. When the ON data and the OFF data of the generated PWM signal pulse are pulse 1 (the PWM signal generated at PWM1 · OUT), the data of the PWM1 latch 9 is Each time the value matches the value of the UP free-run counter 26, the UP
The value of the free-run counter 26 and the on-data or off-data of the pulse to be generated are alternately summed by an adder 63, the result is set again in the latch 9, and the value is compared with the value of the UP free-run counter 26. Compare the value and repeat this procedure. At this time, the ON data and the OFF data to be added are stored in the latches 3 and 5, respectively, and
At the timings of 1ON and PM1OF0, the clocked buffers 13 and 15 become through and latch by the adder 63.
And the result is set in the latch 9 again.

FIG. 4 shows a simple flowchart of the processing procedure for PWM1.

Similarly, in the case of the pulse 2 (PWM signal generated at PWM2.OUT), every time the data of the PWM2 latch 10 matches the value of the UP freerun counter 26, the UP freerun counter when the data matches The value of 26 and the on-data or off-data of the pulse to be generated are alternately summed by an adder 63, the result is set again in the latch 10, and the value and the UP free-run counter 2
6 and repeat this procedure. then,
On data and off data to be added are
6, the clocked buffers 14 and 16 become through at the timings of CHG2ON and PWM2OF0, respectively, and the adder 63 performs a sum operation with the contents of the latch 10 and sets the result in the latch 10 again.

In terms of timing, the latch 9 and the counter 26
Latch 1 at the same timing as the digital match comparison of
The adder 63 executes a sum operation of the data of 0 and the data of the latch 4 or 6 and the result is set in the latch 10 again. Similarly, the digital operation of the latch 10 and the counter 26 is performed. At the same timing as the coincidence comparison, the adder 63 executes the sum operation of the data of the latch 9 and the data of the latch 3 or 5, and the result is set in the latch 9 again. However, these sum operations are always performed by PWM1 · O
The timing immediately following the inversion of the output values of UT and PWM2.OUT and the timing at which no coincidence signal of the comparator occurs, that is, CHG1ON, CHG2ON,
It is executed only at the timing of PM1OF0 and PM2OF0.

For these controls, the clocked buffers 13, 14, 15, 16, 21, 22, 23, and 24 need to be appropriately switched and controlled. The basic control signals are shown in the time chart of FIG. Show. Specifically, CHG1ON, CHG2ON, PM1OF0, P
M2OF0, CHG2, CHG1, SUM1O, SUM
2O. The adder 63 operates to set the result of the sum of the signals applied to its input terminal to its output at each rising timing of the TSET signal, and output the value on the bus line 66. That is, the configuration is such that the normal adder and the DFF are integrated into one module. Further, a control signal obtained by ANDing TSET and CHG1 is applied to the latch 9 through a two-input AND gate 40.
, A logical product of TSET and CHG2 is given through a two-input AND gate 37. The clocked buffers 23 and 24 have SUM1O and SUM, respectively.
A control signal of UM2O is provided, and the above-described complicated control can be operated in a time division manner.

It should be noted that CHG1 and CHG2 are P
The timing of the next 31.25 nsec immediately after the inversion of WM1.OUT and PWM2.OUT indicates that CHG1 = C
HG1ON + PM1OF0, CHG2 = CHG2ON +
PM2OF0.

The comparison result of the digital comparator 27 is output to a signal line 71, and the two-input AND gates 41 and 42 are provided.
Are output to the T inputs of the TFFs 29 and 30 by sampling at the timing of TSET bar, and inverting the outputs to output PWM1 • OUT and PWM2 • OUT.
, A correct PWM signal is output.

For convenience of explanation, all latches, counters, comparators, and adders in FIG. 1 are 8 bits, but can be implemented with an appropriate bit size. The timing example of FIG. 3 is for the case where 3H data is set in the PWM1 latch 3 and the PWM2 latch 4, respectively.

The initial value of each circuit is such that the CPU turns on the flag 80, puts the clocked buffer 25 into a through state, and puts the clocked buffer 74 into a high impedance state. Then, the CPU sends a data set signal generated from the address signal and the strobe signal to the signal line M.
AXSET1, MAXSET2, ON1SET, ON2
In addition to SET, CPUSET1, and CPUSET2, initial data is set in latches 1, 2, 3, 4, 5, and 6 via buses 73 and 75, respectively. Then the CPU
Writes 0 in the flag 80, makes the clocked buffer 74 through, and puts the clocked buffer 25 into a high impedance state.

Next, control of the ON width of the PWM signal pulse will be described. This control is performed using the adder 63 by using the PWM1ONS and the PM2ONS during the timing when the PWM signal is off (0), where no coincidence of the digital comparator 27 occurs.

The ON width of PWM1 · OUT is controlled by controlling the value of the external feedback signal FBIN1 with respect to the value of the comparison reference voltage Vrefl of the analog comparator 51 to Vre.
When f1 <FBIN1, the ON width of PWM1.OUT is reduced to reduce the value of FBIN1, and Vr
When ef1> FBIN1, feedback control is performed such that the ON width of PWM1.OUT is increased and the value of FBIN1 is increased.

The output value of the analog comparator 51 is sampled by the DFF 28 in synchronism with the CMP.CLK1 (PM1OFS can be substituted). When the output is H, the Q output of the DFF 28 becomes H. L is sampled on the Q output.

When the Q output of the DFF 28 is H,
The gates 33, 34, 81, and 82 select the clocked buffer 19 at the timing when the signal of PW1ONS becomes H, and the clocked buffer 20 enters a high impedance state, and conversely, when the Q output of the DFF 28 is L, The gates 33, 34, 81, 82
At the timing when the signal of M1ONS becomes H, the clocked buffer 20 is selected and becomes through, and the clocked buffer 19 enters a high impedance state.

That is, when increasing the ON width, the sum of the register value of 01H of the latch 8 and the value of the latch 3 is calculated, and the sum is written into the latch 3 again to increase the value of the latch 3 by 1. Is controlled. When the ON width is reduced, the sum of the register value of FFH of the latch 7 and the value of the latch 3 is calculated, and the sum is written into the latch 3 again to control the value of the latch 3 by one.

Similarly, the control of the ON width of PWM2.OUT is performed by comparing the reference voltage Vr of the analog comparator 51-2.
External field back signal FBIN for the value of ef2
When the two values are Vref2 <FBIN2, PWM2 ·
The ON width of OUT is reduced to reduce the value of FBIN2, and when Vref2> FBIN2, PWM2
Feedback control is performed such that the ON width of OUT is increased and the value of FBIN2 is increased.

The output value of the analog comparator 51-2 is supplied to the DFF 28-2 by the CPM · CLK2 (PM2O
FS signal).
When the output is H, the Q output of the DFF 28-2 becomes H. When the output is L, L is sampled on the Q output.

When the Q of the DFF 28-2 is H,
By the gates 33-2, 34-2, 81, 82, PM2
At the timing when the ONS signal becomes H, the clocked buffer 19 is selected and becomes through, and the clocked buffer 2
0 is in a high impedance state, and conversely, when the Q output of the DFF 28 is L, the clocked buffer 20 is selected by the gates 33, 34, 81 and 82 at the timing when the signal of PM1ONS becomes H, and the clocked buffer 20 becomes through. 19 is in a high impedance state.

In other words, when increasing the ON width, the sum of the register value in which 01H of the latch 8 is written and the value of the latch 4 is written to the latch 4 again, and the value of the latch 4 is set to 1
It is controlled to increase. To reduce the ON width, the register value of FFH of the latch 7 and the latch 4
, And write it to Latch 4 again.
Is controlled so as to reduce the value of “1”.

The timing for the above control is PWM.
1. Latch 3 containing control data for ON width of OUT
, The signals of PM1ONS and TSET are passed through a two-input AND gate 43, and further applied through an OR gate 45.
An M1ONS signal is provided. Similarly, PWM2 ・ OU
For the latch 4 containing the control data of the ON width of T, the PM2ONS and TSET signals are supplied through the two-input AND gate 44 and further supplied through the OR gate 46, and the PM2O is supplied to the buffer 14 through the OR gate 50.
NS signal is provided. Note that CMP · CLK1 is
This is a sampling signal synchronized with PM1ONS.
MP · CLK2 may be a sampling signal synchronized with PM2ONS.

By changing the values of the latches 8 and 7, the ON width to be increased or decreased can be appropriately selected.

Next, control of the pulse maximum value (maximum ON width) limiter will be described. This control also uses the timing when the PWM signal of the comparator 27 where no coincidence occurs is off (0). Specifically, PM1OFS, PM1
The calculation is performed using the adder 63 using 2OFS.

In the case of PWM1.OUT, the inverted value of the register value of the latch 3 and the inverted value of the register value of the latch 1 (the maximum pulse width value of the PWM1) are added by the adder 63 at the timing of PM1OFS. , D latch 31 is set to 1; otherwise, 0 is set. The latch timing is determined by PWM1OFS and TS1.
The ET signal is supplied to 31 through an AND gate 38. Once the Q output of the D latch 31 becomes 1, the 2-input AND gate 47 is turned off, the 2-input AND gate 35 is turned on, and when the next CHG1ON signal is input, the latch 3 is replaced with the latch 3 The contents of the register value of 1 are output on the bus 65. That is, the ON width of PWM1.OUT is always controlled to the maximum value of the ON width set in the latch 1.

That is, when the sum of the inverted value of the width data of the maximum value of the latch 1 and the ON width is larger than the data of the width of the maximum value of the latch 1, the carry is added to the result of the above-described sum operation. This is because a control method of latching and controlling this information is used, utilizing the occurrence.

When the Q output of the D latch 31 is 0, one of the inputs of the two-input AND gate 47 becomes H, the two-input AND gate 35 is turned off, and the next CHG1ON is turned on.
Is input, the contents of the latch 3 are output on the bus 65 as they are.

For controlling these buses, latches 17 and 1
8, clocked buffers 11, 12, 13, and 14 are respectively PM2OFS, PM1OFS, CHG1ON, C
Control is performed in synchronization with HG2ON, CHG1ON, and CHG2ON. Incidentally, 54 and 55 are latches 2 and 1 respectively.
Is an inverter for inverting the contents of all the bits and outputting the inverted data to the bus 64 via the clocked buffers 17 and 18, respectively. The details are shown in FIG. Note that the minimum value control of the ON width can be easily realized by using the same method.

Reference numerals 61 and 62 denote PWM1 and PWM, respectively.
2 is a minimum ON width detection circuit for detecting the ON width 1H in the present embodiment and preventing the ON width from being smaller than the width. Detected and DW1 and DW2 are 1, UP1, UP
When 2 is 0, the registers 3 and 4 are operated to always set the register to 1, and DW1 and DW2 are set to 1 to 0, respectively.
When UP1 and UP2 change from 0 to 1, the latch 3,
Operates to release the set of 1 to 4.

In the case of PWM2 · OUT, the register value of the latch 4 and the register value of the latch 2 (PWM2 maximum pulse width value) are added by the adder 63 at the timing of PM2OFS, and if there is a carry in the result, the D latch 32 Is set to 1; otherwise, 0 is set. Note that the timing of the latch is such that the PM2OFS and the TSET signal are 2
The signal is supplied to the D latch 32 through an input AND gate 39. Once the Q output of the D latch 32 becomes 1, the 2-input AND gate 48 is turned off, the 2-input AND gate 36 is turned on, and when the next CHG2ON signal is input, the latch 4 is replaced with the latch 4 2 is output on the bus 65. That is, the ON width of PWM2 · OUT is controlled to the maximum value of the ON width that is always set in the latch 2.

This is because when the sum of the inverted value of the data of the maximum value width of the latch 2 and the ON width is larger than the data of the maximum value width of the latch 2, the carry result is added to the result of the aforementioned sum operation. This is because a control method of latching and controlling this information is used by utilizing the fact that the above occurs.

When the Q output of the D latch 32 is 0, one of the inputs of the two-input AND gate 48 becomes H, the two-input AND gate 36 is turned on, and the next CHG2ON is turned off.
Is input, the contents of the latch 4 are output on the bus 65 as they are.

Reference numeral 53 denotes a timing circuit for generating the above operation timing. A basic clock is supplied to the terminal 81, and the signal line divided by the frequency divider 59 is supplied to the clock input of the UP free-run counter 26. Connected to terminal. A signal obtained by delaying the basic clock by the delay element 60 is output as a TSET signal, and a signal obtained by inverting the signal by an inverter 59 is used as a TSET bar. All other timings are
Using the signals of WM1.OUT and PWM2.OUT, it can be easily generated in the timing circuit 53 by a digital differentiation technique.

(Embodiment 2) FIG. 5 is a block diagram of Embodiment 2. Since only the components 100 to 105 are added to the first embodiment, the description of the common portions is omitted here, and only the changed portions will be described.

Reference numerals 101 and 102 denote two-input AND gates. One input terminal of the gate 101 is connected to PM2OF0, the other input terminal is connected to the output terminal of the inverter 100, and the output terminal is connected to the clocked buffer 16. Connected to the control terminal.

Similarly, one input terminal of 2-input AND gate 102 is connected to PM2OF0, the other input terminal is connected to CHANGE terminal via signal line 105, and the output terminal is connected to the control terminal of clocked buffer 103. ing. Similarly, the input terminal of the inverter 100 is connected to the CHANGE terminal through the signal line 105.

The output terminal of the clocked buffer 103 is
It is connected to a bus line 65. The input terminal of the clocked buffer 103 is connected so that the output signal of the latch 4 is inverted by the inverter 104 and input. However, the order of the LSB and the MSB is not changed.

Next, the operation will be described.

When the CPU is transmitting an L signal to the CHANGE terminal, the operation is completely the same as in the first embodiment, and a description thereof will be omitted.

Under this condition, the gates 102 and 1 are set so that the output of the clocked buffer 16 becomes high impedance and the clocked buffer 103 becomes operable.
01,100 works. Under this condition, in the first embodiment, the PWM
2. The off width of the pulse sent from OUT
Is sent out instead of the register value of the latch 4. This means that when the value of the latch 4 increases or decreases by 1, the inverted value increases or decreases by 1 and the sum always matches the maximum value of the register value of the latch 4. That is, under this condition, the PWM2.OUT signal is transmitted as a PWM signal having a constant frequency.

Although the above embodiments use the UP counter, the present invention is not limited to this, and the present invention can be similarly implemented using a DW counter. Further, the external signal is not limited to the feedback signal. In addition, other register means such as a register and a memory can be used as the latch.

[0085]

As described above, according to the present invention, by using one adder to execute a plurality of control operations in a time-division manner, a PWM signal capable of obtaining a plurality of control operations at a high frequency can be obtained. Can be generated.

Further, when implementing an LSI, since a bus connection configuration is possible with the same block structure suitable for the LSI, the circuit chip area is smaller than that of the conventional method when trying to make a 2-channel PWM signal generator, for example. Therefore, it can be manufactured in a size of 50 to 70%, and a significant cost reduction can be realized. Further, the switching between the fixed off-time PWM and the fixed frequency PWM, which is difficult with the conventional method, can be realized very easily, and there is an advantage that the degree of freedom of the application of the PWM signal is increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment;

FIG. 2 shows inverters 54, 55,
Detailed view of 104

FIG. 3 is a time chart of the first embodiment.

FIG. 4 is a flowchart showing the operation of the first embodiment.

FIG. 5 is a block diagram of a second embodiment;

FIG. 6 is a flowchart illustrating the operation of the second embodiment.

FIG. 7 is a block diagram of Conventional Example 1.

FIG. 8 is a flowchart showing the operation of Conventional Example 1;

FIG. 9 is a block diagram of a second conventional example.

FIG. 10 is a time chart of Conventional Example 2

FIG. 11 is a flowchart showing an operation of a modification of Conventional Example 2;

[Explanation of symbols]

 1-10 Latch (or register) 26 UP free-run counter 27 Digital comparator 29,30 DFF 41,422 2-input AND gate 63 Adder

Claims (5)

(57) [Claims] A counter for counting a predetermined clock pulse; a register for setting required data ;
The count value of the counter and the value set in the register
Comparing the the data, and the digital comparator issuing a coincidence output whenever they are consistent, each time matching the output of the digital comparator, and an output inverting means for inverting the state of the output signal of the device, also of the comparator each of the coincidence output, a PWM signal generator with a setting means for setting the required data in the register means, the setting means, the PWM signal oN width and O
ON data and OFF data representing the
Comprising a latch that, the adder operating in time division, the latch data of the register means by the adder
Set ON data or OFF data alternately
The required data is calculated by the addition, and the calculated required data is calculated.
Data is set in said register means . 2. The method according to claim 1, wherein the setting means is configured to output the first PWM signal.
ON data and OFF data that represent the
And a second latch for setting the second PWM signal.
ON data and OFF data representing ON width and OFF width, respectively.
And a second latch which over data is set, the first and second La by the adder to the data of the register
ON data or OFF data set in the switch
And respectively correspond to the first and second PWM signals.
Claims, characterized in that to calculate the required data that
2. The PWM signal generator according to 1 . Wherein setting means, in response to information from an external circuit, by adding a predetermined value to the data of the register means to calculate the required data by the adder, of the PWM signal O <br/> down 3. The PWM signal generator according to claim 1, wherein the PWM signal generator controls a width and / or an off width. 4. The P-type control circuit according to claim 1, wherein said setting means performs limit control of an on-width of a PWM signal in accordance with a carry output of said adder.
WM signal generation device. Wherein setting means, said adder the registration <br/> by adding on the data representing the ON width to the data of the static means calculates the necessary data for the on-width controlled by also the cashier < The required data for controlling the OFF width is calculated by adding data obtained by inverting the ON data representing the ON width to the data of the star means. Item 3. The PWM signal generation device according to Item 2.