WO2023103852A1 - Clock recovery circuit and communication device - Google Patents

Abstract

The present application provides a clock recovery circuit and a communication device. The clock recovery circuit comprises a clock phase discrimination unit and a clock adjustment circuit. The clock phase discrimination unit comprises a processing module and a calculation unit. The processing module is used for processing a clock signal to be recovered so as to output a first undersampled signal and a second undersampled signal which have different sampling phases. The calculation unit is used for estimating a time error signal of a first sampling clock according to the energy difference or the amplitude difference between the first undersampled signal and the second undersampled signal. The clock adjustment circuit is used for adjusting the first sampling clock according to the time error signal. According to embodiments of the present application, clock recovery can be realized for signals of a plurality of modulation formats, and the stability and robustness of a system are high.

Description

Clock recovery circuit and communication equipment

Cross References to Related Applications

This application claims the priority of a Chinese patent with application number 202111506580.8 and application title "Clock Recovery Circuit and Communication Equipment" filed with the China Patent Office on December 10, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the field of electronic technology, in particular to a clock recovery circuit and communication equipment.

Background technique

In a communication system, the transmitter can send a data signal driven by a local clock, and the receiver samples the data signal through the clock signal generated by the phase-locked loop, and detects the deviation between the sampling position and the sampling position of the sending clock, and The time difference can be used to adjust the phase and frequency of the clock generated by the phase-locked loop, thereby recovering the clock of the transmitter. Therefore, it is extremely critical for the communication system to realize normal communication to accurately detect the deviation between the receiving sampling position and the transmitting clock sampling position to drive the phase-locked loop to achieve clock synchronization.

Existing clock recovery circuits are not robust enough to detect clock skew. In addition, the cost and power consumption of the existing clock recovery circuit are relatively high, and the implementation complexity is high.

Contents of the invention

In view of this, the present application provides a clock recovery circuit and communication equipment. By adopting the embodiments of the present application, the synchronization between the local clock of the receiver and the clock of the transmitter can be quickly completed, and the power consumption is low, and the cost is saved.

In a first aspect, an embodiment of the present application provides a clock recovery circuit, where the clock recovery circuit includes a clock phase detection unit and a clock adjustment circuit. The clock phase detection unit includes a processing module and a calculation unit; the processing module is used to process the clock signal to be recovered, so as to output the first under-sampling signal and the second under-sampling signal with different sampling phases; the calculation The unit is used for estimating the time error signal of the first sampling clock according to the energy difference or amplitude difference between the first subsampling signal and the second subsampling signal. The clock adjustment circuit is used to adjust the first sampling clock according to the time error signal.

By adopting the embodiment of the present application, the sampling clock can be adjusted according to the time error signal output by the clock phase detection unit, so that the time error becomes smaller and smaller, so as to recover the required clock signal and complete the clock recovery. The implementation of the present application For example, the synchronization between the local clock of the receiver and the clock of the transmitter can be quickly completed, and the power consumption is low, which saves costs.

In a possible design, the processing module includes a first processing unit and a second processing unit, the first processing unit is configured to perform signal processing on the clock signal to be recovered, so as to output a first undersampling signal; the The second processing unit is configured to perform signal processing on the to-be-recovered clock signal to output a second under-sampled signal, and the sampling phase of the first under-sampled signal is different from that of the second under-sampled signal. Based on such a design, the clock recovery circuit of the present application can calculate the time error signal of the first sampling clock through two under-sampled signals with different sampling phases, and then complete the clock recovery.

In a possible design, the first processing unit is configured to under-sample the clock signal to be recovered by using the second sampling clock of the first phase, and output a first under-sampling signal, and the second processing unit used for undersampling the clock signal to be recovered by using the third sampling clock of the second phase, and outputting a second undersampling signal, and the calculation unit is used for according to the first undersampling signal and the second undersampling signal The energy difference or the amplitude difference of the sampled signals estimates the time error signal of the first sampling clock. Based on this design, the clock recovery circuit of the present application can obtain two undersampled signals by using two sampling clocks with different phases, so that the energy difference between the two undersampled signals can be calculated, and the time error can be obtained more accurately Signal.

In a possible design, the clock adjustment circuit is further configured to divide the frequency of the first sampling clock to generate a second sampling clock for the first processing unit, and the clock adjustment circuit is also configured to The first sampling clock is delayed, and the delayed first sampling clock is frequency-divided to generate the third sampling clock, so as to output the third sampling clock to the second processing unit.

In a possible design, the clock recovery circuit further includes a demodulation unit, the demodulation unit is electrically connected to the first sample and hold unit, and the demodulation unit is used to demodulate the received signal, The modulated baseband signal is sampled by the first sample-and-hold unit to obtain a clock-reconstructed sampling signal.

In a possible design, the clock recovery circuit further includes a power detection unit, the power detection unit is configured to obtain the power amplitude of the baseband signal, and perform clock recovery by using the power amplitude. With such a design, the power detection unit can obtain the instantaneous power of the baseband signal corresponding to the high-frequency modulation signal, and perform clock recovery through the instantaneous power signal.

In a possible design, the clock recovery circuit further includes a first sampling and holding unit, and the clock phase discrimination unit further includes a delay unit, the first sampling and holding unit is used to receive a baseband signal, and A sampling clock samples and holds the baseband signal to output an oversampled signal to the clock phase detection unit, and the first processing unit is used to extract an output from a plurality of the oversampled signals to output the The first undersampled signal; the delay unit is used to delay the oversampled signal, and transmit the delayed oversampled signal to the second processing unit; the second processing unit is used to transmit the delayed oversampled signal to the second processing unit; extracting one output from the delayed oversampled signals to output the second undersampled signal. Based on such a design, the sampling clock can be adjusted according to the time error signal output by the clock phase detection unit, so that the time error becomes smaller and smaller, so as to recover the required clock signal and complete the clock recovery. Embodiments of the present application can The synchronization of the local clock of the receiver and the clock of the transmitter is completed quickly, and the power consumption is low, which saves costs.

In a possible design, the clock phase detection unit further includes a first power processing unit and a second power processing unit, the first power processing unit is electrically connected to the first processing unit, and the second power processing unit The processing unit is electrically connected to the second processing unit, the first power processing unit is used to calculate the first power of the first subsampled signal, and the second power processing unit is used to calculate the second subsampled signal The second power of the signal. Based on such a design, the calculation unit calculates the energy difference of the two powers to obtain a clock error signal to realize clock recovery.

In a possible design, the calculation unit is connected to the first power processing unit and the second power processing unit, and the calculation unit is used to calculate the difference between the first power and the second power The power energy difference to output the clock error signal to the clock adjustment circuit. Based on such a design, the calculation unit calculates the energy difference of the two powers to obtain a clock error signal to realize clock recovery.

In a possible design, the clock phase detection unit further includes a clock combination unit and a serial-to-parallel conversion unit, the clock combination unit is used to output the fourth sampling clock to the processing module, and the processing module uses Under-sampling the clock signal to be recovered by using the fourth sampling clock, so as to output the first under-sampling signal and the second under-sampling signal to the serial-to-parallel conversion unit, and the serial-to-parallel conversion The unit is used to output the first under-sampling signal and the second under-sampling signal to the computing unit in parallel.

In a possible design, the clock recovery circuit further includes a first sampling and holding unit, and the clock phase detection unit further includes a serial-to-parallel conversion unit, and the first sampling and holding unit is used to receive the baseband signal, and is used to pass The first sampling clock samples and holds the baseband signal to output an oversampled signal to the clock phase detection unit; the processing module is used to extract two outputs from a plurality of the oversampled signals to output The first undersampled signal and the second undersampled signal with different phases are sampled to the serial-to-parallel conversion unit.

In a possible design, the clock phase detection unit further includes a first power processing unit and a second power processing unit, and the serial-to-parallel conversion unit is used to convert the first under-sampled signal and the second under-sampled The sampling signal is output to the first power processing unit and the second power processing unit in parallel, the first power processing unit is used to calculate the first power of the first subsampled signal, and the second power processing unit For calculating the second power of the second subsampled signal, the calculation unit is used for calculating the power energy difference between the first power and the second power, so as to output the clock error signal to the clock adjustment circuit.

In a possible design, the clock phase detection unit further includes a first filtering unit, and the first filtering unit is configured to filter out an in-band spectral component of the clock signal to be recovered. Based on such a design, the high-pass filter unit can suppress noise and improve the robustness of the phase detection signal.

In a possible design, the clock recovery circuit further includes a second filtering unit, the second filtering unit is connected to the calculation unit, and the second filtering unit is configured to filter the time error signal, In order to obtain the time error signal after filtering. Based on such a design, the out-of-band noise can be suppressed, and the stability of the loop can be improved, so that the clock recovery circuit can meet certain occasions with high performance requirements.

In a possible design, the clock adjustment circuit is further configured to receive the filtered time error signal, and adjust the frequency of the first sampling clock according to the filtered time error signal. Based on such a design, the voltage-controlled oscillation unit can continuously reduce the time error, and can quickly complete the synchronization between the local clock of the receiver and the clock of the transmitter.

In a second aspect, embodiments of the present application further provide a communication device, where the communication device includes the clock recovery circuit as described above.

The clock recovery circuit and communication device provided in the embodiments of the present application can extract a clock signal from a received signal, complete clock phase detection, and drive the clock recovery circuit to realize clock recovery. The clock recovery circuit of the embodiment of the present application does not depend on the signal eye diagram, is applicable to various modulation modes, and can perform clock recovery before channel equalization of the receiver.

Description of drawings

FIG. 1 is a schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 2 is a schematic diagram of a clock phase detection unit provided by an embodiment of the present application.

FIG. 3 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

Fig. 4a is a signal spectrum diagram of a baseband signal according to an embodiment of the present application.

Fig. 4b is a frequency response diagram of the high-pass filter unit of the embodiment of the present application.

FIG. 5 is a spectrum diagram of a signal filtered by a high-pass filter unit according to an embodiment of the present application.

FIG. 6 is a frequency spectrum diagram of an undersampled signal according to an embodiment of the present application.

FIG. 7 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 8 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 9 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 10 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 11 is a schematic diagram of processing a sampling clock by a clock combination unit provided in an embodiment of the present application.

FIG. 12 is another schematic diagram of a clock recovery circuit provided by an embodiment of the present application.

FIG. 13 is a schematic structural diagram of a communication device provided by an embodiment of the present application.

Description of main component symbols

clock recovery circuit	100
communication device	200
sampling circuit	10
Envelope Detection Unit	12
sample and hold unit	14, 70
clock phase detection unit	20
High-pass filter unit	twenty two
first processing unit	twenty four
processing module	25
second processing unit	26
serial-to-parallel conversion unit	27
computing unit	28
clock combiner unit	29
loop filter unit	30
clock adjustment circuit	40
VCO	41
The first crossover unit	42
second crossover unit	43
first clock delay unit	44
second clock delay unit	45
The third crossover unit	46
delay unit	47
demodulation unit	50
power detection unit	51
Mixing unit	60
first power processing unit	80
Second Power Processing Unit	82

The following specific embodiments will further describe the present application in detail in conjunction with the above-mentioned drawings.

Detailed ways

It should be noted that when an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be an intervening element at the same time. When an element is referred to as being "disposed on" another element, it can be directly disposed on the other element or intervening elements may also be present.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of the application are only for the purpose of describing specific embodiments, and are not intended to limit the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In order to facilitate the understanding of the clock recovery circuit provided in the embodiment of the present application, the application scenarios of the clock recovery circuit in the embodiment of the present application are described below. The clock recovery circuit can be applied to communication equipment, and the clock recovery circuit can be used to complete the synchronization between the local clock of the receiver and the clock of the transmitter.

In a possible scenario, a clock recovery circuit can detect the time error between the local clock and the sending clock by comparing the position deviation between the sampling position and the receiving eye diagram edge or eye diagram apex, so as to drive the phase-locked loop to work, thereby Recover the clock. The clock recovery circuit in the above scenario is very dependent on the eye diagram of the received signal. However, for a non-amplitude modulation communication system, if the received signal does not include a simple eye diagram, the clock recovery circuit will fail. When there is intersymbol interference in the transmission channel, the received signal of the amplitude modulation communication system needs to undergo channel equalization to recover the eye diagram. At this time, an equalization module needs to be added to the clock recovery circuit, which will increase the delay of the loop, thereby reducing loop stability and clock tracking capability.

In another possible scenario, in a receiver using a quadrature mixing architecture, a local clock of 2 times the signal baud rate is generated through a phase-locked loop to oversample the received I/Q signal, thereby Two sampling points can be obtained from each signal. Since the time interval between two sampling points is half a symbol period, when the sampling clock is synchronized with the sending clock, the two sampling points can collect the stable peak point and transition point of the transmission signal at the same time, using the transition point and peak point The characteristics of the statistical distribution can detect the statistical error when the sampling position deviates, which corresponds to the time error between the sampling clock and the sending clock. Clock recovery can thus be achieved by means of this time error. The clock recovery method in the above scenario requires the receiver to sample the received signal at twice the symbol rate. However, in a transmission system with a high baud rate, the generation of twice the sampling clock will bring huge power consumption and complexity.

Based on this, the embodiments of the present application provide a clock recovery circuit and communication equipment, which can realize clock recovery for signals of various modulation formats, and the clock recovery circuit can not depend on the eye pattern quality of the signal , and clock recovery can be implemented at the front end of the receiver, and the system has high stability and robustness.

Please refer to FIG. 1 , which is a schematic block diagram of a clock recovery circuit 100 provided by an embodiment of the present application.

The clock recovery circuit 100 in the embodiment of the present application may be applied to a receiver. It can be understood that the receiver and the transmitter may constitute a communication system. The transmitter can send a signal driven by a local clock (such as a high-speed clock), and the receiver can receive the signal, and can extract the clock signal of the transmitter from the received signal through the clock recovery circuit 100, and then The local clock signal can be adjusted according to the extracted clock signal of the transmitter, thereby completing the synchronization of the local clock of the receiver and the clock of the transmitter.

In one embodiment, the clock recovery circuit 100 may include a sampling circuit 10 , a clock phase detection unit 20 , a loop filter unit 30 and a clock adjustment circuit 40 . The sampling circuit 10 may be electrically connected to the clock phase detection unit 20 and the clock adjustment circuit 40, the clock phase detection unit 20 may be electrically connected to the loop filter unit 30, and the loop filter unit 30 It can be electrically connected to the clock adjustment circuit 40 .

It can be understood that the sampling circuit 10 in this embodiment can sample the received signal of the receiver according to the local clock signal, and can output the sampled signal to the clock phase detection unit 20 .

The clock phase detection unit 20 can estimate the time error between the sampling clock and the sending clock from the clock signal to be recovered, and output a time error signal to the loop filter unit 30 .

The loop filtering unit 30 can filter the time error signal. The clock adjustment circuit 40 can adjust the filtered sampling clock so that the time error keeps getting smaller, thereby completing clock recovery and realizing normal communication reception.

Please refer to FIG. 2 . FIG. 2 is a schematic structural diagram of a clock phase detection unit 20 provided by an embodiment of the present application.

It can be understood that the clock phase detection unit 20 in this embodiment may include a high-pass filter unit 22 , a first processing unit 24 , a second processing unit 26 and a calculation unit 28 . The first processing unit 24 may be configured to sample an input signal and output a sampled signal. The second processing unit 26 can be used to sample the input signal and output the sampled signal. The high-pass filter unit 22 can be electrically connected to the sampling circuit 10, the first processing unit 24 is electrically connected between the high-pass filter unit 22 and the computing unit 28, and the second processing unit 26 is electrically connected to Between the high-pass filter unit 22 and the calculation unit 28 , the calculation unit 28 is electrically connected to the loop filter unit 30 . It can be understood that, in an embodiment, the calculation unit 28 may be a calculation unit or a comparator, which is not limited in this application. It can be understood that, in a possible implementation manner, the first processing unit 24 and the second processing unit 26 may be implemented by using the same device or circuit. In a possible implementation manner, both the first processing unit 24 and the second processing unit 26 may include a sample-and-hold unit.

In this embodiment, the high-pass filter unit 22 may be used to filter out the in-band spectral components of the sampled signal, where the spectral components refer to the amplitude of a frequency in the frequency domain after transformation. The spectrum can reflect the distribution of signal amplitude and phase with frequency, which describes the characteristics of the signal in the frequency domain. The first processing unit 24 can perform under-sampling on the filtered signal by a specific ratio through the sampling clock of the first phase, and output the first under-sampling signal to the calculation unit 28, and the second processing unit 26 can pass the first phase The two-phase sampling clock under-samples the filtered signal at a specific ratio, and outputs a second under-sampled signal to the calculation unit 28 . The calculation unit 28 calculates the energy difference or amplitude difference of the two signals, and the energy difference is the time error. It can be understood that the difference between the first phase and the second phase may represent a time difference between the sampling clock of the first processing unit 24 and the sampling clock of the second processing unit 26 .

It can be understood that, in an embodiment, the sampling phases of the first under-sampled signal and the second under-sampled signal are different, and the different sampling phases may represent different sampling positions.

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of a clock recovery circuit 100 provided by an embodiment of the present application.

In this embodiment, the sampling circuit 10 may include an envelope detection unit 12 and a sample-and-hold unit 14 . Specifically, the transmitter sends an amplitude modulation signal to the receiver driven by a local clock. The envelope detection unit 12 can demodulate the received modulated signal to obtain a baseband signal. It can be understood that the sample and hold unit 14 may sample the baseband signal to obtain a restored and reconstructed transmission signal.

The envelope detection unit 12 can output a baseband signal to the high-pass filter unit 22, and the high-pass filter unit 22 filters the baseband signal, and the output signal passes through the first processing unit 24 and the second processing unit After 26 samples, two undersampled signals are obtained. Since the two under-sampled signals are unipolar signals (such as positive or negative signals), the approximate calculation of the energy difference can be realized by passing the two under-sampled signals through a subtractor. Therefore, the two under-sampled signals are passed through the After the calculation by the calculation unit 28, the approximate calculation of the energy difference or amplitude difference of the two signals can be realized, and the output of the calculation unit 28 is a clock error signal. The calculation unit 28 outputs the clock error signal to the clock adjustment circuit 40 .

In a possible implementation manner, the clock adjustment circuit 40 may include a voltage-controlled oscillation unit 41 , a first frequency division unit 42 , a second frequency division unit 43 , and a first clock delay unit 44 .

In this embodiment, the voltage-controlled oscillation unit 41 may be electrically connected to the loop filter unit 30, and the first frequency dividing unit 42 is electrically connected to the voltage-controlled oscillation unit 41 and the first processing unit 24 Between, the second frequency division unit 43 is electrically connected between the second processing unit 26 and the first clock delay unit 44 . The first clock delay unit 44 is electrically connected to the voltage-controlled oscillation unit 41 . The sample-and-hold unit 14 may also be electrically connected to the first clock delay unit 44 and the voltage-controlled oscillation unit 41 . It can be understood that, in a possible implementation manner, the first clock delay unit 44 may be a shift register or a digital buffer unit.

In the specific implementation process of the present application, the loop filter unit 30 may filter the time error signal output by the clock phase detector unit 20, and transmit the filtered signal to the voltage-controlled oscillation unit 41, In this way, the out-of-band noise can be suppressed, and the stability of the loop can be improved, so that the clock recovery circuit 100 can meet certain occasions with high performance requirements. In a possible implementation manner, the loop filtering unit 30 may be any one of a first-order filter, a second-order filter, or a high-order filter, which is not limited in this application.

The voltage-controlled oscillation unit 41 can generate a clock signal according to the received time error signal, and can adjust the frequency of the clock signal under the control of the input signal. Based on such a design, the clock error signal output by the clock phase detector unit 20 can be sequentially processed by the loop filter unit 30 and the voltage-controlled oscillation unit 41 to output a clock signal with a symbol rate of M/N times, M >N. It can be understood that the clock signal can drive the sample and hold unit 14 to perform normal signal sampling.

It can be understood that, in a possible implementation manner, the clock signal of the voltage-controlled oscillation unit 41 may also be output to the first frequency division unit 42 and the first clock delay unit 44 . Specifically, the first frequency division unit 42 receives the clock signal output by the voltage-controlled oscillation unit 41 , and the clock signal can obtain the first under-sampling clock after passing through the first frequency division unit 42 times 1/M.

The clock signal output by the voltage-controlled oscillating unit 41 can be delayed by L beats by the first clock delay unit 44, and then passed by the second frequency division unit 43 of 1/M times, so as to generate a second under-sampling clock. It can be understood that the signals of the first under-sampling clock and the second under-sampling clock can be used to drive the first processing unit 24 and the second processing unit 26 in the clock phase detection unit 20 respectively.

FIG. 4 a shows a signal spectrum diagram of the baseband signal, and FIG. 4 b shows a frequency response diagram of the high-pass filter unit 22 . It can be understood that the high-pass filtering unit 22 can filter the baseband signal. The bandwidth of the baseband signal may be (1+α)×B.

Among them, B is the symbol baud rate, α is the roll-off coefficient, and α<1. It can be seen from FIG. 4a and FIG. 4b that in this embodiment, the optimal high-pass cut-off frequency of the high-pass filter unit 22 is fc=(1-α)/2×B. The narrower the transition band of the high-pass filter unit 22, the better.

FIG. 5 is a spectrum diagram of the signal filtered by the high-pass filter unit 22 . It can be seen that the filtered signal only contains the spectrum of the sidebands and roll-off regions on both sides.

When there is a clock delay of length τ between the sampling signal and the clock of the sending signal, according to the characteristics of Fourier transform, the frequency spectrum of the sampling signal can be equivalent to superimposing a linear phase difference τf on the phase-frequency response of the sending signal , that is, the spectrum R(f) of the received signal can satisfy the following formula (1):

R(f)＝S(f)e ^i2πτf (1)

Wherein S(f) is the spectrum of the transmitted signal, based on the periodicity of the spectrum of the transmitted signal outside the sidebands, S(f) has the same frequency spectrum near the sidebands f=±B/2 on both sides, that is, S(-B /2)=S(B/2).

It can be understood that in a scenario, if a specific undersampling is performed on the spectrum R(f) of the received signal, an undersampled signal with an integer multiple of the period of the transmitted symbol can be obtained, and the spectrum S(f) of the received signal will be Aliasing will occur. Since the period of this subsampling is an integer multiple of the symbol period, the frequency spectrum near both sidebands f=±B/2 will be superimposed near the same frequency point during aliasing, and the aliased frequency spectrum can satisfy the following formula ( 2):

Wherein, f0 represents the original sideband frequency point f=±B/2 at the frequency point position after aliasing, because the frequency spectrum D after aliasing has a cosine component related to τ, when τ=0, the formula ( 2) The amplitude of D can reach the maximum value. Therefore, the magnitude value of D can have the ability to detect time errors.

If the clock period of the undersampling is 4 times of the clock period of the transmitted signal, the frequency spectrum of the sampled signal will be aliased by 4 times.

As shown in FIG. 6 , the aliased frequency spectrum may be formed by the superposition of the g1 part, the g2 part, the g3 part and the g4 part. The g1 part, g2 part, g3 part and g4 respectively correspond to four sub-spectrum segments of the signal spectrum before undersampling. It can be understood that the part g3 and the part g4 are the roll-off regions of the two sidebands respectively. The aliasing spectrum D in the roll-off region may have the ability to detect clock errors, so the g3 part and the g4 part may be useful signals for identifying clock errors. The g1 and g2 parts are located in the in-band interval of the original signal spectrum. Because of the randomness of their spectrum content, they cannot be used to identify clock errors after aliasing, and the detection of clock errors is a noise item. Based on this, in order to improve the signal-to-noise ratio of the detection time error, the embodiment of the present application can suppress the in-band spectral components through the high-pass filter unit 22 before under-sampling, thereby greatly improving the signal-to-noise ratio of the useful signal after under-sampling. Noise ratio and accuracy of time error detection.

For example, the roll-off factor may be α=0.2, and the sampling clock CLKc may be 1.25 times the symbol baud rate, that is, M/N=5/4. The sampling clock CLKc may be a clock signal recovered by the voltage-controlled oscillation unit 41 . If the sampling clock CLKc generated by the clock recovery circuit 100 needs to be kept at the M/N=5/4 multiple of the sending clock, the clock phase detection unit 20 needs to filter the signal of the high-pass filter unit 22 according to the aliasing spectrum D The detection principle carries out the detection of the clock error.

It can be understood that, in this embodiment, the first frequency division unit 42 can generate the under-sampling clock CLKa according to the sampling clock CLKc output by the voltage-controlled oscillation unit 41 . The first clock delay unit 44 receives the sampling clock CLKc output by the voltage-controlled oscillation unit 41 and delays the sampling clock CLKc. The second frequency dividing unit 43 can generate the under-sampling clock CLKb according to the delayed sampling clock CLKc of the voltage-controlled oscillation unit.

In some scenarios, the period of the under-sampling clock can be an integer multiple of the symbol period, and both the first frequency division unit 42 and the second frequency division unit 43 can be 1/M frequency division, such as 1/5 Frequency division unit.

In the embodiment of the present application, the clocks generated by the first frequency division unit 42 and the second frequency division unit 43 are used to drive the first processing unit 24 and the second processing unit 26 to process the signal filtered by the high-pass filter unit 22 During under-sampling, the period of the under-sampling clock may be N times (for example, 4 times) the period of the sending clock. Therefore, the spectrum of the sampled signal will be aliased by a factor of 4.

In a possible implementation manner, when the first frequency division unit 42 divides the sampling clock CLKc to generate the undersampling clock CLKa, it generates one beat of the undersampling clock CLKa every M sampling clocks CLKc, and continuously M beats Any beat of the sampling clock CLKc can be used as the start clock beat of the undersampling clock CLKa. Therefore, the first frequency division unit 42 and the second frequency division unit 43 may have M different frequency division time differences during frequency division.

It can be understood that, in a possible implementation, for the sampling clock CLKc with M/N times oversampling, if the time error between the first beat sampling clock CLKc and the sending clock is τ, then M different frequency division time differences τ _i satisfies the following formula (3):

τ _i =τ+mod(i·N/M, 1)T, i=0, 1, . . . , M-1 (3)

Wherein, T=1/B, and T is the symbol period of the transmitted signal. In this embodiment, M=5, N=4, so the five different frequency division time differences are τ ₀ =τ, τ ₁ =τ+0.8T, τ ₂ =τ+0.6T, τ ₃ =τ+0.4 T, τ ₄ =τ+0.2T.

It can be understood that the clock recovery circuit 100 of the embodiment of the present application can generate two undersampling clocks CLKa and CLKb with different frequency division time differences through the first clock delay unit and two frequency division units. Wherein, the frequency division time difference of the undersampling clock CLKb can be recorded as τb, and the frequency division time difference of the undersampling clock CLKa is recorded as τa. In this embodiment, the frequency division time difference τb of the undersampling clock CLKb is greater than the The frequency division time difference τa of the undersampling clock CLKa delays the sampling clock CLKc by L beats, and 1<L<M. It can be understood that, as mentioned above, under the condition of 1/M frequency division, the undersampling clock can have M different starting sampling phases. Therefore, the effect of L≥M can be the same as that in the range of 1<L<M The effect of the application is the same, and the scope of the effect of this application can still be entered.

It can be understood that, when the sampling clock CLKc is delayed by L beats, there is a time difference between the frequency division time difference τb and the frequency division time difference τa, and the time difference may be τ _b −τ _a =βT.

It can be seen from formula (3) that β=L·N/M.

In a possible implementation manner, the first clock delay unit 44 may include L latches. It can be understood that, in some other possible implementation manners, the first clock delay unit 44 may also include a shift register, a delay line, a state machine, and the like. This application is not limited to this.

It can be understood that, in some possible implementation manners, the first processing unit 24 may sample the signal filtered by the high-pass filter unit 22 under the drive of the under-sampling clock CLKa, where the aliasing spectrum D _a can satisfy the following formula (4):

It can be understood that, in some possible implementation manners, the second processing unit 26 may sample the signal filtered by the high-pass filter unit 22 under the drive of the under-sampling clock CLKb, where the aliasing spectrum D _b can satisfy the following formula (5):

Thus, the phase detection error Err of the clock phase detection unit 20 can be obtained from the difference of D _a and D _b , that is, the phase detection error Err can satisfy the following formula (6):

As can be seen from the above formula (6), if the phase detection error Err is used to drive the clock recovery circuit to complete locking, the phase detection error Err can remain at 0, that is, the undersampling clock CLKa can be locked to a stable The frequency division time difference

In addition, if there is a certain frequency division time difference among the M frequency division time differences τ _i of the sampling clock CLKc

Then τj=0, then the sampling clock CLKc can achieve locking and recovery of the sending clock at M/N times.

It can be understood that, in this embodiment, since the signal input to the clock phase detection unit 20 passes through the envelope detection unit 12, that is, the amplitude of the baseband signal is a positive number. The spectral energy of the positive signal may be directly proportional to the signal amplitude. In this embodiment of the present application, an undersampled signal is used to replace its spectrum energy D to perform difference calculation, thereby realizing time error detection.

In a possible implementation manner, the first clock delay unit 44 may include one latch, that is, L=1, at this time, β=0.8, and the frequency division time difference of the undersampling clock CLKa is τ _a =-0.4T, there is a frequency division time difference τ _j =τ _a +0.4T=0 in the sampling clock CLKc, therefore, the under-sampling clock CLKc achieves 1.25 times the recovery of the sending clock. It can be understood that in another possible implementation, the subtractor used in the above formula (6) can also be replaced by a comparator, and the phase detection error Err can satisfy the following formula (7):

Err＝Sign{D _a (f _o ，τ _a )-D _b (f _o ，τ _b )} (7)

Wherein, if a>0, Sign{a}=1; if a<0, Sign{a}=-1; if a=0, Sign{a}=0.

It can be understood that from the above formula (7), it can be obtained that when D _a is greater than D _b , then the phase detection error Err is equal to 1; when D _a is less than D _b , then the phase detection error Err is equal to -1; When D _a is equal to D _b , the phase detection error Err is equal to zero.

Using the clock recovery circuit of the embodiment of the present application, the clock signal can be extracted from the received signal, and the clock phase detection can be completed. When the sampling clock is M/N times of the sending clock, the time error can be detected only by satisfying M>N , and drive the clock recovery circuit to achieve clock recovery. The embodiments of the present application do not depend on signal eye diagrams, are applicable to various modulation modes, and can perform clock recovery before channel equalization of the receiver.

Please refer to FIG. 7 , which is a schematic structural diagram of a clock recovery circuit 100 provided in another embodiment of the present application.

The difference from the clock recovery circuit 100 shown in FIG. 3 is that, as shown in FIG. 7 , the clock recovery circuit 100 in this embodiment may further include a second clock delay unit 45 and a third frequency division unit 46 .

In this embodiment, the second clock delay unit 45 may be electrically connected to the voltage-controlled oscillation unit 41 and the first clock delay unit 44, and the third frequency division unit 46 may be electrically connected to the second The clock delay unit 45 and the sample and hold unit 14 .

It can be understood that the third frequency division unit 46 can receive the sampling clock CLKc, and can be used to generate a sampling clock CLKd locked at the same frequency as the sending clock. In a possible implementation, the third frequency division unit 46 may be an N/M frequency division unit, that is, the third frequency division unit 46 may be a 1/M frequency division unit connected in series with an N-multiple frequency device.

In order to realize a clock in phase with the sending clock, the sampling clock CLKd output by the third frequency division unit 46 needs to have no non-integer symbol period time error with the sending clock. Therefore, in the embodiment of the present application, before the third frequency division unit 46 performs N/M frequency conversion on the sampling clock CLKc, a second clock delay unit 45 with a length of H may be added, and the second clock delay unit 45 may A clock signal with a time difference of τ _d from the sending clock is obtained. It can be understood that H may be the number of beats of clock delay by the second clock delay unit 45 .

In this embodiment, the time difference is τ _a can be locked to a fixed deviation determined by L

Thus the second delayer 45 can delay H, that is, a fixed deviation can be generated between the time difference τ _d and the time difference τ _a

Right now

That is, the non-integer symbol period time difference between the sampling clock CLKd and the sending clock can be eliminated, and then the clocks can be in phase. It can be understood that in one scenario, when half of the time error between the sampling clock CLKb generated by L and the sampling clock CLKa can be offset by the time error between the sampling clock CLKd generated by H and the sampling clock CLKa, Then the offset time error is 0 or may be an integer multiple of the period of the sending clock. In another scenario, you can choose L=1, and make β=0.8, choose H=3, and make τ _d -τ _a =0.4T. At this time, the sampling clock CLKd can be in phase with the sending clock, and the time error is 0.

In another possible implementation, when the receiver has no in-phase constraint on the phase between the sampling clock CLKd and the sending clock, or when

τ _d may also be 0, and at this time, there may be no second clock delay unit 45 between the third frequency division unit 46 and the voltage-controlled oscillation unit 41 .

Please refer to FIG. 8 , which is a schematic structural diagram of a clock recovery circuit 100 provided in another embodiment of the present application.

The difference from the clock recovery circuit 100 shown in FIG. 3 is that, as shown in FIG. 8 , the clock recovery circuit 100 in this embodiment may further include a demodulation unit 50 and a power detection unit 51 .

In this embodiment, the demodulation unit 50 is electrically connected to the sample-and-hold unit 14 , and the power detection unit 51 is electrically connected between the demodulation unit 50 and the high-pass filter unit 22 .

The demodulation unit 50 is used to demodulate the received high-frequency modulation signal, and the demodulated baseband signal can be driven by the recovered sampling clock and sampled by the sample-and-hold unit 14 to obtain a clock-reconstructed signal. sample signal.

The power detection unit 51 is used to obtain the instantaneous power of the baseband signal corresponding to the high-frequency modulation signal, and perform clock recovery through the instantaneous power signal. Optionally, the power detection unit 51 may be a circuit or device such as a self-mixer, an envelope detection unit, or a photodiode. Based on such a design, the power detection unit 51 can directly obtain the baseband power of the modulated signal.

Please refer to FIG. 9 , which is a schematic structural diagram of a clock recovery circuit 100 provided in another embodiment of the present application.

The clock recovery circuit 100 in this embodiment may include a frequency mixing unit 60 , a sample and hold unit 70 , a clock phase detector unit 20 , a loop filter unit 30 and a voltage-controlled oscillation unit 41 .

The frequency mixing unit 60 may be electrically connected to the sample and hold unit 70, the sample and hold unit 70 is electrically connected to the clock phase detection unit 20, and the clock phase detection unit 20 is connected to the loop filter unit 30 , the voltage-controlled oscillation unit 41 is electrically connected between the sample-and-hold unit 70 and the loop filter unit 30 .

In this embodiment, the frequency mixing unit 60 may be used to receive a high-frequency modulation signal, and may demodulate the received high-frequency modulation signal into a baseband signal. The frequency mixing unit 60 can also transmit the baseband signal to the sample and hold unit 70 . It can be understood that, in a possible implementation manner, the frequency mixing unit 60 may be an I/Q mixer.

The sample and hold unit 70 can be used to receive the baseband signal output by the frequency mixing unit 60, and to sample and hold the baseband signal according to the sampling clock CLKc, so as to output an oversampled signal to the clock phase detection unit 20.

In this embodiment, the clock phase detection unit 20 may include a high-pass filter unit 22, a delay unit 47, a first processing unit 24, a second processing unit 26, a first power processing unit 80, a second power processing unit 82 and a calculation Unit 28.

The high-pass filtering unit 22 is electrically connected to the sample-and-hold unit 70, the first processing unit 24 and the delay unit 47, the first processing unit 24 is electrically connected to the first power processing unit 80, and the delay The unit 47 is electrically connected to the second processing unit 26, the second power processing unit is electrically connected to the second processing unit 26 and the computing unit 28, and the first power processing unit 80 is electrically connected to the Calculation unit 28.

The high-pass filtering unit 22 can be used to perform high-pass filtering on the oversampled signal. In one embodiment, the high-pass filtering unit 22 may be any one of an analog filter, a finite-length unit impulse response (Finite Impulse Response, FIR) filter, or a digital filter.

The first processing unit 24 may extract one output from every M signals of the oversampled signals filtered and output by the high-pass filter unit 22 to obtain a first undersampled signal.

The delay unit 47 is used to delay the oversampled signal. It can be understood that, in a possible implementation manner, the delay unit 47 may be a shift register or a digital buffer unit.

The second processing unit 26 is configured to extract an output from every M signals in the input oversampled signals to obtain a second undersampled signal.

The first power processing unit 80 is used for calculating the power of the first subsampled signal.

The second power processing unit 82 is used for calculating the power of the second subsampled signal.

In this embodiment, the calculation unit 28 may be used to calculate the difference between two powers and energy, so as to output a clock error signal to the loop filter unit 30 .

Please refer to FIG. 10 , which is a schematic structural diagram of a clock recovery circuit 100 provided in another embodiment of the present application.

As shown in FIG. 10 , the clock phase detection unit 20 in this embodiment includes a high-pass filter unit 22 , a processing module 25 , a serial-to-parallel conversion unit 27 , a calculation unit 28 and a clock combining unit 29 .

The processing module 25 is electrically connected between the high-pass filter unit 22 and the serial-to-parallel conversion unit 27, and the clock combining unit 29 is electrically connected between the clock adjustment circuit 40 and the processing module 25, The serial-to-parallel conversion unit 27 is electrically connected to the computing unit 28 .

The difference from the clock recovery circuit 100 shown in FIG. 3 is that, as shown in FIG. 10 , in this embodiment, the first processing unit 24 and the second processing unit 26 can be implemented by using the same device or circuit. The processing module 25 in this embodiment may include a sample and hold unit. The processing module 25 can process the clock signal to be recovered to output two under-sampled signals with different sampling phases.

Specifically, the clock combining unit 29 is electrically connected to the first frequency dividing unit 42 and the second frequency dividing unit 43 . The first frequency dividing unit 42 and the second frequency dividing unit 43 respectively output the under-sampling clock CLKa and the under-sampling clock CLKb to the clock combining unit 29 . The clock combining unit 29 outputs a sampling clock CLKe to the processing module 25 to drive the processing module 25 to perform signal sampling. Therefore, the processing module 25 can sample the signal output by the high-pass filter unit 22 under the drive of a 2/N times sampling clock CLKe to obtain a sampling signal. The sampling signal can be input to the serial-to-parallel conversion unit 27 , and the serial-to-parallel conversion unit 27 can output two under-sampled signals in parallel to the calculation unit 28 .

Wherein, the serial-to-parallel conversion unit 27 can process two continuously input signals, and output the two signals in parallel from two output ports respectively. It can be understood that, in a possible implementation manner, the serial-to-parallel conversion unit 27 may be implemented by using two alternately working latches. In another possible implementation manner, the serial-to-parallel conversion unit 27 may also be implemented by using a buffer with a depth of 2.

It can be understood that, in this embodiment, the under-sampling clock CLKa and the under-sampling clock CLKb are two clock signals with different phases. As shown in FIG. 11 , the under-sampling clock CLKa and the under-sampling clock CLKb have different level transition positions within one cycle, and the clock combining unit 29 combines the two clocks to obtain a sampling clock CLKe. Wherein, the sampling clock CLKe includes level transition positions of two clocks simultaneously in one cycle, and the clock frequency of the sampling clock CLKe is twice that of the under-sampling clock CLKa and the under-sampling clock CLKb.

In a possible implementation manner, the clock combining unit 29 may be implemented by using a signal combiner or an adder.

It can be understood that, in this embodiment, the two signals output in parallel by the serial-to-parallel conversion unit 27 may be equivalent to signals obtained by sampling driven by the under-sampling clock CLKa and the under-sampling clock CLKb. Therefore, the effect of the clock phase detection unit 20 in this embodiment is the same as that of the clock phase detection unit 20 in the embodiment in FIG. 3 .

Please refer to FIG. 12 , which is a schematic structural diagram of a clock recovery circuit 100 provided in another embodiment of the present application.

The difference from the clock recovery circuit 100 shown in FIG. 9 is that, as shown in FIG. A processing unit 80 , a second power processing unit 82 and a computing unit 28 .

The high-pass filter unit 22 is electrically connected to the sample-and-hold unit 70 and the processing module 25, and the serial-to-parallel conversion unit 27 is electrically connected to the first power processing unit 80 and the second power processing unit 82, and the The serial-to-parallel conversion unit 27 is also electrically connected to the processing module 25 , and the first power processing unit 80 and the second power processing unit 82 are electrically connected to the computing unit 28 .

In this embodiment, the high-pass filtering unit 22 may be configured to perform high-pass filtering on the oversampled signal. In one embodiment, the high-pass filtering unit 22 may be any one of an analog filter, a finite-length unit impulse response (Finite Impulse Response, FIR) filter, or a digital filter.

The processing module 25 may decimate the oversampled signal filtered and output by the high-pass filter unit 22, and output an undersampled signal. In this embodiment, the processing module 25 may extract two out of every M signals in the received oversampled signals. It can be understood that two different extraction positions of the oversampled signal by the signal extraction unit correspond to two different undersampling phases.

The output of the processing module 25 can be processed by a 1:2 serial-to-parallel conversion unit 27, and the serial-to-parallel conversion unit 27 can output two parallel undersampling signals to the first power processing unit 80 and the second power processing unit 80 respectively. The processing unit 82 , that is, the serial-to-parallel conversion unit 27 may output the first under-sampling signal and the second under-sampling signal to the first power processing unit 80 and the second power processing unit 82 respectively. Wherein, the first under-sampling signal and the second under-sampling signal output by the processing module 25 have different phases. It can be understood that, in a possible implementation manner, the serial-to-parallel conversion unit 27 may be implemented by using two alternately working latches. In another possible implementation manner, the serial-to-parallel conversion unit 27 may also be implemented by using a buffer with a depth of 2.

The first power processing unit 80 is used for calculating the power of the first subsampled signal.

The second power processing unit 82 is used for calculating the power of the second subsampled signal.

In this embodiment, the calculation unit 28 may be used to calculate the difference between two powers and energy, so as to output a clock error signal to the loop filter unit 30 .

Please refer to FIG. 13. The embodiment of the present application also provides a communication device 200. As shown in FIG. the required clock signal. Clocks can be synchronized by the action of the clock recovery circuit 100 .

The above is only a preferred implementation mode of the application, and is not intended to limit the application in any form. Although the application is a preferred implementation mode disclosed above, it is not intended to limit the application. Any skilled person familiar with this field , without departing from the scope of the technical solution of the present application, when the technical content disclosed above can be used to make some changes or be modified into equivalent implementations with equivalent changes, but as long as it does not depart from the technical solution of the present application, according to the technical content of the present application In essence, any simple modification, equivalent change and modification made to the above embodiments still fall within the scope of the technical solution of the present application.

Claims (16)

1. A clock recovery circuit, characterized in that the clock recovery circuit comprises:

   A clock phase detection unit, the clock phase detection unit includes a processing module and a calculation unit; the processing module is used to process the clock signal to be recovered, so as to output the first sub-sampling signal and the second sub-sampling signal with different sampling phases signal; the calculation unit is used to estimate the time error signal of the first sampling clock according to the energy difference or amplitude difference between the first subsampling signal and the second subsampling signal;

   A clock adjustment circuit, configured to adjust the first sampling clock according to the time error signal.
2. The clock recovery circuit according to claim 1, wherein the processing module comprises a first processing unit and a second processing unit, and the first processing unit is used to perform signal processing on the clock signal to be recovered to output the first An under-sampled signal; the second processing unit is used to perform signal processing on the clock signal to be recovered to output a second under-sampled signal, the sampling of the first under-sampled signal and the second under-sampled signal The phases are different.
3. The clock recovery circuit according to claim 2, wherein the first processing unit is configured to perform under-sampling on the clock signal to be recovered by using the second sampling clock of the first phase, and output a first under-sampling signal , the second processing unit is configured to perform under-sampling on the clock signal to be recovered by using the third sampling clock of the second phase, and output a second under-sampling signal, and the calculation unit is configured to perform according to the first under-sampling The difference in energy or magnitude of the signal and said second undersampled signal estimates a time error signal of said first sampling clock.
4. The clock recovery circuit according to claim 3, wherein the clock adjustment circuit is further configured to divide the frequency of the first sampling clock to generate a second sampling clock for the first processing unit, the The clock adjustment circuit is further configured to delay the first sampling clock, and divide the delayed first sampling clock to generate the third sampling clock, so as to output the third sampling clock to the second processing unit.
5. The clock recovery circuit according to any one of claims 2-4, wherein the clock recovery circuit further comprises a demodulation unit, the demodulation unit is electrically connected to the first sample and hold unit, and the demodulation unit It is used to demodulate the received signal, and the demodulated baseband signal is sampled by the first sample and hold unit to obtain a clock-reconstructed sampling signal.
6. The clock recovery circuit according to claim 5, wherein the clock recovery circuit further comprises a power detection unit, the power detection unit is used to obtain the power amplitude of the baseband signal, and perform clock recovery through the power amplitude .
7. The clock recovery circuit according to claim 2, wherein the clock recovery circuit further comprises a first sample and hold unit, and the clock phase discrimination unit further comprises a delay unit, and the first sample and hold unit is used for receiving baseband signal, and sample and hold the baseband signal according to the first sampling clock to output an oversampled signal to the clock phase detection unit, and the first processing unit is used to extract a plurality of the oversampled signals One output, to output the first under-sampling signal; the delay unit is used to delay the over-sampling signal, and transmit the delayed over-sampling signal to the second processing unit; the first The second processing unit is used to extract an output from the delayed oversampled signals to output the second undersampled signal.
8. The clock recovery circuit according to any one of claims 2-7, wherein the clock phase detection unit further includes a first power processing unit and a second power processing unit, and the first power processing unit is electrically connected to The first processing unit, the second power processing unit are electrically connected to the second processing unit, the first power processing unit is used to calculate the first power of the first sub-sampled signal, the second The power processing unit is used to calculate the second power of the second subsampled signal.
9. The clock recovery circuit according to claim 8, wherein the calculation unit is connected to the first power processing unit and the second power processing unit, and the calculation unit is used to calculate the first power and The power energy difference between the second powers is used to output the clock error signal to the clock adjustment circuit.
10. The clock recovery circuit according to claim 1, wherein the clock phase detection unit further comprises a clock combination unit and a serial-to-parallel conversion unit, and the clock combination unit is used to output the fourth sampling clock to the processing module, the processing module is used to under-sample the clock signal to be recovered by using the fourth sampling clock, so as to output the first under-sampling signal and the second under-sampling signal to the serial-to-parallel conversion A unit, the serial-to-parallel conversion unit is used to output the first under-sampled signal and the second under-sampled signal to the calculation unit in parallel.
11. The clock recovery circuit according to claim 1, wherein the clock recovery circuit further comprises a first sampling and holding unit, and the clock phase detection unit further comprises a serial-to-parallel conversion unit, and the first sampling and holding unit is used for Receive a baseband signal, and be used to sample and hold the baseband signal through the first sampling clock, so as to output an oversampled signal to the clock phase detection unit; the processing module is used to process a plurality of the oversampled signals Two outputs are extracted to output the first under-sampled signal and the second under-sampled signal with different sampling phases to the serial-to-parallel conversion unit.
12. The clock recovery circuit according to claim 11, wherein the clock phase detection unit further includes a first power processing unit and a second power processing unit, and the serial-to-parallel conversion unit is used to convert the first subsampled The signal and the second subsampled signal are output to the first power processing unit and the second power processing unit in parallel, and the first power processing unit is used to calculate the first power of the first subsampled signal, The second power processing unit is used to calculate the second power of the second sub-sampled signal, and the calculation unit is used to calculate the power energy difference between the first power and the second power to output the The clock error signal is sent to the clock adjustment circuit.
13. The clock recovery circuit according to any one of claims 1-12, wherein the clock phase detection unit further comprises a first filter unit, and the first filter unit is used to filter out the clock signal to be recovered The in-band spectral components of .
14. The clock recovery circuit according to any one of claims 1-13, characterized in that, the clock recovery circuit further comprises a second filter unit connected to the computing unit, and the second filter unit The unit is used for filtering the time error signal to obtain a filtered time error signal.
15. The clock recovery circuit according to claim 14, wherein the clock adjustment circuit is further configured to receive the filtered time error signal, and adjust the first The frequency of the sampling clock.
16. A communication device, characterized in that the communication device comprises the clock recovery circuit according to any one of claims 1-15.

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