JPS63285019A - Modulation noise preventing circuit - Google Patents

Abstract

PURPOSE:To decrease the fluctuation in the time axis direction by providing a synchronizing circuit receiving a digital signal to be converted, to the pre-stage of a digital/analog converter (DAC) to supply a clock signal whose time axis fluctuation is suppressed to the synchronizing circuit, thereby synchronizing the digital signal to be converted, with the clock signal. CONSTITUTION:A master clock signal from a crystal oscillator 2 is frequency- divided by a signal processing circuit 3 to generate a sampling pulse to extract a desired channel data from a timing signal and plural channel data, and a sampled signal being the result of sampling the input digital signal by a sampling pulse and the timing signal are fed to the synchronizing circuit 5. Moreover, the master clock signal outputted from the crystal oscillator 2 is fed to the synchronizing circuit and the sampled signal and the timing signal are synchronized by using the master clock at the synchronizing circuit 5. Thus, the signal fed to the DAC 1 is synchronized by the synchronizing circuit 5 and the time axis fluctuation of the analog signal converted by the DAC 1 is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a digital audio disc playback device, a PC
The present invention relates to a modulation noise prevention circuit for converting analog signals into C, which is used in M processors, digital audio tape recorders, etc.

(Prior Art) In a conventional circuit of this kind, as shown in FIG. 3, for example, a master clock signal from a crystal oscillator 2 is frequency-divided by a signal processing circuit 3 to generate a sampling pulse and a timing signal, and the input digital signal is The signal sampled by the sampling pulse and the timing signal are supplied to a digital/analog converter (hereinafter referred to as DAC) 1 and converted into an analog signal.

In addition, as shown in Fig. 4, the PL from the input digital signal
A clock signal is regenerated by the L circuit 4, the regenerated clock signal is used as a master clock signal, input digital data is processed by the mask clock signal, and the processed digital signal is converted into an analog signal by the DAC 1. It is configured.

(Problem to be Solved by the Invention) In the former case of the conventional example, the timing signal in the signal processing circuit is supplied to the DAC 1 as a conversion timing signal, and due to fluctuations in the time axis of the timing signal, the DAC
There was a problem in that the analog signal converted by No. 1 also had the same time axis fluctuation.

Further, the latter conventional example also had the same problems as described above.

An object of the present invention is to solve the above problems and provide a modulation noise prevention circuit that reduces fluctuations in the time axis direction.

(Means for Achieving the Object) In order to solve the above problems, the present invention is constructed as follows.

The present invention provides a synchronization circuit to which the digital signal to be converted is supplied before the r-, y digital/analog converter, and supplies a clock signal with suppressed time axis fluctuation to the synchronization circuit to clock the digital signal to be converted. I tried to synchronize with the signal.

(Operation) Therefore, the digital signal to be converted is synchronized by a clock signal whose time axis fluctuation is suppressed in the synchronization circuit, and the synchronized digital signal to be converted is supplied to the DAC and converted into an analog signal. Therefore, the time axis variation of the digital signal supplied to the DAC is small, the time axis variation of the analog signal output from the DAC is suppressed, and modulation noise is prevented.

(Example) The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

The first embodiment of the present invention is a sun glyph for extracting desired channel data from a timing signal and multiple channel data by frequency-dividing a master clock signal from a crystal oscillator 2 by a signal processing circuit 3.
It generates a sampling pulse (simply referred to as a sampling pulse), and supplies the input digital signal with a sampling pulse and a timing signal to the synchronization circuit 5, and also supplies the master clock signal output from the crystal oscillator 2 to the synchronization circuit 5. However, in the synchronization circuit 5, the Sunsilt signal and the timing signal are synchronized by a master clock signal.

The Sunsilt signal and timing signal output from the synchronization circuit 5 are supplied to the DAC 1 and converted into analog signals.

However, since the signals supplied to the DAC 1 are synchronized by the master clock signal in the synchronization circuit 5, this time-base fluctuation is also suppressed in the analog signal converted by the DAC 1.

Therefore, for example, when the input digital signal is a two-channel signal, there is a clock signal and a channel identification signal as a sampling pulse for identifying the digital data of one channel and the digital data of the other channel. The signal is a signal obtained by dividing the master clock signal. Therefore, the time axes of digital data, clock signals, and identification signals vary due to time axis fluctuations caused by the signal processing circuit 3, but this time axis fluctuation is synchronized by the master clock pulse signal in the synchronization circuit 5, and this fluctuation is suppressed.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention.

In the second embodiment of the present invention, an input digital signal is supplied to a PLL circuit 4 to reproduce a clock signal from the input digital signal, and the clock signal reproduced by the PLL circuit 4 and the input digital signal are supplied to a signal processing circuit 3. Then, the reproduced clock signal is frequency-divided to generate a sampling pulse and a timing signal, and a sunsilt signal obtained by sampling the input digital signal using a sampling pulse and a timing signal are supplied to a synchronization circuit.

On the other hand, the reproduced clock signal output from the PLL circuit 4 is supplied to the PLL circuit 6. Here, the PLL circuit 4 is set to have a wide band so as to be able to reproduce the clock signal from the input digital signal, thereby improving followability. Furthermore, the PLL circuit 6 is set to have a narrow band so that even if jitter exists in the reproduced clock signal due to the input clock signal, the jitter component is removed.

The Sunsilt signal and timing signal output from the signal processing circuit 3 are synchronized in the synchronization circuit 5 by the clock signal output from the PLL circuit 6. The sampled signal and timing signal output from the synchronization circuit 5 are supplied to the DAC 1 and converted into analog signals.

However, since the signal supplied to the DAC 1 is synchronized in the synchronization circuit 5 with the clock signal from which the book is removed in the PLL circuit 6, the time axis fluctuation of the converted analog signal output from the DAC 1 is suppressed.

(Effects of the Invention) As explained above, according to the present invention, the dizotal data supplied to the DAC is synchronized with a stable clock signal and then supplied to the DAC, so that the time axis of the analog signal converted by the DAC is Fluctuations will be suppressed and modulation noise will be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention. FIG. 3 and FIG. 4 are block diagrams showing the configuration of a conventional example. 1... DAC12... Crystal oscillator, 3... Signal processing circuit, 4 and 6... PLL, 5... Synchronous circuit.

Claims (1)

[Claims] A synchronization circuit to which the digital signal to be converted is supplied is provided before the digital/analog converter, and a clock signal with suppressed time axis fluctuation is supplied to the synchronization circuit to synchronize the digital signal to be converted with the clock signal. This modulation noise prevention circuit is characterized by: