JP2913634B2 - Synchronization adjustment device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization adjustment device used for dubbing digital audio tapes or the like recorded in different formats. [Summary of the Invention] The present invention relates to a synchronization adjustment device, and by performing conversion of a frame synchronization signal using a plurality of PLLs, it is possible to perform good dubbing even on tapes recorded in different formats. It is to be. 2. Description of the Related Art In a so-called professional digital audio tape, since a VTR is used as a recording / reproducing device, various formats exist according to a television standard system in each country. That is, 25Hz, 30Hz as frame synchronization frequency
And the sampling frequency s of the audio signal has a format of 48 kHz, 44.1 kHz, 44.056 kHz, or the like. On the other hand, so-called time codes are used in the editing of signals using such a commercial VTR, and the time codes also have a time code clock frequency t of 2 kHz or 2.4 kHz in accordance with the format of the above-mentioned signals. , 2.39
There are various formats such as 76kHz. However, in editing or the like, it is necessary to edit the above-mentioned different formats and dub them to a VTR of an arbitrary format. Conventionally, in dubbing between such different formats, a tape recorded in an arbitrary format is converted to the frame frequency of the VTR to be dubbed using a so-called frame number conversion device to create a secondary tape. Thereafter, dubbing has been performed while performing data conversion using the secondary tape. However, in such a method, it takes time to prepare the secondary tape, and the number of dubbing increases, so that the occurrence of errors increases and the signal may deteriorate. [Problems to be Solved by the Invention] As described above, in the related art, when dubbing a tape having a different format, a long processing time is required, and the possibility of signal deterioration is increased. There was a problem. [Means for Solving the Problems] The present invention relates to a synchronization adjustment device for performing synchronization adjustment between a reproducing device and a recording device having different formats, and receives a reference frame synchronization signal (terminal (1)). A first PLL for forming a desired sampling signal (output terminal (4))
A circuit (2), a second PLL circuit (6) that receives an output of the first PLL circuit, and outputs (terminal (8)) a timing signal corresponding to a recording time code of the recording device; Upon receiving a playback frame synchronization signal separated (circuit (10)) from a playback time code (input terminal (9)) obtained from the device, the playback frame synchronization signal is converted into a target time code and the recording time code (input A third conversion is performed so that the signal has the same frequency as the recording frame synchronization signal separated (circuit (15)) from the terminal (14).
And a phase comparing means (13) for comparing the phase of the output of the third PLL circuit with the recording frame synchronization signal separated from the target time code. Speed control (output terminal (16)) between the reproducing apparatus and the recording apparatus using the output signal of the recording apparatus, and the reproduction time code from the reproducing apparatus is converted into the format of the recording apparatus using the timing signal. This is a synchronization adjusting device that converts (circuit (17)) to recording time code (output terminal (18)). [Operation] According to this, since the format can be converted arbitrarily, speed control between different formats can be performed, and thereby dubbing between tapes having different formats can be performed well. [Embodiment] In the figure, (1) is an input terminal to which a reference frame synchronization signal is supplied, and this input terminal (1) is a first terminal.
It is connected to a first input of a phase comparison circuit (2a) constituting the PLL (2). The output of this comparator (2a) is VCXO (2b)
And the output of this VCXO (2b) is connected to the second input of the comparison circuit (2a) through a 1 / a divider circuit (2c) and a 1 / b divider circuit (2d). You. VCXO (2b)
Is connected to the output terminal (4) of the sampling clock through a 1/100 frequency divider (3). Further, a phase comparator (6a) constituting a second PLL (6) through a frequency divider (5) whose output of the frequency divider (2c) is 1 / c.
Connected to a first input of The output of the comparator (6a) is connected to the control input of the VCXO (6b), and the output of the VCXO (6b) is connected to the second input of the comparator (6a) through a 1 / d frequency divider (6c). Connected. Furthermore, the output of VCXO (6b) is 1 /
e is connected to the output terminal (8) of the time code clock through the frequency dividing circuit (7). Further, an input terminal (9) to which a playback time code is supplied from a playback device for a signal to be dubbed is connected to a time code reading circuit (10), and an output of the separated frame synchronization signal is supplied to a third PLL ( 11) is connected to the first input of the phase comparison circuit (11a). This comparison circuit (1
The output of 1a) is connected to the control input of VCO (11b) and this VC
The output of O (11b) is connected to the second input of the comparison circuit (11a) through the 1 / n frequency dividing circuit (11c). In addition, VCO (11
The output of b) is connected to a first input of a phase control circuit (13) for speed control through a 1 / m frequency dividing circuit (12). An input terminal (14) to which a target time code is supplied from the recording device is connected to a time code reading circuit (15), and an output of the separated frame synchronization signal is supplied to a second input of a comparison circuit (13). Connected to. The output of the comparison circuit (13) is connected to the output terminal (16) of the speed control signal. Further, the output of the time code of the reading circuit (10) is connected to the time code conversion circuit (17), and the output of the frequency dividing circuit (7) is connected to the conversion circuit (17). ) Output is the recording time code output terminal (1
8) Connected to. In this device, when the frequency of the reference frame active period signal supplied to the input terminal (1) is 25 Hz,
Frequency division ratios a, b, of the frequency divider circuits (2c) (2d) (5) (6c) (7)
By setting c, d, and e as shown in Table I below, sampling clocks and time code clocks of desired frequencies s and t are output to output terminals (4) and (8), respectively. When the frequency of the reference frame synchronization signal is 29.97 Hz, clock signals s and t can be obtained similarly as shown in Table II. Further, when the frequency of the reference frame synchronization signal is 30 Hz, clock signals s and t can be obtained similarly as shown in Table III. As a result, sampling clocks and time code clocks of desired frequencies s and t can be obtained for the respective reference frame synchronization signal frequencies. If the frame frequencies of the time codes supplied to the input terminals (9) and (14) are different from each other in combination as shown on the left side of Table IV, the dividing ratio n of the dividing circuits (11c) and (12) is n. , m are determined as shown on the right. As a result, the frame synchronization signal of the reproduction time code can be converted into the frequency of the frame synchronization signal of the target time code, and the speed can be controlled by comparing the phases. When the frequencies of the frame synchronization signals match, it is assumed that the PLL (11) does not operate and the signal is passed as it is. The time code from the readout circuit (10) is supplied to the conversion circuit (17), and the conversion circuit (17) is supplied with the time code clock from the frequency dividing circuit (7), so that the reproduced signal is reproduced. Is converted at the timing of the time code of the recording device and is taken out to the output terminal (18). Therefore, in this apparatus, speed control is performed between tapes of different formats, and the time code is converted and supplied to the recording apparatus. In this way, speed control between different formats is performed, and dubbing can be performed in this state. However, according to the above-described apparatus, it is not necessary to create a secondary tape or the like, so that processing is quickly transmitted, and There is no risk of signal deterioration or the like due to this. [Effects of the Invention] According to the present invention, since the format can be arbitrarily converted, speed control between different formats can be performed, whereby dubbing between tapes having different formats can be performed well. I can do it.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an example of the present invention. (1) (9) (14) are input terminals, (2) (6) (11)
PLL, (3) (5) (7) (12) is frequency divider, (4)
(8), (16) and (18) are output terminals, (10) and (15) are time code reading circuits, (13) is a phase comparison circuit, and (17) is a time code conversion circuit.

Claims (1)

(57) [Claims] A synchronization adjustment device for adjusting synchronization between a reproducing device and a recording device having different formats, a first PLL circuit to which a reference frame synchronization signal is input to form a desired sampling signal, and the first PLL circuit And outputs a timing signal corresponding to the recording time code of the recording apparatus
A PLL circuit, receiving a playback frame synchronization signal separated from the playback time code obtained from the playback device, and receiving the playback frame synchronization signal from the recording time code of the recording device as a target time code. A third PLL circuit for converting the signal into a signal having a frequency equal to the following, and phase comparing means for comparing the phase of the output of the third PLL circuit with the recording frame synchronization signal separated from the target time code. The speed control of the reproducing apparatus and the recording apparatus is performed by using an output signal of the phase comparing means, and a reproduction time code from the reproducing apparatus is converted into a format of the recording apparatus by using the timing signal. Synchronization adjustment device that converts to recording time code.