JPS60204192A - Signal processor - Google Patents

Abstract

PURPOSE:To output a stable picture by writing sequentially an input signal to each set of memory devices at each synchronizing signal and reading sequentially an output signal from other set not in the write state at each synchronizing signal repetitively. CONSTITUTION:A time division multiplex signal TC formed by applying time compression to color difference signals R-Y, B-Y and a luminance signal Y given from an input terminal 71 and arranging them in time division is extracted by a synchronizing separator section 7 and multiplied by the 1st phase control group 1. In the control group 1, an LPF12 is set so that the output frequency of a voltage controlled oscillator 13 follows in response to jitter of the synchronizing signal of the input. On the other hand, the synchronizing signal is inputted to the 2nd phase control group 2 and a counter 52 generates a read address 521. The control group 2 does not respond to the jitter of the inputted synchronizing signal and an LPF22 is set so as to follow the frequency deviation and drift. Thus, even if jitter is included in the input signal, it does not appear in the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device that can be used in video tape recorders, television broadcast transmitting devices, and the like.

Conventional configuration and its problems In recent years, instead of a composite video signal, three component signals, a luminance signal (Y) and a color difference signal (RY, B-Y), are time-division multiplexed and transmitted or recorded and reproduced. This is an attempt to improve image quality.

For example, as shown in Fig. 1, the R-Y, B-Y, and Y signals are time-compressed, converted into time-division multiplexed signals TC (hereinafter referred to as TC signals) arranged in a time-division manner, and then transmitted or transmitted. After recording and playing, conversely perform time expansion,
Three video signals are obtained.

A conventional signal processing device will be described below with reference to the drawings. Figure 2 shows the T
Convert to C signal or convert TC signal to R-Y, B-Y,
This is a circuit configuration diagram of a signal processing device that performs inverse conversion into each signal of Y. In the former case, there are three systems on the input side, and the signals are output in parallel to a memory device one time at a time and serially output. In the latter case, there are three output systems, and the data is written to the memory serially for one hour and output in parallel. Therefore, since both have the same configuration as shown in FIG. 2, the case where the TC signal is inversely converted will be explained. In FIG. 2, 71 is an input terminal, and 72 is an output terminal.

A synchronization separator 7 extracts only a synchronization signal from the input TC signal, which is added to the phase control loop 1 and multiplied. The sample clock frequencies of the Y signal and TC signal are m
-aJH, n-a-fH (mekodashi, fH is the frequency of the synchronization signal, m/n is the time compression ratio, ma, n, a is the number of samples between the synchronization signals), the voltage of phase control loop 1 The output frequency of the controlled oscillator (hereinafter referred to as VCO) 13 is:
The frequency division ratio of the frequency divider 14 is set to 1/(m·n'a) so that the common multiple m'n·a−fH is obtained. Therefore, the phase control loop 1 compares the phases of the synchronization signal and the output of the frequency divider 14, and the output of the phase detector (PD) 11, that is, the phase difference voltage, passes through the low-pass filter (hereinafter referred to as LpF) 12, and
It is added to the CO 13 to form a phase control loop, and operates so that the phase difference between the synchronizing signal and the output of the 1/(mn-a) frequency divider 14 becomes zero. As a result, the output frequency of vC013 becomes m-n-a"fH. This output is 1
The sample clock frequency n-a-fH of the TC signal is obtained by the 7m frequency divider 81, and 1/(
n-a) Counter (hereinafter referred to as writing counter) 6
1 to generate a write address 511 for the first memory device 31 and the second memory device 32.

On the other hand, the output of the VCO 13 is also applied to a 1/n frequency divider 82, and similarly, a 1/(m-a) counter for reading (hereinafter referred to as
A read counter (referred to as a read counter) 52 generates a read address 521 for the Y signal. Write counter 61. The read counter 52 is reset by a synchronization signal.

In addition, the input TC signal is A/D (analog/digital)
The signal is converted into a digital signal by the converter 61 at a sample clock frequency of "" fH, and is input to the first memory device 31 or the second memory device 32.

Input, output, and respective addresses of these memory devices.

For clock signals etc., selector switches 41, 42゜43
．． Furthermore, since this is connected to the output of the 1/2 frequency divider 91, and a synchronization signal is applied to the 1/2 frequency divider 91, these switching is performed every synchronization signal. It will be held in This operation will be further explained using FIG. In the same figure, a is the TC signal, and the attached number (
1"', "2") d indicates a memory device that can be written to. Also, ml and m2 in the same figure indicate write (W) and read (R) of the first and second memory devices, respectively.
It shows the status of. bil-1 in the same figure: RY, B-
Y or Y signal with attached numbers (1", 2")
indicates the memory device to be read.

First, changeover switches 41, 42, 43 as shown in FIG.
In the state 44, the A/D converted TC signal is being written to the first memory device 31, and being read from the second memory device 32. every sync signal.

This operation is alternated, resulting in a timing diagram as shown in FIG.

The A/D converter 61 and writing are performed at a clock frequency of n-a-fH and are sequentially written to each memory in each memory device, and the D/A (digital/analog) converter 62 and reading is performed at a clock frequency of m-a-, fH, is read out in parallel from each memory in each memory device, and is D/A converted to obtain each output signal of R-Y, BY, and Y. .

In this way, in conventional signal processing devices, the write and read operations of the memory device are switched simultaneously for each synchronization signal of the input signal. When a signal containing jitter with a relatively high frequency component or drift with a relatively low frequency component is input, there is a problem in that the jitter and drift appear as they are in the output signal. The jitter component is particularly problematic because it makes the boundaries of one image "jagged" and degrades the image quality.

OBJECTS OF THE INVENTION An object of the present invention is to provide a signal processing device in which jitter components on the input side do not appear on the output side.

Composition of the Invention The signal processing device of the present invention includes first and second phase control routers receiving a synchronization signal separated from an input signal, and a plurality of sets of memory devices, and a first phase control loop. The output of the second phase control loop is a write clock signal for writing the input signal to the memory device, the output of the second phase control loop is a read clock signal for reading the output signal from the memory device, and the output of the second phase control loop is a read clock signal for reading the output signal from the memory device. every period of the synchronization signal.

Writing is performed by sequentially changing the sets of memory devices to be written using the write clock signal, and the output signal from the other sets that are not in the write state is changed from one set to another every cycle of the synchronization signal, and the set is changed using the read clock signal. The LpFO cutoff frequency of the first phase control loop is set higher than that of the second phase control loop to increase the response speed, and the LpFO cutoff frequency of the first phase control loop is made higher than that of the second phase control loop. The output of the first phase control loop follows the jitter of the input signal, and the output of the second phase control loop does not follow the jitter, so that the jitter component on the input side does not appear on the output side. It is.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram of an embodiment of the present invention.

In FIG. 4, the same components as those in the conventional example shown in FIG. 2 are denoted by the same reference numerals, and redundant explanation thereof will be omitted. 2 is an added phase control loop, which will be referred to as the second phase control loop, and the 10 phase control loop will be referred to as the first phase control loop.

92 is a timing control section, 53 is a decoding section, and the third
Memory device 33 and its changeover switches 45 and 46
has been added.

The operation of the signal processing device of this embodiment configured as described above will now be described. First, from the input TC signal input from the input terminal 71, only the synchronization signal is extracted by the synchronization separator 7, and is added to the first phase control loop 1, where it is multiplied. Same as the conventional example.

When the sample clock frequencies of the Y signal and the TC signal are m-a-fH and na-a-fH, respectively, the first ■C01
Different from the conventional example, the output frequency of No. 3 is fH, which is the sample clock frequency of the TC signal, and the write address 511 is generated from the write counter 51. 1st
The phase control loop 1 determines the constant of the first LpF 12 so that the output frequency of the first vCO 13 quickly follows the jitter of the input synchronization signal.

On the other hand, the synchronization signal is also input to the second phase control loop 2,
The output frequency of the second VCO 23 becomes the read clock frequency m-a-fH of the Y signal, and the read counter 62 generates a read address 521. Further, this readout counter 62 also serves as a frequency divider for the second phase control loop 2. The operation of the second phase control loop 2 determines the constant of the second LPF 22 so as not to respond to the jitter of the input synchronizing signal, but to follow the frequency deviation and drift.

As a result, the cutoff frequency of glLpF is
It will be higher than that of F22. Still read address 52
By applying phase control to the output of the decoding section 63 that detects a predetermined address from 1, a phase difference is created between the input signal and the output signal, thereby increasing the margin for the jitter width.

Furthermore, the timing control unit 92 controls the changeover switches 41, 42, 43, 44, 46, and 46 to sequentially select the memory device to write to and the memory device to read from.

Changeover switch 41, 42, 43゜44.45 in Fig. 4
．． In the state 46, the input signal is being written to the first memory device 31 and being read from the second memory device 32. Then, for each synchronization signal of the input signal, changeover switches 41 and 43
．． 45 are sequentially switched, and changeover switches 42, 44, and 46 are switched every time the output signal is synchronized.

The above operations are performed using FIGS. 5 and 6.

I will explain further. 6 and 6 show the timing of FIG. A in the figure is the input TC signal, and the numbers (1'', ``2'', ``3'') indicate the memory device to be written into.

m2. and m3 are first memory devices, respectively.

Writing of the second memory device and the third memory device (W)
, readout (R) operation, and b in the figure shows R-Y, B-Y
, or a Y signal, with the attached numbers (171, 11
2'', ``3'') indicate the memory device to be read.

Figure 5 shows the steady state, where writing and reading to the memory device are synchronized with the input signal, and the first phase control loop 1
is in phase with the input signal, and the second phase control loop 2
is a state in which the signals are synchronized at a predetermined phase difference from the input signal.

FIG. 6 shows a state in which the input signal contains jitter, and shows the moment when the input signal fluctuates in the direction in which the period of the synchronization signal becomes shorter. At this time, the first phase control loop 1 immediately follows the input signal.

However, the second phase control loop 2 does not follow immediately.

Therefore, the writing and reading timings are different. As can be seen from this figure, the jitter component on the input side does not appear in the output signal. Well, the second phase control loop 2 is also slow, but it follows the input signal, so the state shown in Figure 6 does not last long.
Eventually, the state will become as shown in Figure 5.

Effects of the Invention As is clear from the above description, the present invention has first and second phase control loops, a plurality of sets of memory devices,
The output of the first phase control loop is used as a write clock signal to the memory device to track the jitter of the input signal; jitter, write the input signal sequentially to each set of memory devices for each synchronization signal, and repeat the operation of sequentially reading the output signal from the other sets that are not in the write state for each synchronization signal. With this configuration, an excellent effect can be obtained in that the jitter component of the input signal does not appear in the output signal. Due to this effect, stable images can be obtained.

[Brief explanation of the drawing]

Fig. 1 is an example of the R-Y, B-Y, and Y signals and a signal waveform diagram for time-division multiplexing them, Fig. 2 is a circuit configuration diagram of a conventional signal processing device, and Fig. 3 is a diagram of the signal waveforms obtained by time-division multiplexing them. FIG. 4 is a circuit configuration diagram of an embodiment of the present invention, and FIGS. 5 and 6 are timing diagrams of FIG. 4. 1...First phase control loop, 7...Synchronization separation unit, 11...First phase detector, 12...
...10th pass filter, 13...1st voltage controlled oscillator, 15...1/(n-a) frequency divider,
2...Second phase control loop, 21...Second
Phase detector, 22...20th pass filter,
23...Second voltage controlled oscillator, 31...
First memory device, 32...Second memory device, 3
3... Third memory device, 51... 1/(n--) counter for writing, 62... 1/(m·a) counter for reading, 53... . . . Decoding unit, timing control unit for 92 . Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 31.4 Figure 4

Claims (2)

[Claims] (1) The first input signal is a synchronization signal separated from the input signal.
and a second phase control loop, and a plurality of sets of memory devices, and the output of the first phase control loop is a write clock signal for writing the input signal to the memory device, and a second phase control loop is provided. The output of the phase control loop is a read clock signal for reading an output signal from the memory device, and the set of memory devices to be written to is sequentially changed by the write clock signal every cycle of the synchronization signal of the input signal. A signal characterized in that the output signal is changed from another group that is not in a writing state to another group every cycle of the synchronization signal, and the operation of reading out the output signal using the read clock signal is repeated. Processing equipment. (2) The cutoff frequency of the low-pass filter included in the first phase control loop is higher than the cutoff frequency of the low-pass filter included in the second phase control loop. The signal processing device described in (1).