JPS60213191A - Signal processor - Google Patents

Abstract

PURPOSE:To prevent appearance of jitter component of input side in output side by making a write clock signal to a memory follow the jitter of an input signal and making a read clock signal not respond to the jitter. CONSTITUTION:A synchronizing signal is taken out from an input TC signal entered from an input terminal 71 and applied to the first and second phase control loops 1, 2. In the loop 1, the output frequency follows quickly responding to the jitter of the synchronizing signal of input, and write address 511 is generated from a counter 51 for writing. The loop 2 does not respond to the jitter, but follows frequency deviation and drift and generates address 521. Changeover switches 41-46 are controlled by a timing control section 92 and the input signal is written in memories 31-33 and read out from memories which are not in writing state, and this operation is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device that can be used in video tape recorders, television broadcast transmitting devices, and the like.

Conventional configuration and its problems In recent years, instead of a composite video signal, three component signals, a luminance signal (Y) and a color difference signal (RY, B-Y), are time-division multiplexed and transmitted or recorded and reproduced. This is an attempt to improve image quality.

For example, as shown in Figure 1, the R-Y, B-Y, and Y signals are time-compressed and converted into a time-division multiplexed signal TC (hereinafter referred to as a TO-multiplied signal) arranged in a time-division manner, and then transmitted or transmitted. After recording and reproducing, conversely time expansion is performed to obtain three video signals.O Hereinafter, a conventional signal processing device will be described with reference to the drawings. Figure 2 shows the T
Convert to C signal or convert TO signal to R-Y, B-Y,
It is a circuit configuration diagram of a signal processing device that performs inverse conversion into each signal of Y. In the former case, there are three systems on the input side, which are written in parallel in time to a memory device and output in series. In the latter case, there are three systems on the output side, and data is written to the memory serially in time and output in parallel. Therefore, since both have the same configuration as shown in FIG. 2, the case where the TC signal is inversely converted will be explained. In FIG. 2, 71 is an input terminal, and 72 is an output terminal.

From the input TCi signal, only the synchronization signal is extracted by the synchronization separator 7, and is added to the phase control loop 1, where it is multiplied. The Y signal and TO double signal sample clock frequencies are respectively met fH, n-as fH (where fH is the frequency of the synchronization signal, m/n is the time compression ratio, ma, n,
If a is the number of samples between synchronization signals, phase control loop 1
The output frequency of the voltage controlled oscillator (hereinafter referred to as vOC) 13 is determined by changing the division ratio of the frequency divider 14 to 1/(m,n-a
). Therefore, the phase control loop 1 compares the phases of the synchronization signal and the output of the frequency divider 14, and the output of the phase detector (PD) 11, that is, the phase difference voltage, is filtered by a low-pass filter (hereinafter referred to as
(referred to as LPF) 12 and is added to VCOl 3,
A phase control loop is constructed, and the synchronization signal and 1/(m・n−a
) It operates so that the phase difference with the output of the frequency divider 14 is zero. As a result, the output frequency of VCOl 3 is m*
n - a m fH. This output is determined by the 17m frequency divider 81VC at the sample clock frequency n of the TC signal.
*h −fH is obtained, and in addition, 1/(n
-λ) counter (hereinafter referred to as writing counter) 61
is added to generate a write address 611 for the first memory device 31 and the second memory device 32.

On the other hand, the output 1d of the VCOl3 is also added to the 1/n frequency divider 82, and similarly, the readout 1/(m-a) counter (hereinafter referred to as readout counter) 52 generates the readout address 621 of the Y signal. do. In addition, a write counter 61. The read counter 62 is reset by the synchronization signal.

In addition, the input TO multiplied signal A/D (converted to a digital signal at a sample clock frequency of n-a-fH by an analog/digital converter 61,
Alternatively, it is input to the second memory device 32. Inputs, outputs, addresses, clock signals, etc. of these memory devices are controlled by changeover switches 41, 42, 43, 44, which are further connected to the output of the 1/2 frequency divider 91. Since a synchronizing signal is applied to the 1/2 frequency divider 91, these switching operations are performed for each synchronizing signal. This operation will be further explained using FIG. In the same figure, there is a[TO double signal, the attached numbers (#11, r2#
) indicates the memory device to be written to. In addition, ml and m2 in the same figure are the first memory device and the second memory device, respectively.
It shows the write (W) and read (R) states of the memory device. b in the figure is the R-Y, B-Y, or Viy signal, and the appended numbers (j) 11 and I 2 indicate the memory devices to be read.

First, select the changeover switch 41°42.43 as shown in Figure 2.
．． In the state 44, the TO multiplied signal obtained by human/D conversion is written into the first memory device 31, and the second memory device 32 is read out. This operation is alternated every synchronous signal month, resulting in a timing diagram as shown in FIG. 3.

A, /D converter 61 and writing are no & -fH
Writing is performed serially and sequentially to each memory in each memory device at a clock frequency of m-a·fH, and reading from the D/A (digital/analog) converter 62 is performed at a clock frequency of m-a·fH. They are read out in parallel from each memory in each memory device, are D/A converted, and R-Y, B-Y,
Obtain each output signal of If a signal containing jitter with a relatively high frequency component or drift with a relatively low frequency component is input as a time axis error, the output signal will contain that jitter or drift. There was a problem that I was too lazy to show up. The jitter component is particularly problematic because it makes the boundaries of the image 'jagged' and degrades the image quality.

OBJECT OF THE INVENTION An object of the present invention is to provide a signal processing device in which jitter components on the input side do not appear on the output side. the first and second phase control loops, a plurality of sets of memory devices, and a synchronization signal adding section provided on the output side of the memory devices, and for each of the synchronization signals, the set of memory devices is is sequentially changed, the input signal is written every output pulse of the first phase control loop only during a predetermined time interval shorter than the period of the synchronization signal, and the synchronization signal is written from another set of memory devices that are not in the write state. The device is configured to repeat the operation of reading out the output signal for each output pulse of the second phase control loop only during a predetermined time interval shorter than the period, and furthermore, the LP of the first phase control loop is
The cutoff frequency of F is set higher than that of the second phase control loop to increase the response speed, so that the output of the first phase control loop follows the jitter of the input signal, and the output of the second phase control loop follows the jitter of the input signal. This is to prevent jitter components from appearing on the output side by not following jitter. Furthermore, by reading out a predetermined time interval portion of the output signal whose period is the synchronous signal month from the memory device,
The operating time rate of the memory device is lowered, the margin for jitter width is increased, and even two sets of memory devices can be configured. .

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 4 is a circuit diagram of an embodiment of the present invention.

In FIG. 4, the same components as those in the conventional example shown in FIG. 2 are denoted by the same reference numerals, and redundant explanation thereof will be omitted. 2 is an added phase control loop, which will be referred to as a second phase control loop, and the phase control loop 1 will be referred to as a first phase control loop.

92 is a timing control section, 63 is a decoding section, and the third
Memory device 33 and its changeover switches 45 and 46
has been added. Note that 63 indicates the memory devices 31 and 32.
．． 33, that is, the input side of the D/A converter 62.

The operation of the signal processing device of this embodiment configured as described above will be described below. First, from the large sword TO signal inputted from the input terminal 71, only the synchronization signal is taken out by the synchronization separation section 7, which is then outputted to the first phase control loop 1Fi and multiplied. As in the conventional example, the Y signal and TO multiplied signal sample clock frequencies are each m*! L @ fH,n
In the case of o a # fH (7), the output frequency of the first VCOl 3 is n・a−fH, which is different from the conventional example, which is T
A write address 611 is generated from the write color/receiver 51 at O times the signal sample frequency. The constant of the first LPF 12 is determined so that the output frequency of the first vC013 quickly follows the jitter of the input synchronization signal of the first phase control loop 1Fi.

On the other hand, the synchronization signal is also input to the second phase control loop 2,
The output frequency of the second vC023 is the read clock frequency m-a*fH (!-) of the Y signal, and the read counter 6
2, a read address 621 is generated. Further, this read counter 52 also serves as a frequency divider for the second phase control loop 2. The constant of the second LPF 22 is determined so that the operation of the second phase control loop 2 does not respond to the jitter of the input synchronizing signal and follows the frequency deviation and drift (K). As a result, the cutoff frequency of the first LPF becomes lower than that of the second LPF.
It is higher than that of LPF22. Further, by applying phase control to the output of the decoding section 53 that detects a predetermined address from the read addresses 621, a phase difference is created between the input signal and the output signal, and a margin for the jitter width is increased.

Further, the timing control section 92 controls the changeover switches 41, 42, 43, 44, 45.degree. 46 so as to sequentially select the memory device for writing and the memory device for reading.

Furthermore, since a predetermined section of the output signal is detected from the read address 521 and only that section is read out from the memory device, a synchronization signal or the like is added to the other sections by the synchronization signal adding section 63.

Changeover switch 41, 42, 43゜44.45 in Fig. 4
．． In state 46, the input signal is being written to the first memory device 31 and read from the second memory device 32. Then, for each synchronization signal of the input signal, a changeover switch 41, 43
．． 45 are sequentially switched, and changeover switches 42, 44, and 46 are switched every time the output signal is synchronized.

The above operation will be further explained using FIGS. 5 and 6. 5 and 6 show the timing of FIG. 4. In the same figure, the &ke input TO times signal, the attached number (
'11, #2#, lsl) indicates a memory device that is written on the first page. In addition, ml, m2, and m3 in the same figure are the first memory device, the second memory device, and the third memory device, respectively.
Indicates write (W) and read (R) operations of the memory device,
b in the figure is the R-Y, B-Y, or Y signal, and the appended numbers (11#, ?2#, I31) indicate the memory devices to be read.

FIG. 6 shows a steady state in which writing and reading to and from the memory device are synchronized with the input signal, the first phase control loop 1 is in phase with the input signal, and the second phase control loop 2V is in phase with the input signal.
This is a state in which they are synchronized at a predetermined phase difference from the i input signal.

FIG. 6 shows a state in which the input signal contains jitter, and shows the moment when the input signal fluctuates in the direction in which the period of the synchronization signal becomes shorter. At this time, the first phase control loop 1 immediately follows the input signal.

However, the second phase control loop 2 does not follow immediately.

Therefore, the writing and reading timings are different. As can be seen from this figure, the jitter component on the input side does not appear in the output signal. In addition, the second phase control loop 2 also follows the input signal, although it is slow, so the state shown in Fig. 6 does not last long.
Eventually, the state will become as shown in Figure 5.

FIG. 7 shows another embodiment of the invention. The embodiment is the same as the embodiment shown in FIG. 4 except that there are two sets of memory devices. 8th
9 and 9 are timing diagrams of FIG. 7, which correspond to FIGS. 6 and 6, where FIG. 8 is in a steady state, and FIG. It shows the moment when it swayed in the direction of becoming shorter. Since the output signal is read only in a predetermined time interval, there is a margin between writing and reading even if there are two sets of memory devices, and for signals with small jitter width, three or more sets of memory devices are required. The same operation as used is possible. Therefore, there are 2 memory devices.
Even if the input signal is a pair, the jitter component of the input signal does not appear in the output.

Effects of the Invention As is clear from the above description, the present invention includes first and second phase control loops, a plurality of memory devices, and a synchronization signal adding section, and the first phase control loop output is the output of the second phase control loop is used for a read clock signal from the memory device and is not responsive to jitter in the input signal; The structure is such that the input signal is sequentially written to each set of memory devices for each synchronous signal, and the operation of sequentially reading out the output signal from other sets that are not in the write state for each synchronous signal is repeated. An excellent effect is obtained in that the jitter component does not appear in the output signal. Due to this effect, stable images can be obtained.

Furthermore, since the output signal is read out during a predetermined time interval of the period of the synchronization signal, the operation can be performed even with two sets of memory devices, and the same effect can be obtained.

[Brief explanation of the drawing]

Fig. 1 shows an example of the R-Y, B-Y, and Y signals and a signal waveform diagram of time-division multiplexed signals, Fig. 2 is a circuit configuration diagram of a conventional signal processing device, and Fig. 3 is the same as that of Fig. 2. 4 is a timing diagram of one embodiment of the present invention; FIGS. 6 and 6 are timing diagrams of FIG. 4; FIG. 7 is a circuit diagram of another embodiment of the present invention; 8 and 9 are timing diagrams of FIG. 7. 1...first phase control loop, 7. synchronization separation section,
11... 1st phase detector, 12... 10th bus filter, 13... 1st voltage controlled oscillator,
16...1/(n-a) frequency divider, 2...
...Second phase control loop, 21...Second phase detector, 22...Twentieth-pass filter, 23
...Second voltage controlled oscillator, 31...First memory device, 32...Second memory device, 33
...Third memory device, 61...Writing 1/(n-a) counter, 62...Reading 1/(m@lL) counter, 63...・Decoding section, 63... Synchronization signal addition section, 92...
・Timing control section. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2f! 1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (2)

[Claims] (1) The first input signal is a synchronization signal separated from the input signal.
and a second phase control loop and a plurality of sets of memory devices;
A synchronization signal adding section is provided on the output side of these memory devices, and the set of memory devices is sequentially changed for each synchronization signal, and the input is applied only during a predetermined time period that is shorter than the period of the synchronization signal. A signal is written every output pulse of the first phase control loop, and the output signal is written to the output of the second phase control loop only for a predetermined time interval shorter than the period of the synchronization signal from the other memory device set that is not in the write state. A signal processing device configured to repeat a read operation for each pulse. (2) The cutoff frequency of the low-pass filter included in the first phase control loop is higher than the cutoff frequency of the low-pass filter included in the second phase control loop. 1) The signal processing device described in section 1).