JPS63161777A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To select one of plural synchronizing signals without giving an adverse effect to a reproduced picture by selecting and outputting the synchronizing signals from either an internal synchronizing signal generation means or a synchronizing signal control means. CONSTITUTION:An input synchronizing signal 6, whose phase is controlled by a phase locked loop(PLL), and an external synchronizing signal 7 are respectively inputted in horizontal and vertical synchronizing signal generation PLL circuits 26 and 28 which form the horizontal synchronizing signal and the vertical synchronizing signal. Any one of the output signals from the horizontal and vertical synchronizing signal generation PLL circuits 26 and 28 and the output signals from an internal synchronizing signal generating unit 27 is selected with a signal switching unit 29 based on the synchronizing signal selection signal 8 so as to obtain a system synchronizing signal 30. Since a signal switching unit 29 switches alternatively, the adverse effect to be given to the reproduction of a TV signal caused by switching can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization signal generating device in a video tape recorder (VTll), a television (TV) receiver, etc.

[Prior Art] A frame memory device for storing TV signals is shown in FIG. This inputs It, G, [1 human power signal l, converts it from an analog signal to digital No. 48 using a converter 2, and stores it in a frame memory 3.

The timing generator 9 selects one of the internal synchronization signal, the manual synchronization signal 6 as an external signal, and the external synchronization signal 7 based on the synchronization signal selection signal 8, and generates timing synchronized with the selected synchronization signal. Depending on the device, to 〇 converter 2. Controls the frame memory 3゜D^ converter 4 and transfers data synchronized to the selected synchronization signal to the frame memory 3.
This is read out from 〇 and converted into analog data by a converter 4 to obtain It, G, B output signals 5.

In the conventional frame trimming device, the timing generator 9 is constructed as shown in FIG.

Human synchronization signal6. One of the external synchronization signals 7 is selected by the signal switch 11 based on the synchronization signal selection signal 8 . This selected synchronization signal is input to the TV synchronization signal generator 12.

The output signal of the TV synchronization signal generator 12 is input to the control signal generator 13, and from here to 〇Converter control signal 1
4. Memory control signal 15 and D to converter control signal 16
Output.

Furthermore, the TV synchronization signal generator 12 outputs a synchronization signal lO synchronized with the input synchronization signal.

This TV synchronization signal generator 12 has a configuration as shown in FIG. That is, the manual synchronization signal 17 is input to the horizontal synchronization divider 18 and the vertical synchronization signal divider 19, and the separator 18 outputs the horizontal synchronization signal, and the separator 1
9 outputs a vertical synchronization signal.

The phase comparators 20 and 21 are connected to the 2-:! of the TV signal generation frequency divider 23, respectively. Horizontal synchronization signal 2 of one of the output signals of
4 and the other vertical synchronization signal 25 and the horizontal and vertical synchronization signals separated from the manual synchronization signal 17, and the respective phase difference signals are input to a 4fsc (subcarrier) generator 22. The output signal of the 4 f, c generator 22 is input to a frequency divider 23 for generating a TV signal.

As described above, the horizontal synchronization signal 24 synchronized with the synchronization signal 17
The PLl and the circuit are configured so that the vertical synchronization signal 25 and the vertical synchronization signal 25 can be obtained.

[Problems to be Solved by the Invention] However, if the TV synchronization signal generator 12 is configured as shown in FIG. It takes time to do so. That is, in order to configure a PLL at 4 fsc from horizontal and vertical synchronization signals, it is necessary to control the generator 22 with a frequency close to 1000 times the horizontal synchronization frequency, for example.

Therefore, it is difficult to configure a PLL that accurately follows the jitter of the horizontal and vertical synchronizing signals, resulting in disadvantages such as a complicated circuit configuration.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the above-mentioned conventional example and to provide an inexpensive synchronization signal generator.

[Means for Solving the Problems] The present invention provides internal synchronization signal generation means, synchronization signal control means for controlling the phase of an external synchronization signal to form a synchronization signal, internal synchronization signal generation means, and synchronization signal control means. and an output means for selecting and outputting a synchronization signal from one of the above.

[Function] According to the present invention, the synchronization signal from either the internal synchronization signal generation means or the synchronization signal control means is selected and output.

[Embodiment] An embodiment of the present invention is shown in FIG. 1, which is an embodiment of a synchronization signal generator for inputting to the control signal generator 13 of the timing generator 9 in FIG.

As shown in FIG. 1, the input synchronization signal 6 and the external synchronization signal 7 are generated by horizontal and vertical synchronization signal generation PLL circuits 26 and 28, respectively, which control the phase of a human synchronization signal using a PLL to form a horizontal synchronization signal and a vertical synchronization signal. to use human power. Either one of the output signals of the horizontal and vertical synchronization signal generation PLL circuits 26 and 28 and the output signal of the internal synchronization signal generator 27 is selected by the signal switch 29 based on the synchronization signal selection signal 8, and the system synchronization signal is selected. Get 30. This system synchronization number 8 30 is assumed to be the number 8 of the control signal generator 13 in FIG.

In this way, in order to generate the system synchronization signal 30, the external signals (human synchronization signal and external synchronization signal) are provided with independent horizontal and vertical synchronization signal generation PLL circuits 26, respectively.
and 28, and since these and the internal synchronization signal generator 27 are selectively switched by the signal switch 29, it is possible to eliminate the adverse effect on TV signal reproduction caused by switching, and also to Synchronous signal generation PL
The L circuits 26 and 28 can be constructed, for example, from a synchronization signal PLLIG used in commercially available TV receivers.

Next, FIG. 2 shows an example of a more specific configuration of the configuration shown in FIG. 1.

The horizontal synchronization signals PLLs 31 and 38 generate horizontal synchronization signals synchronized with the manual synchronization signal 6 and the external synchronization signal 7, respectively, in a PLL configuration.

Similarly, vertical synchronization signals PLLs 32 and 39 generate vertical synchronization signals synchronized to human synchronization signal 6 and external synchronization signal 7, respectively, in a PLL configuration.

Furthermore, the synchronization signal detectors 33 and 40 detect the presence or absence of the human synchronization signal 6 and the external synchronization signal 7, respectively.

Field detectors 34 and 41 output signals of horizontal synchronization signal PLL31 and vertical synchronization signal PLL32, and output signals of horizontal synchronization signal PLL38 and vertical synchronization signal PLL4, respectively.
The field of the TV signal is detected from the output signal of 0.

Non-interlace detectors 35 and 42 detect non-interlace signals from the output signals of field detectors 34 and 41, respectively.

When the 2V Gate circuit 36 determines that a synchronization signal is present based on the output signal of the synchronization signal detector 33, the 2V Gate circuit 36 controls one frame for a 2V (vertical scanning) period after the freeze signal 37, which is a control signal for stopping the frame memory, is input manually. Outputs a capture signal of a still image signal.

46 is a mode selector, which includes selector circuits 47 to 46;
51.

The 172 frequency divider 52 divides the output signal of the selector circuit 48 into 172 frequencies.

The master clock oscillator 53 generates a master clock synchronized with the output signal of the selector circuit 49, and uses this as the clock for the to-〇 converter, the clock for the horizontal address counter of the frame memory, and the clock for the D-to-converter.

The operation shown in FIG. 5 is shown in FIG.

In FIG. 6, symbols with only numbers indicate outputs of the corresponding circuit elements.

FIG. 6 basically shows a configuration in which a selected synchronization signal is output by synchronization signal selection.

In this embodiment, three signals, a manual synchronization signal, an internal synchronization signal, and an external synchronization signal, are switched as the selected synchronization signals, but it goes without saying that the number of these signals may be increased or decreased.

Furthermore, although this embodiment has been applied to a device that stores TV signals, it is clear that the present invention can be applied to systems that switch and use various TV synchronization signals.

[Effects of the Invention] As explained above, according to the present invention, one of a plurality of synchronization signals can be selected without adversely affecting the reproduced image. Furthermore, the synchronization signal control means (for example, PLL circuits for generating horizontal and vertical synchronization signals) can be constructed from a PLLIC for synchronization signals used in commercially available TV receivers, which is inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a diagram showing a more specific configuration of the same embodiment, FIG. 3 is a block diagram of a frame memory device, and FIG. 4 is a diagram showing the configuration of a timing generator. Figure 5 is a diagram showing the configuration of a part of the generator, Figure 6 is a diagram showing the configuration of a part of the generator.
This figure is a diagram showing the operation timing of the configuration shown in FIG. 2. 26.28...Horizontal and vertical synchronization signal generation PLL circuit, 27...Internal synchronization signal generator, 29...Signal switch.

Claims (1)

[Claims] Internal synchronization signal generation means; synchronization signal control means for controlling the phase of an external synchronization signal to form a synchronization signal; and synchronization from either the internal synchronization signal generation means or the synchronization signal control means. 1. A synchronous signal generator comprising output means for selecting and outputting a signal.