JPS60171869A - Synchronizing signal generator - Google Patents

Abstract

PURPOSE:To transmit a TV signal only with a clock synchronism without intervention of a color burst by resetting a frequency divider in a PLL circuit generating a clock being an integral number of multiple of a subcarrier frequency at each color frame. CONSTITUTION:A subcarrier fsc in 3.58MHz is given to a phase comparator 1, and the phase of the result is compared with that of a signal frequency-dividing a signal having 32fsc oscillating frequency of a VCO2. The phase error signal is given to the VCO2 as a control voltage, the 32fsc oscillating output is obtained in synchronization with the subcarrier and a sample clock fsa of 4fsc is obtained from a frequency divider 4. Since the frequency dividers 3, 4 are reset by a 15Hz color frame pulse CF, the sample clock fsa and a serial data clock fsi are synchronized with the TV signal.

Description

[Detailed description of the invention] Industrial application field.

TECHNICAL FIELD The present invention relates to a synchronization signal generator, and particularly to a digital VTR.
It is ideal for use in circuits that form synchronization signals (including sampling clocks and data transmission locks).

Background technology and its problems Conventionally, composite color TV signals have been converted into digital VT.
When recording and reproducing in R, the sampling frequency is often 6 or 4 times the subcarrier frequency, and the quantization number is 8 bits. The sampling clock is formed based on 3.58 MHz subcarriers locked to the color burst.

However, when the recording density of the tape is increased, the recording frequency is too high and sufficient recording and playback characteristics cannot be obtained.
It is necessary to lower the bit rate to a degree that does not cause a large deterioration in image quality, and it is appropriate to select the sampling frequency to be 2 to 6 times the subcarrier frequency and quantization P16 to 7 bits. In this case, the sampling frequency may be selected to be a non-integer multiple of the subcarrier frequency.

By the way, by taking advantage of the features of a digital VTR, instead of transmitting (recording and reproducing) color burst waves, a color burst is created in synchronization with a pit clock that is synchronized with playback data during playback, and this is interpolated into the playback signal. We can think of a system that can be replaced.

Such a system eliminates color unevenness due to phase shift that occurs when recording and reproducing color bursts (color standards).
It provides high image quality unique to digital VTRs, which analog VTRs do not have.

-However, in such a system, both the phase relationship between the TV signal and the sampling clock during recording and the phase relationship between the TV signal and the readout clock during playback must be constant, and the phase relationship is unstable. If so, the phase relationship between the color burst wave generated during reproduction and the reproduced TV signal changes, and the reproduced hue changes. In particular, if the system clock (sampling clock and bit recovery clock on the playback side) is a non-integer multiple of the subcarrier, it becomes virtually difficult to transmit color (recording and playback) using only clock synchronization without performing colorverse recording and playback. .

OBJECT OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is a method that allows a TV signal and its processing clock (such as a sampling clock on the recording side or a bit recovery clock on the reproduction side) to have a fixed phase relationship. This enables accurate color transmission (recording and playback) with clock synchronization in, for example, a digital VTR, etc., without transmitting color bursts. This device includes a PLL circuit that generates a double clock or a non-integral multiple clock, and a frequency divider that divides the output of an oscillator in the PLL circuit is reset for each color frame. This allows the phase relationship between the TV signal and its processing clock to be constant.

Example The present invention will be explained below based on examples.

FIG. 1 shows a digital V'I, which shows a first embodiment of the present invention.
” is a block diagram of a synchronization signal generator of H. In this example, a subcarrier fsc is formed in phase synchronization with a color burst of an input video signal, and a digital VTR system clock (processing clock) which is an integer multiple of this subcarrier is generated. ) is created using a PLL circuit.

In Fig. 1, the subcarrier fsc of 3.58 MHz is given to the phase ratio [device 1, and the output of V0O2 having an oscillation frequency of 32 fsc is rotated for 1/32 minute to compare the phase with the signal. . The phase error signal is given to V2O3 as a control voltage, and the phase error signal is 32 f phase-synchronized with the subcarrier.
An oscillation output of sc is obtained. This output is frequency-divided by a divider 4 of 178, and a sample clock fsa of 4 fsc is used.
is obtained. Based on this sample clock, the input video signal is quantized to, for example, 8 bits. Also V2O3
The output of is 32 fsc serial data clock fsc
It is used as a parallel/serial conversion of recorded data and a read pit clock of reproduced data.

The branchers 3 and 4 are reset by a 15 Hz (4 field) color frame pulse OF.

The phase of the subcarrier (color burst) is completed in four fields (one color frame), and the phase matches the synchronization signal of the TV signal for each color frame. Therefore, the sample clock and serial data clock obtained from the synchronization signal generator of FIG. 1 are synchronized with the TV signal by resetting every color frame. In the recording system of a VTR, when recreating various synchronization signals such as horizontal and vertical synchronization signals and color frame pulses that are separate from the input video signal, a frequency divider that further divides the sampling clock output shown in Figure 1 is used. is used.

During recording, the color frame pulse 0Ff)S is recorded as a control signal on the side edge of the magnetic tape.

Then, during playback, servo control (drum servo and/or capstan servo) is performed so that the phase of the 15Hz servo reference pulse obtained by dividing the free-run reference oscillator and the playback control signal OTL matches.
By multiplying by 0, the phase relationship between the reproduced signal and the output (data clock or bit clock) of the free-run oscillator is fixed, and the bit data of the reproduced signal can be read in this synchronous state. In addition, if a 3.58 MHz burst wave is formed from the standard bit clock (data clock) by branching and inserted into the playback signal, high-quality signals with no color phase change due to passing through the recording/playback system can be obtained. You can get the image.

Next, FIGS. 2 and 6 show a second embodiment of the present invention,
FIG. 2 is a block diagram of a synchronizing signal generator for a recording system of a digital VTR, and FIG. 3 is a block diagram of a synchronizing signal generator for a reproducing system.

In this second embodiment, a system clock (sample clock or data clock) that is a non-integer multiple of the subcarrier is generated. Therefore, in a system that does not perform color synchronization by recording and reproducing color bursts, synchronization between the system clock and the TV signal is necessarily required.

Note that in order to generate a system clock that is a non-integer multiple of the subcarrier fsc, a PL as shown in FIG. 4 or 5 is generally used.
An L circuit is used. In FIG. 4, in VOO20, the frequency Af is A times the reference clock fR (for example, subcarrier).
After obtaining the output of B, the frequency is divided into i/A by the frequency divider 21, and the phase is compared with the reference clock by the phase comparator 22.
Control the VC020 with the error voltage to synchronize the phase with the reference clock, and divide the output of this VOO20 into 1/B by the frequency divider 26.
I have met you.

In the case of the circuit shown in FIG. 4, the oscillation frequency AfR of the voltage controlled oscillator VOO20 is selected to be the least common multiple of the base clock frequency f8 and the required output clock frequency fv (=sfn). Therefore, if fR and fv do not have an integral multiple relationship, the oscillation frequency AfR of the VOO 20 will be extremely high, making manufacturing difficult. For example fn −3,5
8MHz, fv(4fR)=9. Assuming OOMHz, VOO oscillation frequency Af R = 1.611 G
Hz.

The division ratio A=450 and B=179.

In FIG. 5, the output frequency of the VOO 20 is -s f B, which is set to 1/A by the frequency divider 21, and then the reference clock fR is set to 1/B by the frequency divider 23 in the phase comparator 22.
The VOO 20 is controlled by an error voltage compared with a signal whose frequency is divided into .

In the case of FIG. 5, the frequencies compared by the phase comparator 22 are:
Reference frequency fR and required output lock frequency f
Since it is selected as the greatest common divisor with v (= Tf R), if fR and fv do not have an integral multiple relationship, the comparison frequency n fH will be a very low frequency, and the frequency response of the PLL circuit will be slow. The followability to the reference clock is poor (1°), for example, fR450, B=179.

Furthermore, in both the cases of FIGS. 4 and 5, the frequency division ratios A and B become large, requiring multi-stage counters, and the circuit becomes complicated.

In FIG. 4 or 5, in order to synchronize the phase of the output clock with the color frame, it is conventionally necessary to use a 15 Hz color frame pulse as the reference clock, and therefore, the phase comparator 22 has a very low frequency. Since phase detection is performed in a long cycle, the response speed of the PLL circuit is 1 and the problem is S.

Therefore, in order to obtain a non-integer multiple of the reference clock, it is preferable to use a PLL circuit as shown in FIG. The synchronizing signal generator of the embodiment shown in FIGS. 2 and 3 has the basic configuration shown in FIG.

In FIG. 6, first, a PLL circuit ( PLL-1). Next, using the oscillation frequency AfR of ■0026 as a reference, AfR
is multiplied by 1/B by the frequency divider 28 and 1/D by the frequency divider 62, and the resulting frequency fR can be set to any non-integer multiple. Further, A, B, O, and D are determined to be multiples of relatively small integers. As a result, the oscillation C frequencies AfR and -fR of VOO26 and VOO30 become relatively low frequencies,
Moreover, the comparison frequencies fR and n fB in the phase comparator 25 and the phase comparator 29! The frequency is relatively high.

For example, reference clock frequency f B =3.58 MH
zs output four frequency fv (= 4 fB) =
When the frequency is 9.00 MHz, the division ratio A=11, B=5
．． By setting 0=8 and D=7, the oscillation frequency AfB of V0O26 becomes 3938MH1, and the oscillation frequency of V0030 becomes 0-T-fR=66.008MHz. Also, the comparison frequency of the phase comparator 25 is f B "" 3.58 MHz
1 The comparison frequency of the phase comparator 29 is s f n =Z8
It becomes 76MHz.

The embodiments shown in FIGS. 2 and 6 are based on FIG. 6, and the same parts are given the same reference numerals.

In FIG. 2, first, a color burst wave and a composite synchronization signal are separated from a TV signal by a color burst separation circuit 36 and a synchronization separation circuit 64. Then, continuous color subcarriers are created from the color burst wave by burst A and PO35. A color frame pulse is extracted from the composite synchronization signal by a color frame separation circuit 36. Next, using the continuous color subcarrier as a reference clock, the phase comparator 25 and the frequency 11 fsc (39,3
V6O13, 1/11 frequency divider 2 oscillating at 75MHz)
7 constitutes a PLL circuit (PLL-1), and 11 f
SC is divided into 115 by the divider 28, and the frequency is 15 fs.
c (7,875MHz).

Next, set 1115 fsc as a new standard, phase comparator 29, frequency 11 x 8/5 f sc
VCo oscillating at (63,008MHz), 5O11/
8 PLL circuit (PLL-2) by frequency divider 1/61
11×815fs. is divided into 1/7 by the frequency divider 32 to obtain 88/35 fsc, which is used as the sample clock fsa.

Also, if the frequency division ratio 1 is equal to the number of quantization bits, 88
15fsc is the serial data clock fsi.
'Sa, fBi can be selected to be a non-integer multiple of subcarrier f8C by a combination of frequency division ratios and integer values of 11, 5, and 8.7.

Furthermore, the sample clock fsa is divided into 1/E by the frequency divider 37.
A color frame pulse (15Hz) is obtained. This color frame pulse can be stably obtained even if the input TV signal is momentarily lost. This color frame pulse is recorded on the side edge of the tape as a control signal OTL in order to provide the servo system with color frame information that serves as a reference for the clock phase during reproduction.

In order to synchronize these various system clocks with the input TV signal, the splitter 27.2B uses the color frame pulse extracted from the synchronization separation.

32. Reset 37. This makes it possible to generate a clock that is a non-integer multiple of the subcarrier in synchronization with the TV signal. Note that the frequency divider 31 is a PLL circuit (PLL-
Since it is in the loop of 2) and the input pulse to this PLL circuit is already synchronized with the color frame, there is no need to reset it with the color frame pulse.

The synchronizing signal generator of the reproducing system shown in FIG. 3 is the same as that of the recording system, and can be used in common. During reproduction, the reference subcarrier tsc is given to the phase comparator 25 from the freely oscillating oscillator 40, and the sample clock '8a s serial data clock fsi is generated by the PLL circuit (PLL-1 and PLL-2).

The subcarrier clock from the oscillator 40 is made into a burst by a burst gate pulse, and inserted into the reproduced TV signal as a burst wave. In addition, the subcarrier clock is a 15Hz color frame pulse l by the 1/E frequency divider 41.
The signal is frequency-divided and applied as a reset pulse to the frequency divider 27, 28, and 32, and is also applied as a reference clock to the servo system of the VTR. Then, servo control is performed so that the reproduced OTL signal is phase-synchronized with the reference clock. This allows the data played from the tape to be synchronized with the serial data clock fsi and sample clock fga.
can be read synchronously with That is, the servo system (head drum or capstan) operates so that the free-run read clock and reproduced data bits are synchronized.

Through the above operations, even if the required system clock such as the sample clock is a non-integer multiple of the subcarrier frequency, and even if color burst waves are not recorded, the phase relationship between the TV signal and the clock during recording will be within the color frame. It is self-sufficient (constant residence) based on the color frame, and during playback, it is reproduced by servo control based on the color frame.
A constant phase relationship between the V signal, the system clock, and the added color burst is obtained. Therefore, no hue change occurs in the reproduced signal due to color burst recording and reproduction, and a high-quality reproduced image can be obtained.

Effects of the Invention As described above, the present invention provides a PL that generates a clock having a frequency that is an integral multiple or a non-integral multiple of the color subcarrier.
Since the frequency divider in the L circuit is reset for each color frame to obtain a clock whose phase is synchronized with the color frame, the phase relationship between the TV signal and its processing clock is constant, and therefore the color burst cannot be mediated. It is possible to accurately transmit (record and play) digitized TV signals (particularly color signals) only by clock synchronization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the synchronization signal generator of the present invention, and FIGS. 2 and 3 are synchronization of the recording system and reproduction system of a digital VTR, showing a second embodiment of the invention. A block diagram of a signal generator. Figures 4 and 5 are block diagrams of a general synchronous signal generator that generates a clock that is a non-integer multiple of the subcarrier. Figure 6 is a basic diagram of Figures 2 and 3. FIG. 2 is a block diagram showing the configuration. In addition, in the symbols used in the drawings, 1 ...... Phase comparator 2...
・・・・・・・・・・・・VOO3,4・・・・・・
...It is a frequency divider. Agent Masaru Ueya Yoshio Tsuneko

Claims (1)

[Claims] A synchronous signal generator comprising a PLL circuit that generates a clock of an integral multiple or a non-integer multiple of the subcarrier frequency based on a color subcarrier, wherein a frequency divider that divides the output of an oscillator in the PLL circuit is a color frame. The synchronization signal generator is provided with a reset means for resetting each time the clock is synchronized with the color frame.