JPS61131915A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To obtain an analog output without distortion by using a clock signal phase-locked to a synchronizing signal detected from a digital input signal so as to demodulate, D/A-convert and sample-and-hold the input signal. CONSTITUTION:When a digital input signal RX is inputted to a detection circuit 2, a synchronizing signal 2FSR is detected. The synchronizing signal has a frequency twice the sampling frequency fS and fed to a phase comparator 3 of a phase locked loop PLL circuit 7 and compared with a feedback signal from a frequency divider 6, a phase comparison error signal is converted into a DC voltage by a loop filter 4, a clock signal RXCP is extracted from a control voltage oscillator 5 controlled by this voltage, and the signal RXCP is fed to a demodulation circuit 8 together with the signal RX. These signals are subjected to serial/parallel conversion 9 and D/A conversion 10 and then sample-and-hold 11, and an analog signal without distortion is outputted (15).

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is suitable for use in converting a digital signal into an analog signal (hereinafter referred to as D/A conversion) in, for example, audio equipment. Regarding.

[Conventional technology]

One type of digital transmission system is a digital audio interface transmission system. This digital audio interface supports L channel with one digital cable.

R channel transmits two data. For this reason, the first
As shown in FIG. 4A, a time division multiplex transmission method is used in which L channel data and R channel data are alternately transmitted and received. For example, if the sampling frequency is 44.1kHz like a compact disc, the L channel and R channel
Each channel has 44,100 pieces of data per second.
A total of 88,200 pieces are transmitted on both channels. The length of one channel data section (word) is 11.3
It is 4 microseconds. Further, one word is composed of 32 bits, and the bits are divided as shown in FIG. 14B in this case. In other words, in the same figure, the first 4
The bit is the 5YNC part for synchronization, and a preamble described later is inserted. Next is the part where audio data is entered, and there is a 24-bit field.

However, most audio data, such as compact discs, are 16 bits, and currently only the last 16 bits are used. The last 4 bits are a control part that carries information attached to the data such as ON/OFF of emphasis and subcode.

As shown in FIG. 14C, the data assembled in this way has a so-called biphasic mark (biphas mark) in which data "0" is inverted once and data "1" is inverted twice.
A modulation called e mark) is applied. However, 5
The YNC part is an exception, and the preamble (prea+5bl
A special pattern called e) is inlaid. In the preamble, the inversion response due to data is ignored, and the time that the high level continues is longer than in any other part.

[Problem that the invention seeks to solve]

However, a D/A conversion device for D/A converting a digital audio interface signal in which audio data has been modulated using a specific modulation method such as the biphase mark modulation method as described above has not yet been developed.

The present invention has been made in view of this point, and is a D/A converter that can D/A convert an input signal including at least a synchronization signal and audio data modulated using a predetermined modulation method, such as a digital audio interface signal. A conversion device is provided.

[Means for solving problems]

The present invention includes a detection circuit (2) that detects a synchronization signal from a human input signal that includes at least a synchronization signal and audio data modulated with a predetermined modulation method, and a detection circuit (2) that detects a synchronization signal from a human input signal that includes at least a synchronization signal and audio data modulated with a predetermined modulation method; P that generates the clock signal
An LL circuit (7) and a demodulation circuit (8) which obtains a demodulated signal in response to the clock signal from the PLL circuit and the input signal.
), and a D/A converter Y&+9)α・ which converts the demodulated signal from this demodulation circuit from a digital signal to an analog signal.
and sample/hold means (11) (12) for sampling and holding the output of the D/A converting means using a sampling timing signal formed from the demodulated signal and a signal related to the clock signal. It consists of

[Effect]

A detection circuit (2) detects a synchronization signal from the input signal, phase-locks to the detected synchronization signal, forms a clock signal of a predetermined frequency in a PLL circuit (7), and converts this clock signal and a human input signal into a demodulation circuit. (8) to demodulate the input signal based on the clock signal, convert the demodulated signal from a digital signal to an analog signal in the D/A conversion means +Q+, Ql, and form the input signal based on the demodulated signal and the clock signal. By sampling and holding the D/A conversion output in the sample and hold means (11) and (12) using the sampling timing signal, a desired analog signal is obtained at the output side of the sample and hold means.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 13.

FIG. 1 shows a first embodiment of the present invention, in which fil is an input terminal to which an input signal in the format shown in FIG. 14 is supplied, and (2) is an input terminal (1
This is a detection circuit that detects, for example, a synchronization signal having a frequency twice the sampling frequency fs of audio data from the input signal from the audio data. As shown in FIG. 2, this detection circuit (2) is, for example, an inverter (2b) provided between the other input terminal of -(2a) and input terminal +1) to form a delay circuit.

(2c) and a capacitor (2d), and are provided on the output side of the exclusive OR circuit (2a) for a predetermined set time twL, for example, twt! =v450n sec, and a retriggerable mono multivibrator (2e) provided on the output side of this mono multivibrator (2e),
It is possible to use a retriggerable mono multivibrator (2f) having a predetermined setting time tw2, for example, ti*z#5μ1iec. Note that the mono multivibrator (2f) may be a normal mono multivibrator without using a retriggerable type.

Returning to Figure 1 again, (3) indicates that the output of the detection circuit (2) is 1.
For example, a negative edge comparison type phase comparator is supplied to the input side, (4) is a loop filter provided on the output side of the phase comparator (3), and (5) is a loop filter (the oscillation frequency of which is determined by the output of the gradient). This oscillator (5) is a controlled voltage-controlled oscillator, and a clock signal having a frequency that is, for example, 256 times the sampling frequency fs is obtained on the output side of this oscillator (5). Any value may be used as long as it is a frequency. (6) is the oscillator (5
), the output of this frequency divider (6) is supplied to the other input side of the phase comparator (3). The phase comparator (3), loop filter (4), oscillation a (5), and frequency divider (6) constitute a so-called PLL circuit (7).

(8) is a demodulation circuit that demodulates (decodes) the input signal from the input terminal (1) based on the clock signal from the PLL 1 path (7), and the output side of the circuit demodulates (decodes) the input signal from the input terminal (1). Lock BCK, L
A clock LRCK for identifying the channel and R channel is output. (9) is a demodulation circuit (which converts the demodulated signal from 81 from a serial signal to a parallel signal (hereinafter referred to as S/P
The S/P conversion circuit outputs 16-bit parallel data per channel at the falling edge of the clock LRCK, that is, at the end of the R channel, as will be described later.

The a-ring is a 16-bit parallel input current output type D/A conversion circuit that converts the output of the S/P conversion circuit (9) from a digital signal to an analog signal.

(11) is a sample/hold circuit that samples and holds the output of the D/A conversion circuit α. A D-type flip-flop circuit (12) is used to form a sampling timing signal for this sample-and-hold circuit (11).
The clock LRCK from the demodulation circuit (8) is supplied to the input terminal of this flip-flop circuit (12), and the output of the frequency divider (61) of the PLL circuit (7) is supplied to the clock terminal CK. The signal is supplied via an inverter (13), and each output of the output terminal Q and the inverting input terminal of the flip-flop circuit (12) is supplied as a sampling timing signal to the sample-and-hold circuit (11).

As the sample and hold circuit (11), for example, one shown in FIG. 3 is used. That is, a differential amplifier (jla) is provided, and the inverting input terminal of this differential amplifier (lla) is connected to the output side of the D/A conversion circuit αl (FIG. 1) via a switch circuit (llb). The switch circuit (llb) is connected to the input side and the ground side of the switch circuit (llb).
c) is provided. In addition, the non-inverting input terminal of the differential amplifier (lla) is grounded, a capacitor (lid) is connected between the inverting input terminal and the output terminal, and the output terminal of the differential amplifier (lla) and the switch circuit (llb')
A resistor W(lie) is connected to the input side of. The switch circuits (llb) and (llc) are controlled by the inverting output and output of the flip-flop circuit (12), respectively.

In the sample-and-hold circuit (11), the switch circuit (llb) is turned off as shown in FIG.
c) is in a hold state when it is on, and contrary to the state shown in the figure, it is in a sample state when the switch circuit (llb) is on and the switch circuit (llc) is off.

In addition, in FIG. 1, (14) is a filter provided on the output side of the sample/hold circuit (11), and (15)
is the output terminal.

Next, the rotation operation shown in FIG. 1 will be explained with reference to FIG. 4.

Now, an input signal %Rx as shown in Fig. 4A is supplied from the input terminal (11).The upper part of Fig. 4A is the human input signal Rx.
The waveform is shown in detail, and the lower part of FIG. 4A shows the same input signal Rx horizontally. Such an input signal Rx is supplied to the detection circuit (2), and in the detection circuit (2),
As shown in Fig. 2, an exclusive OR circuit (2
By directly supplying the human input signal Rχ to a) and supplying it after a certain delay, an exclusive OR circuit (2a
), all edges of the input signal Rx are extracted, although not shown. When all the extracted edges are passed through a retriggerable mono multivibrator (2e), a pulse is output when the distance between edges is approximately 450nsee or more.In the case of a zero human power signal Rx, this pulse is output. The part that corresponds to the synchronization signal (SYN) of the L channel and R channel
C) exists only. The R channel outputs one pulse, but the L channel outputs 2111 pulses continuously, so by passing this pulse through a retriggerable mono multivibrator (2f), one edge per I5YNC ( 2nd FI of falling)
! A synchronizing signal 2PSR as shown at JB is detected. This synchronization signal 2FSR has a frequency twice the sampling frequency fs as described above.

The synchronization signal 2FSR from the detection circuit (2) is sent to the PLL circuit (
7) to the phase comparator (3) where the frequency divider (6
) is compared in phase with the feedback signal 2FSV (FIG. 4F).

Then, the phase comparison error (blind symbol) is converted into a DC voltage by the loop filter (4), and based on this DC voltage, the oscillator (5)
) is controlled, and a clock signal RxCP for decoding the human input signal RX is obtained at the output side of the PLL circuit (7), that is, the output side of the oscillator (5). Input signal Rx
The relationship between the black signal RxCP and the human input signal Rx when there is no jitter is expressed as shown in FIG.

Here, as a characteristic of the PLL circuit (7), the synchronization signal 2PSR
If a phase input is added as jitter to the frequency division W +6)
Considering the closed-loop transfer function that determines how well the feedback signal 2FSV can track, there is a flat tracking region as shown by curve a in Figure 5, and a downward-sloping cut-off region where the curve is already accepted. Can be divided. The frequency range of this flat part is the band of the PLL circuit, and here, 94H2 and 8.5kHz are shown, which are about 90 times the difference in ratio. And in this case the 51st i! ! The shaded area indicated by l represents the difference in jitter followability depending on the band of the PLL circuit.

The clock signal RxCP from the PLL circuit (7m) thus obtained is supplied to the demodulation circuit (8) together with the input signal Rx from the input terminal (1).
The input signal Rx and clock signal RxCP supplied to
When there is no jitter in the input signal Rx, it is expressed as shown in FIG. 6, and there are two positive edges of the clock signal RxCP shown in FIG. 6B in one cell of the input signal Rx shown in FIG. 6A. Decoding is possible if the number is included. As a result, on the output side of the demodulation circuit (8), 16-bit serial data DAT^ as shown in FIG.
Ll for identifying SL channel and R channel? CK is obtained.

These outputs are supplied to the S/P conversion circuit (9), and at the falling edge of the clock LRCK, that is, at the end of the R channel, 16-bit parallel data PDATA per channel as shown in Figure 4 is sent to the S/P conversion circuit. (9) is obtained on the output side. This disparate data P[1ATA is supplied to the D/A conversion circuit, and one output current as shown in FIG. 4 corresponding to the parallel data PO^TA is taken out as an analog signal on the output side. The settling time required for switching between these two output currents is approximately 350
n sec. Further, an output current of 1 inch has a relationship of ±1 m for a full bit, that is, 16 bits. This output signal Iyo is supplied to a sample and hold circuit (11).

The clock LRIJ from the demodulation circuit (8) is supplied to the input terminal of the flip-flop circuit (12), and
By inverting the feedback signal 2FSV from the inverter (13) and supplying it to the clock terminal CK of the flip-flop 1 circuit (12), the inverted output terminal Q of the 29717071 circuit (I2) is output as shown in Fig. 4 G. A signal APT is obtained, and the output terminal Q receives a signal π as shown in FIG. 4H.
7 points are obtained. These signals APT and APT are supplied to the sample and hold circuit (11) as sampling timing signals.

The sample and hold circuit (11) is configured so that the signal APT is “0”.
” and the signal APT is “1”, the switch circuit (11t+) in FIG. When , the switch circuit (llb) is turned on and the switch circuit (llc) is turned off to enter the sample state. By repeating this step, the sample and
An output voltage Vctx as shown in FIG. 4 is obtained on the output side of the hold circuit (11). This output voltage Vax is filtered (14) to remove unnecessary components such as harmonic components, and then output as a desired analog signal to an output terminal (15). In this way, even if the audio data has been subjected to phase mark modulation, it can be easily D/A converted.

By the way, the data cell of the input signal Rx and the clock signal R
When the xCP position was as shown in FIG. 6 and there was no jitter, accurate decoding was possible as described above. However, P.L.
When the band of the L circuit (7) is narrowed, if jitter exists in the human input signal Rx (beyond the band), the input signal Rx and the clock signal RxCP will not match in phase, making decoding impossible. For example, a PLL circuit (with a band of η of 94
Hz and a narrow band, and when jitter as shown in Fig. 7 is added to the human input signal Rx, the input signal Rx and the clock signal Rx
The CP relationship was as shown in Figure 8, and it was almost impossible to decode it.

In addition, in FIG. 7, A1 has an average jitter amplitude of 20
At ~3Qn sec, the amplitude of A2 becomes ± like pop noise.
It is shown that it reaches about 100 nsec.

On the other hand, when the band of the PLL circuit +71 is expanded to 8.5kHz, the relationship between the input signal Rx and the clock signal RxCP becomes as shown in Figure 9, and the relative jitter between the input signal Rx and the clock signal RxCP is It becomes unobservable and decoding becomes complete. When decoding from this, PL
It is my knowledge that the wider the band of the L circuit, the better.

Next, an experiment was carried out in the case where there was jitter, such as that shown in FIG. 10, which was not so large as to cause a hindrance to decoding, and it was confirmed that the wider the band of the PLL circuit (7), the worse the distortion rate. Figure 11 shows this situation, where curve a represents the case where the band is 13.5 kHz and curve a represents the case where the band is 94 Hz. From this, it can be seen that the distortion is greater in the band of 8.5 kHz than in the case of the band of 94 Hz. It can be seen that the rate is getting worse.

This occurs through a mechanism as shown in FIG.

In other words, the PLL circuit (if the band of the sword is wide, this PLL circuit
Since the output 2PSV of the divider (6) of the circuit (7) contains jitter, this is used as a clock signal to obtain the sampling timing signal of the sample-and-hold circuit (11) at the output side of the flip-flop circuit (12). As a result, jitter is introduced into the signals APT and APT, and the sample-and-hold circuit (1
The output voltage of 1) changes according to the timing signal APT (and r) as shown on the left side of Figure 12, but when the shifter is mixed in, the sample-and-hold circuit (1)
The output voltage 1) changes as shown on the right side of FIG. In other words, due to the influence of the shifter, when the sample time becomes shorter, the level decreases by the amount of the curve due to the sampling time constant, as shown by the symbol a, and when the sample and hold times become shorter, the level narrows by the area already indicated by the symbol. Therefore, these factors become a factor in deteriorating the distortion rate. Note that in FIG. 12, tL+t2+L3 represents that the timing time is shortened due to jitter.

In this way, whether the band of the PLL circuit (η) is made wide or narrow, there are drawbacks, and this is due to the fact that the demands on the PLL circuit (7) are different between decoding performance and sample/hold performance.In other words, decoding performance From the point of view, it is preferable for the PLL circuit to have a wide band; conversely, from the point of view of sample-hold performance, that is, distortion rate, the PLL circuit should have a wide band.
It can be seen that the narrower the band of the L circuit, the better.

FIG. 13 shows a second embodiment of the present invention, which was made in view of the above points. In the figure, parts corresponding to those in FIG. do.

In this embodiment, a phase comparator (16), a loop filter (
17) and a PLL circuit (19) consisting of a voltage-controlled oscillator (1 day) and phase comparison! The output of the detection circuit (2) is supplied to one input side of (16), and the phase comparator (
The output of the oscillator (18) is supplied to the other input side of the oscillator (16). Further, the output of the oscillator (18) is supplied to the clock terminal GK of the flip-flop circuit (12) via the inverter (13).

The other configurations are the same as in FIG. 1.

The oscillation frequency of the oscillator (18) of the PLL circuit (19) is twice the sampling frequency fs.
The signal A2PS supplied from the phase comparator (18) to the other input side of the phase comparator (16) is supplied to the phase comparator (
3) is the same in frequency as the signal 2FSV supplied to the other input terminal. However, while the signal 2PSV contains a lot of jitter, the signal ^2FS has little jitter.
In other words, in this embodiment, the PLL circuit for decoding (71 has a wide band) and the PLL circuit for sample and hold (1
9) is used with a narrow band. As a result, even if jitter as shown in Fig. 7 is added to the input signal Rx, it can be accurately decoded by the demodulation circuit (8), and the distortion rate characteristic at this time is within the 94Hz band already shown by the curve in Fig. 1. It became similar to.

In the above embodiment, the D/A converter circuit (α type) is of the output type, but a voltage output type may also be used. In this case, a resistor is connected to the input side of the sample/hold circuit (11). Insert one.

Furthermore, since the PL'L circuit can be configured by combining components with different bands, they do not necessarily have to be combined in parallel as shown in Fig. 13. For example, a narrowband PLL circuit can be incorporated using the output of a wideband PLL circuit manually. In other words, they may be connected in cascade. At this time, the configuration is such that the output of the frequency divider (61) of the PLL circuit (7) is supplied to one input terminal of the phase comparator (16) of the PLL circuit (19).

In addition, although the above example has been explained using a case where the sampling frequency is 44.1 kHz, the case is not limited to this, and other sampling frequencies such as 48 kHz or 32 kHz can be used.
Similarly, in the case of kHz, etc., 1Jfi is commonly used.

〔Effect of the invention〕

As described above, according to the present invention, a synchronization signal is detected from a digital input signal, phase-locked to this synchronization signal to obtain a clock signal of a predetermined frequency, and a human input signal is demodulated based on this clock signal and subjected to fl modulation. Converts the signal to D/A,
Since this D/A converted signal is sampled and held using a predetermined sampling timing signal,
Even special digital input signals such as digital audio interface signals in which audio data is subjected to pi-phase mark modulation can be easily D/A converted.

In addition, since multiple PLL circuits are used exclusively for decoding and sample/hold, taking into account the respective bands, even if the input signal contains jitter, it can be decoded and D/A converted. It is possible to prevent distortion from occurring in the sample-and-hold circuit at the time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams showing an example of the essential parts of the invention, respectively.
Figure 4 is a diagram for explaining the operation of Figure 1, Figures 5-
FIG. 12 is a diagram for explaining the invention, FIG. 13 is a block diagram showing another embodiment of the invention, and FIG. 14 is a diagram for explaining the digital audio interface format. (2) is a synchronization signal detection circuit, (71, (19) is a PLL
circuit, (8) is a demodulation circuit, (9) is a serial/parallel (S/P) conversion circuit, α is a digital/analog (D
/A) Conversion circuit, (11) is sample and hold circuit,
(12) is a D-type flip-flop circuit. Figure 1 Figure 2 Figure 3 Figure 1p Figure 5 Shoulder*Number Figure 6 RxCP Figure 7 Time (EeC) Figure 8 Figure 9 B ytxcp-mouth B pxcp''! ff 1st
Figure 0Figure 14

Claims (1)

[Claims] 1. A detection circuit that detects a synchronization signal from an input signal including at least a synchronization signal and audio data modulated by a predetermined modulation method, and a detection circuit that detects a synchronization signal at a predetermined frequency by locking the phase to the detected synchronization signal. a PLL circuit that generates a clock signal, and a PLL circuit that generates a clock signal of
a demodulation circuit that obtains a demodulated signal in response to a clock signal from the LL circuit and the input signal; a D/A conversion means that converts the demodulated signal from the demodulation circuit from a digital signal to an analog signal; and the D/A conversion. A D/A converter comprising sample and hold means for sampling and holding the output of the means using a sampling timing signal formed from the demodulated signal and a signal related to the clock signal. 2. The D/A converter according to claim 1, wherein the PLL circuit comprises a PLL section having a wide band for demodulation and a PLL section having a narrow band for sample and hold.