JP2000105976A - Digital audio interface signal demudulating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the circuit capable of demodulating a digital audio interface signal with a reference clock having a relatively low frequency and being not necessarily synchronized with a digital audio interface signal to be inputted without using a PLL(phase-locked loop). SOLUTION: This circuit is provided with an edge detecting circuit 1 performing the edge detection of the digital audio interface signal with both of positive edges and negative edges of the reference clock, a decision circuit 2 which obtaines a count value by the half clock of the reference clock from the output of the circuit 1 and which decides 1 to 3Ts by a table decision from this count value, a circuit 3 detecting preambles and a biphase demodulation circuit 4 performing a biphase demodulation from 1, 2Ts and the circuit can realize a demodulation circuit without using the PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio interface signal demodulation circuit for receiving a digital audio interface signal used for data transmission between digital audio devices and demodulating the digital audio signal.

[0002]

2. Description of the Related Art IEC-958 "Digital Audio Interface" is a standard for transmitting digital data between digital audio devices such as a compact disk (CD), a digital audio tape recorder (DAT), and a mini disk (MD). The outline of this standard is described below.

FIG. 9 is a timing chart showing an outline of a digital audio interface standard. The figure shows the configuration of a data unit called a subframe of this standard. Each subframe is composed of 32 bits, and its contents are composed of a 4-bit preamble, 4-bit spare bits, 20-bit audio sample information, and 4-bit additional information. Additional information is a validity flag V,
It consists of user bits U, channel status C, and parity P.

[0004] Since one sample of audio data of a CD or DAT consists of two channels, a left channel and a right channel, two sub-frames of channel 1 and channel 2 form a set and constitute one sample. The frame period corresponds to exactly one sampling frequency.

[0005] The preamble is used to indicate the synchronization of subframes at the time of transmission. In order to obtain a unique pattern, modulation including 3T is performed at the beginning, and three types of patterns of B, M, and W are used. 1 for synchronization of additional information
The beginning of a block of 92 samples, channel 1 and channel 2 are shown.

The audio sample information, spare bits and additional information are bi-phase mark modulated, and are composed of only 1T and 2T.

As a circuit for receiving a signal based on this standard, there is a digital audio interface signal demodulation circuit disclosed in JP-A-1-49177 or JP-A-2-7720.

[0008] Such a conventional digital audio interface signal demodulation circuit will be described below.

FIG. 10 is a block diagram of a conventional demodulation circuit for demodulating a digital audio interface signal. The operation will be described below with reference to FIG.

Reference numeral 101 denotes a preamble detection circuit. A 3T periodic signal in the digital audio interface signal s1001 is detected and a preamble detection signal s100 is detected.
2 is output.

Reference numeral 102 denotes a PLL circuit. The phase is locked to the preamble detection signal s1002, and a synchronous clock s1003 whose frequency is 32 times is output.

Reference numeral 103 denotes a biphase demodulation circuit. Bi-phase demodulation of the digital audio interface signal s1001 is performed using the synchronous clock s1003, and a digital audio signal s1004 is output.

FIG. 11 is an operation timing chart of the conventional demodulation circuit. Hereinafter, the operation will be described in detail with reference to FIG.

The preamble detection circuit 101 uses a reference clock s1000 having a period shorter than the minimum inversion interval of the digital audio interface signal s1001 for 2.5T.
By detecting the above inversion interval, the preamble detection signal s10
02 is output.

The PLL circuit 102 forms a phase-locked loop (PLL) using a VCO, compares the frequency of the VCO divided by 32 with the phase of a preamble detection signal s1002, and outputs a synchronous clock s1003 having a 32 times frequency.

The bi-phase demodulation circuit has a synchronous clock s
In step 1003, the digital audio interface signal is punched out, and if it is different from the immediately preceding one, 1 is output.

As described above, the demodulation of the biphase mark signal is performed by detecting the preamble and using the analog PLL to generate a clock synchronized with the digital audio interface signal.

[0018]

However, the conventional digital audio signal demodulation circuit requires a PLL to generate a synchronous clock, and includes analog circuits such as a VCO and a low-pass filter. There is also a problem that two asynchronous clocks, a reference clock and a PLL clock, are required. These are especially LS
This has been an obstacle to securing stability and reliability during I-ization, miniaturization, and ease of testing.

An object of the present invention is to solve the above-mentioned conventional problems, and to demodulate a digital audio interface signal with a relatively low frequency reference clock which is not necessarily synchronized with an input digital audio interface signal without using a PLL. It is an object of the present invention to provide a circuit capable of performing the following.

[0020]

In order to achieve this object, a digital audio interface signal demodulation circuit of the present invention performs edge detection of a digital audio interface signal at both positive and negative edges of a reference clock.
A count value at a half clock of the reference clock is obtained from this output, and a demodulation output is obtained from this count value by table determination, thereby performing highly accurate demodulation using only a low frequency reference clock without using a PLL. be able to.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital audio interface signal demodulation circuit according to the present invention receives the digital audio interface signal and uses a reference clock that is shorter than half the minimum inversion period of the input signal and that is not necessarily synchronized with the input signal. A first punching signal obtained by punching the digital audio interface signal and a first inverted punching signal obtained by punching the digital audio interface signal using the inverted clock of the reference clock and further generating the first punched signal using the inverted clock, An edge is detected and an edge detection signal is output.
An edge detection circuit that outputs a second half detection signal obtained by performing an exclusive OR operation of the punching signal and the first inverted punching signal, and the edge detection signal and the second half detection signal that are input, and an edge detection signal is input. In each case, the value obtained by counting the edge detection signal with the reference clock is obtained.
Further, if the immediately preceding second half detection signal is input, a half clock count value is calculated by subtracting 1 and the half clock count value is compared with a predetermined table to obtain the modulation period 1T, 2T, 3T. A determination circuit that outputs a determination signal, a preamble detection circuit that receives the determination signal, detects the pattern of the preamble, and outputs a preamble detection signal, and receives the preamble detection signal and the determination signal, and receives a preamble detection signal And a bi-phase demodulation circuit that demodulates and outputs a digital audio signal from the determination signal with reference to the timing reference.

Further, the digital audio interface signal demodulation circuit of the present invention, wherein the digital audio interface signal is inputted, and the first digital audio interface signal is punched out by the reference clock.
, A second punching signal obtained by further punching out the first punching signal with the reference clock, and a first inversion punching out a digital audio interface signal with the inverted clock of the reference clock and punching further with the reference clock A punch signal and a second inverted punch signal obtained by further punching the first inverted punch signal with a reference clock are generated, and the first punch signal, the first inverted punch signal, and the second punch signal are added. To obtain a first carry signal, add the first inverted punching signal, the second punched signal, and the second inverted punched signal to obtain a second carry signal, and detect an edge of the first carry signal. And outputs an edge detection signal, and outputs a second half detection signal obtained by taking an exclusive OR of the first carry signal and the second carry signal. The edge detection circuit with noise removal, the edge detection signal and the latter half detection signal are input, and every time the edge detection signal is input, a value obtained by counting the edge detection signal with the reference clock is obtained. If the second half detection signal is input to the multiplied value, 1
Further, if the immediately preceding second half detection signal is input, the half clock count value obtained by subtracting 1 from the calculated half clock count value is compared with a predetermined table to obtain the modulation period of 1T, 2T, A determination circuit that outputs a 3T determination signal, a preamble detection circuit that receives the determination signal, detects the preamble pattern, and outputs a preamble detection signal, and receives the preamble detection signal and the determination signal, A bi-phase demodulation circuit for demodulating and outputting a digital audio signal from the determination signal with the detection signal as a timing reference.

Also, the digital audio interface signal demodulation circuit of the present invention receives the digital audio interface signal, and outputs the digital audio interface signal with a reference clock having a frequency higher than the minimum inversion frequency of the input signal and not necessarily synchronized with the input signal. And a first punched-out signal punched out of the reference clock and a digital audio interface signal punched out with the inverted clock of the reference clock, and a first inverted punched-out signal punched out with the reference clock are generated, and the edge of the first punched signal is detected. An edge detection circuit that outputs an edge detection signal, and outputs a second half detection signal obtained by performing an exclusive OR operation of the first punching signal and the first inverted punching signal; 3 of all required sampling frequencies A frequency detection circuit for detecting a signal width of an edge detection signal corresponding to a signal, and outputting a sampling frequency detection signal depending on whether each period is twice as long as the sampling frequency; And the sampling frequency detection signal are input. Each time the edge detection signal is input, a value obtained by counting the edge detection signal with the reference clock is obtained, and a second half detection signal is input for a value obtained by doubling this value. If the half-clock count value obtained by calculating the half-clock count value obtained by subtracting 1 from the immediately preceding second-half detection signal is subtracted for each sampling frequency indicated by the sampling frequency detection signal, A determination circuit that outputs a determination signal of the modulation period 1T, 2T, 3T by comparing with a predetermined table; Enter a constant signal,
A preamble detection circuit that detects the pattern of the preamble and outputs a preamble detection signal; and inputs the preamble detection signal and the determination signal, and demodulates and outputs a digital audio signal from the determination signal based on the preamble detection signal as a timing reference. And a bi-phase demodulation circuit.

Further, the digital audio interface signal demodulation circuit of the present invention, wherein the digital audio interface signal is inputted, and the first digital audio interface signal is punched out by the reference clock.
, A second punching signal obtained by further punching out the first punching signal with the reference clock, and a first inversion punching out a digital audio interface signal with the inverted clock of the reference clock and punching further with the reference clock A punch signal and a second inverted punch signal obtained by further punching the first inverted punch signal with a reference clock are generated, and the first punch signal, the first inverted punch signal, and the second punch signal are added. To obtain a first carry signal, add the first inverted punching signal, the second punched signal, and the second inverted punched signal to obtain a second carry signal, and detect an edge of the first carry signal. And outputs an edge detection signal, and outputs a second half detection signal obtained by taking an exclusive OR of the first carry signal and the second carry signal. An edge detection circuit with noise removal and the edge detection signal, and detects a signal width of an edge detection signal corresponding to a 3T signal of all sampling frequencies required for demodulation, and each cycle is twice the sampling frequency. A frequency detection circuit that outputs a sampling frequency detection signal depending on whether or not the cycle is a period, and the edge detection signal, the second half detection signal, and the sampling frequency detection signal are input, and the reference clock is input each time the edge detection signal is input. The value obtained by counting the edge detection signal is obtained, and 1 is added to a value obtained by doubling this value if the second half detection signal is input, and 1 is subtracted if the immediately preceding second half detection signal is input. The half clock count value obtained by calculating the half clock count value is used as the sampling frequency indicated by the sampling frequency detection signal. 1T modulation period by comparing with a predetermined table for each number, 2T,
A determination circuit that outputs a 3T determination signal, a preamble detection circuit that receives the determination signal, detects the pattern of the preamble, and outputs a preamble detection signal, and receives the preamble detection signal and the determination signal, A bi-phase demodulation circuit for demodulating and outputting a digital audio signal from the determination signal with the detection signal as a timing reference.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram of a digital audio interface signal demodulation circuit according to an embodiment of the present invention. The operation will be described below with reference to FIG.

Reference numeral 1 denotes an edge detection circuit. Digital audio signal s101 at the positive edge of reference clock s100
Are output, and a second half detection signal s103 indicating that the edge of the digital audio interface signal s101 is present in the second half of the reference clock s100.

Reference numeral 2 denotes a judgment circuit. Edge detection signal s1
Each time 02 is input, a value obtained by counting the interval of the edge detection signal with the reference clock s100 is obtained, and 1 is added to a value obtained by doubling this value if the second half detection signal s103 is input, and furthermore, If the second half detection signal is input, a half clock count value obtained by subtracting 1 is calculated. This half clock count value is stored in a predetermined table, for example, 4
To 9, or 10 to 15, or 16 to 22
1T, 2T, 3T are determined by comparing with
The judgment signal s104 is output.

Reference numeral 3 denotes a preamble detection circuit. 1T,
From the 2T and 3T determination signals s104 to 3113 and 331
When detecting any one of the three types of determination signal sequences, i.e., 1, 3212, it outputs a preamble detection signal s105.

Reference numeral 4 denotes a biphase demodulation circuit. Based on the preamble detection signal s105, 2
By outputting 0 when T is input and outputting 1 when 1T is output twice in succession, the digital audio signal s10 is output.
6 is demodulated and output.

The reference clock s100 may be any frequency higher than half the minimum inversion period (1T) of the digital audio interface signal s101. For example, 1
A clock such as 6.9344 MHz can be used.

FIG. 2 is an example of a circuit diagram of the edge detection circuit 1.

Assuming that a signal obtained by punching out the digital audio interface signal s101 at the positive edge of the reference clock s100 is q1 and a signal punched out at the negative edge of the reference clock s100 is nq1 and that the signal is nq1. It is generated by exclusive OR of q1 and a signal obtained by punching out q1 at the positive edge. The second half detection signal s103 is generated by an exclusive OR of q1 and nq1.

FIG. 3 is an operation timing chart of the edge detection circuit 1 and the judgment circuit 2. Hereinafter, the operation will be described in detail with reference to FIG.

With respect to the reference clock s100, the digital audio interface signal s101 is shown by A, B,
It is assumed that the input is performed as 6, 7, 6, 7, and 12 by counting at half the clock of the reference clock s100 like C, D, and E. In the edge detection circuit 1, a signal punched out at the positive edge of the reference signal s100 and a signal punched out at the negative edge and then punched out at the positive edge have waveforms such as q1 and nq1, respectively. The edge detection signal s102 that detects the edge of q1 is output for each edge as shown in the figure. q
2 and the latter half detection signal s1 obtained from the exclusive OR of nq1
03 is output when there is a transition in the latter half of the reference clock as in B and C in the figure.

In the determination circuit 2, the count value c (t) of the edge interval of s102 and the value p (t) of the second half detection signal s103 are obtained.
The half clock count value n (t) is given by the following equation from the previous half-detection signal value p (t-1).

N (t) =-p (t-1) + 2.times.c
(T) + p (t) where p is 1 or 0. Therefore, for the input of A, since the count value is 3 and the second half detection signal s103 is not raised, n = 6. For the input of B, the count value is 3 and the latter half detection signal s103 has now risen, so n = 7. C
, The count value is 3 and the latter half detection signal s1
Since both 03 are standing, n = 6. Similarly, D is n =
7. E becomes n = 12. These values are output as determination signals s104 as 1T, 1T, 1T, 1T, and 2T, respectively, by table determination.

FIG. 4 is an operation timing chart of the preamble detection circuit 3 and the biphase demodulation circuit 4. Hereinafter, FIG.
The details of the operation will be described with reference to FIG.

The preamble detection circuit 3 outputs a judgment signal s10
4 to 3113, 3311, and 3212, and detects a preamble pattern of any of the three types, and outputs a preamble detection signal s105. Preamble detection signal s
When the preamble pattern is detected, the signal 105 goes to the L level, and the digital audio interface signal 2
After the 8th bit, it is generated by setting it to the H level.
The L period is a portion subjected to the biphase mark modulation.

The bi-phase demodulation circuit 4 obtains demodulated data by outputting 0 for 2T and 1 for 1T two consecutive times from the point where the preamble detection signal s105 has become L level. The audio data is separated from the demodulated data to output a digital audio signal s106.

As described above, according to the present invention, the edge detection of the digital audio interface signal is performed at both the positive and negative edges of the reference clock, and the count value at the half clock of the reference clock is obtained from this output. With a configuration in which a demodulated output is obtained by table determination, demodulation can be performed using only a low-frequency reference clock without using a PLL. (Embodiment 2) FIG. 5 is a block diagram of a digital audio interface signal demodulation circuit according to an embodiment of the present invention. The operation will be described below with reference to FIG.

Reference numeral 51 denotes an edge detection circuit with noise elimination. An edge detection signal s102 for detecting an edge of a signal obtained by majority decision of a signal obtained by detecting the edge of the digital audio signal s101 with three positive, negative and positive edges of the reference clock s100, and a negative, positive and negative of the reference clock s100. A second half detection signal s103 indicating that the center of the edge change is the second half of the reference clock s100 is output from the signal that has been determined by majority decision on the signal that has detected the edge of the digital audio interface signal s101 at three edges.

Reference numeral 52 denotes a frequency detection circuit. All sampling frequencies that require demodulation, e.g.
The signal width of the edge detection signal corresponding to each of the 3T signals of 4.1 kHz and 48 kHz is detected, and 32 bits are determined depending on whether each cycle is twice the sampling frequency.
It detects whether the frequency is kHz, 44.1 kHz or 48 kHz, and outputs a sampling frequency detection signal s107.

Reference numeral 2 denotes a judgment circuit. Edge detection signal s1
Each time 02 is input, a value obtained by counting the interval of the edge detection signal with the reference clock s100 is obtained, and 1 is added to a value obtained by doubling this value if the second half detection signal s103 is input, and furthermore, If the second half detection signal is input, a half clock count value obtained by subtracting 1 is calculated. The half clock count value is compared with a predetermined determination table for each sampling frequency indicated by the sampling frequency detection signal s107, thereby obtaining 1T, 2T, and 3T, respectively.
And outputs a determination signal s104.

Reference numeral 3 denotes a preamble detection circuit. 1T,
From the 2T and 3T determination signals s104 to 3113 and 331
When detecting any one of the three types of determination signal sequences, i.e., 1, 3212, it outputs a preamble detection signal s105.

4 is a bi-phase demodulation circuit. Based on the preamble detection signal s105, 2
By outputting 0 when T is input and outputting 1 when 1T is output twice in succession, the digital audio signal s10 is output.
6 is demodulated and output.

The reference clock s100 may be any frequency higher than half the minimum inversion period (1T) of the digital audio interface signal s101. For example, 1
A clock such as 6.9344 MHz can be used.

FIG. 6 shows an edge detection circuit 51 with noise elimination.
3 is an example of a circuit diagram of FIG.

A signal obtained by punching out the digital audio interface signal s101 at the positive edge of the reference clock s100 is denoted by q1, and a signal punched out at the positive edge is denoted by q2. A signal punched out at the negative edge of the reference clock s100 is replaced by a signal
q1 and a signal punched out at the positive edge is denoted by n
q2. Carry c1 is obtained by adding q1, nq1, and q2 in a full adder, and carry c2 is obtained by adding nq1, q2, and nq2 in a full adder. The edge detection signal s102 is generated by an exclusive OR of c1 and a signal obtained by punching out c1 with a positive edge. Also, the second half detection signal s
103 is generated by the exclusive OR of c1 and c2.

FIG. 7 shows an edge detection circuit 51 with noise elimination.
FIG. 5 is an operation timing chart of the determination circuit 2. Hereinafter, the details of the operation will be described with reference to FIG.

The digital audio interface signal s101 is compared with the reference clock s100 by A, B,
It is assumed that the input is like C, D, E. This is an example of a case where there is fluttering of a signal at an edge between A and B and between C and D, and a whisker-like noise is present at the center of E.

In the edge detection circuit 51 with noise elimination, the signal punched out at the positive edge of the reference signal s100 and the signal punched out at the negative edge and repunched at the positive edge have waveforms such as q1 and nq1, respectively. q1 and nq1
Are further q2 and n
q2. The carry output c1 obtained by adding q1, nq1, and q2 by a full adder is a majority output that becomes H when any two or more of the three signals are at the H level. nq
The same applies to carry output c2 obtained by adding 1, q2, and nq2 in a full adder. In order to facilitate understanding, c1 and c2 have the same waveforms as q1 and nq1 when the digital audio interface signal s101 in FIG. 7 is delayed by half a clock with respect to the reference clock s100. This is equivalent to the above-mentioned operation of the edge detection circuit with noise 51 taking an average at three points delayed by half a clock of the reference clock s100. To come. The edge detection signal s102 that detects the edge of c1 is output for each edge as shown in the figure. The latter half detection signal s103 obtained from the exclusive OR of c1 and c2 is output when the average transition of three points comes in the latter half of the reference clock as shown in A, D, and E in the figure.

In the judgment circuit 2, the count value c (t) of the edge interval of s102 and the value p (t) of the second half detection signal s103 are obtained.
The half clock count value n (t) is given by the following equation from the previous half-detection signal value p (t-1).

N (t) = − p (t−1) + 2 × c
(T) + p (t) where p is 1 or 0. Therefore, for the input of A, since the count value is 3 and the second half detection signal s103 is both standing, n = 6. With respect to the input of B, n = 7 because the count value is 4 and the latter half detection signal s103 has been set only last time. For the input of C, n = 6 because the count value is 3 and the second half detection signal s103 does not rise. Similarly, D is n = 7. E becomes n = 12.

The frequency detection circuit 52 generates an edge detection signal s
From 102, 3 of all sampling frequencies that need demodulation
A signal width corresponding to the T signal is detected. For example, 32 kHz
Signal widths of 11 to 15 for z, 8 to 10 for 44.1 kHz and 48 kHz are detected. 32k depending on whether each period is twice the sampling frequency
Hz, 44.1 kHz or 48 kHz, and outputs a sampling frequency detection signal s107. It should be noted that a half clock count value n (t) of the determination circuit 2 may be used to detect the 3T signal.

FIG. 8 shows an example of the judgment table of the judgment circuit 2. The half clock count value n obtained by the determination circuit 2 in FIG. 7 is 32 kHz in FIG. 8 according to the sampling frequency detection signal s107 output from the frequency detection circuit 52.
The determination is made using any table from z to 48 kHz. For example, assuming that the frequency is 44.1 kHz, it is determined as 1T, 1T, 1T, 1T, 2T by the determination table, and is output as the determination signal s104.

The operations of the preamble detection circuit 3 and the biphase demodulation circuit 4 are exactly the same as in the first embodiment.
The preamble detection circuit 3 determines from the determination signal s104 that
13, 3311, and 3212, and detects a preamble pattern of any of the three types to obtain a preamble detection signal s1.
05 is output. The preamble detection signal s105 is generated by going low when a preamble pattern is detected, and going high when 28 bits of the digital audio interface signal have passed. The L period is a portion subjected to the biphase mark modulation.

The biphase demodulation circuit 4 obtains demodulated data by outputting 0 for 2T and 1 for 2T consecutively from the point where the preamble detection signal s105 becomes L level. The audio data is separated from the demodulated data to output a digital audio signal s106.

As described above, according to the present invention, a correct digital audio signal can be demodulated by adding an addition circuit to the edge detection circuit, even if there is some noise in the edge of the digital audio interface signal or in the middle of the signal. can do.

Further, according to the present invention, the digital audio interface signals of various sampling frequencies can be demodulated by switching the judgment table in accordance with the 3T cycle of the edge detection signal. Also,
By providing the table with a width, the digital audio signal has resistance to frequency deviation and duty deviation.

[0060]

As described above, according to the present invention, the edge detection of the digital audio interface signal is performed using both the positive and negative edges of the reference clock, and the count value at the half clock of the reference clock is obtained from this output. By employing a configuration in which a demodulated output is obtained from a value by table determination, demodulation can be performed using only a low-frequency reference clock without using a PLL.

By eliminating the need for an analog circuit such as a PLL or LPF, the circuit can be downsized and a digital audio interface signal demodulation circuit with stable operation can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital audio interface signal demodulation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit diagram of an edge detection circuit 1.

FIG. 3 is an operation timing chart of an edge detection circuit 1 and a determination circuit 2.

FIG. 4 is an operation timing chart of a preamble detection circuit 3 and a biphase demodulation circuit 4;

FIG. 5 is a block diagram of a digital audio interface signal demodulation circuit according to one embodiment of the present invention.

FIG. 6 is a diagram showing an example of a circuit diagram of an edge detection circuit with noise removal 51;

FIG. 7 is an operation timing chart of the edge detection circuit with noise elimination circuit 51 and the determination circuit 2;

FIG. 8 is a diagram illustrating an example of a determination table of a determination circuit 2.

FIG. 9 is a timing chart showing an outline of a digital audio interface standard.

FIG. 10 is a block diagram of a conventional demodulation circuit for demodulating a digital audio interface signal.

FIG. 11 is an operation timing chart of a conventional demodulation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Edge detection circuit 2 Judgment circuit 3 Preamble detection circuit 4 Biphase demodulation circuit 51 Edge detection circuit with noise removal 52 Frequency detection circuit

Claims (4)

[Claims] 1. A demodulation circuit for adding a preamble and additional information to a digital audio signal, demodulating a digital audio interface signal transmitted by bi-phase modulation, and receiving the digital audio interface signal. A first punched signal obtained by punching out a digital audio interface signal with a reference clock that is shorter than half of the minimum inversion period of the digital audio interface and that is not necessarily synchronized with an input signal; A first inverted punching signal punched by a clock is generated, an edge of the first punching signal is detected, an edge detection signal is output, and an exclusive logic of the first punching signal and the first inverted punching signal is generated. Output the second half detection signal The edge detection circuit to be input, the edge detection signal and the second half detection signal are input, a value obtained by counting the edge detection signal with the reference clock every time the edge detection signal is input, and this value is doubled. If the second half detection signal is input, 1 is added to the value, and if the immediately preceding second half detection signal is input, 1 is subtracted to calculate a half clock count value, and the half clock count value is set in a predetermined table. A determination circuit that outputs a determination signal of a modulation period of 1T, 2T, 3T by comparing with a preamble detection circuit that receives the determination signal, detects the pattern of the preamble, and outputs a preamble detection signal; A preamble detection signal and a determination signal are input, and a digital audio signal is demodulated from the determination signal with the preamble detection signal as a timing reference. Digital audio interface signal demodulating circuit and a biphase demodulation circuit to output. 2. A demodulation circuit for adding a preamble and additional information to a digital audio signal, demodulating a digital audio interface signal transmitted by bi-phase modulation, and receiving the digital audio interface signal, A first punching signal obtained by punching a digital audio interface signal by a clock, a second punching signal obtained by punching the first punching signal by the reference clock, and a digital audio interface signal punched by an inverted clock of the reference clock. And generating a first inverted punching signal further punched by the reference clock and a second inverted punching signal further punched out of the first inverted punching signal by the reference clock,
Adding a first punching signal, a first inverted punching signal, and a second punching signal to obtain a first carry signal;
Adding a first inverted punching signal, a second punching signal, and a second inverted punching signal to obtain a second carry signal, detecting an edge of the first carry signal, and outputting an edge detection signal; An edge detection circuit with noise elimination that outputs a second half detection signal obtained by performing an exclusive OR operation of the first carry signal and the second carry signal; inputting the edge detection signal and the second half detection signal to detect an edge; Each time a signal is input, a value obtained by counting the edge detection signal with the reference clock is obtained, and 1 is added to a value obtained by doubling this value if a second half detection signal is input, and further, the immediately preceding second half detection signal is added. Is input, a half clock count value obtained by subtracting 1 is calculated, and the half clock count value obtained is compared with a predetermined table to output a determination signal of the modulation period 1T, 2T, 3T. A preamble detection circuit that inputs the judgment signal, detects the pattern of the preamble and outputs a preamble detection signal, and inputs the preamble detection signal and the judgment signal, and sets the preamble detection signal as a timing reference. And a bi-phase demodulation circuit for demodulating and outputting a digital audio signal from the determination signal. 3. A demodulation circuit for adding a preamble and additional information to a digital audio signal, demodulating a digital audio interface signal transmitted by bi-phase modulation, and receiving the digital audio interface signal. A first punched signal obtained by punching a digital audio interface signal at a frequency higher than the minimum inversion frequency of the reference signal and not necessarily synchronized with the input signal, and a digital audio interface signal punched at the inverted clock of the reference clock and further with the reference clock. A first inverted punching signal that has been punched out is generated, an edge of the first punching signal is detected, an edge detection signal is output, and an exclusive OR of the first punching signal and the first inverted punching signal is calculated. Output second half detection signal And an edge detection circuit that receives the edge detection signal, detects a signal width of an edge detection signal corresponding to a 3T signal of all sampling frequencies that need demodulation, and sets each cycle to be equal to the sampling frequency of 2T.
A frequency detection circuit that outputs a sampling frequency detection signal depending on whether the period is doubled, and the edge detection signal, the second half detection signal, and the sampling frequency detection signal are input, and the reference is input each time the edge detection signal is input. The value obtained by counting the edge detection signal by the clock is obtained, and 1 is added to a value obtained by doubling this value if the second half detection signal is input, and 1 is subtracted if the immediately preceding second half detection signal is input. The half-clock count value obtained by calculating the half-clock count value is compared with a predetermined table for each sampling frequency indicated by the sampling frequency detection signal to output a determination signal for the modulation period 1T, 2T, 3T. A determination circuit for inputting the determination signal, detecting a pattern of the preamble and outputting a preamble detection signal A digital audio interface signal demodulation circuit comprising: a preamble detection circuit; a bi-phase demodulation circuit for receiving the preamble detection signal and the determination signal; circuit. 4. A demodulation circuit for adding a preamble and additional information to a digital audio signal, demodulating a digital audio interface signal transmitted by bi-phase modulation, and receiving the digital audio interface signal, A first punching signal obtained by punching a digital audio interface signal by a clock, a second punching signal obtained by punching the first punching signal by the reference clock, and a digital audio interface signal punched by an inverted clock of the reference clock. And generating a first inverted punching signal further punched by the reference clock and a second inverted punching signal further punched out of the first inverted punching signal by the reference clock,
Adding a first punching signal, a first inverted punching signal, and a second punching signal to obtain a first carry signal;
Adding a first inverted punching signal, a second punching signal, and a second inverted punching signal to obtain a second carry signal, detecting an edge of the first carry signal, and outputting an edge detection signal; An edge detection circuit with noise elimination that outputs a second half detection signal obtained by performing an exclusive OR operation of the first carry signal and the second carry signal; and all the sampling frequencies for which the edge detection signal is input and demodulation is required. , The signal width of the edge detection signal corresponding to the 3T signal of
A frequency detection circuit that outputs a sampling frequency detection signal depending on whether the period is doubled, and the edge detection signal, the second half detection signal, and the sampling frequency detection signal are input, and each time the edge detection signal is input, the reference The value obtained by counting the edge detection signal by the clock is obtained, and 1 is added to a value obtained by doubling this value if the second half detection signal is input, and 1 is subtracted if the immediately preceding second half detection signal is input. By comparing the half clock count value obtained by calculating the calculated half clock count value with a predetermined table for each sampling frequency indicated by the sampling frequency detection signal, a determination signal of the modulation period 1T, 2T, 3T is output. A determination circuit for inputting the determination signal, detecting a pattern of the preamble and outputting a preamble detection signal A digital audio interface signal demodulation circuit comprising: a preamble detection circuit; a bi-phase demodulation circuit for receiving the preamble detection signal and the determination signal; circuit.