JPH0362060B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention makes it possible to significantly reduce demodulation sensitivity to low-order harmonic components of subcarriers and to improve separation.
Regarding FM stereo demodulation circuit.

As is well known, in principle, analog multiplication of a composite signal and a sine wave signal maintaining a subcarrier (38 KHz) frequency is desirable in an FM stereo demodulation circuit. However, in reality, it is difficult to obtain an ideal analog multiplier circuit in terms of its linearity, etc. Therefore, conventionally, a switching method using a rectangular wave as shown in FIG. 2 has been simply used.

In Figure 1, a composite signal C(t) is branched into two systems and given to two multiplier elements TR ₁ and TR ₂ , and these elements TR ₁ and TR ₂ are connected to an oscillation circuit OSC (usually a PLL output). and is synchronized with the pilot signal.) 38KHz output from
The composite signal C(t) and the switching signal s(t) are operated alternately and symmetrically by the switching signal s(t), and the result of this multiplication is further passed through the low-pass filters F ₁ and F ₂ . The audio signals L and R are taken out.

Here, as the switching signal s(t), a rectangular wave with a duty ratio of 50% as shown in FIG. 2 is normally used. Demodulated output C in this case
(t)·s(t) is expressed by equation (1).

C(t)・s(t)=C(t)×{(1/2
)±(2/π)cosωt±(2/3π) cos3ωt……±(2/5π)cos5ωt±……
}...(1) As is clear from equation (1), when the composite signal C(t) includes frequency components such as 3ω and 5ω, it has demodulation sensitivity to these frequency components themselves. become. In other words, if a square wave with a duty ratio of 50% is used as the switching signal s(t), for example, 114KHz, (38KHz x 3),
Even for an input signal of 190KHz (38KHz x 5), it has a large demodulation sensitivity as shown in Figure 3, and the FM detection output has a high demodulation sensitivity of 3ω, 5ω (however, ω
If a frequency component such as 38KHz) is included, this will cause effects such as deterioration of the S/N ratio and beat interference.

Therefore, a method is used to attenuate these bands with a filter in advance, but this method reduces the flatness (both amplitude and phase) between 53KHz, which is the subcarrier region, and the stereo after demodulation There was a problem that the frequency characteristics of the separation deteriorated.

Therefore, the present applicant previously proposed in Japanese Patent Application No. 167744/1983 that the multiplicand signal to be multiplied by the composite signal was a stepped pseudo sine wave formed by a combination of a resistor ladder circuit and an analog multiplexer. A stereo demodulation circuit is proposed.

FIG. 4 shows an example of such an FM stereo demodulation circuit. In the figure, 1 is a phase detector (hereinafter referred to as PD), 2 is a buffer amplifier, and 3 is a voltage controlled oscillator (hereinafter referred to as PD).
4 is a BCD/U/D counter, 5 is a BCD/DEC decoder, 6 is an RS flip-flop, 7, 8 and 9 are NAND circuits, 10,
11 and 12 are D-type flip-flops, 13 is a series resistance ladder consisting of resistors _R1 to _R7 , and SW1 to _R7 .
SW ₈ , SW ₁ ′ to SW ₈ ′ are analog switches.

According to the above configuration, the VCO 3 outputs a 532 KHz clock signal as shown in FIG. 5, and the decoder 5 supplies switching pulses as shown in FIG. The switching pulses output from the output terminals Q ₀ to _{Q 7} of the decoder 5 are among the divided voltage outputs in the resistor ladder 13.
Analog switches, namely SW ₁ and
It is simultaneously supplied to SW ₁ ′, SW ₂ and SW ₂ ′, and SW ₃ and SW ₃ ′.

As a result, if a constant voltage is temporarily applied across the resistor ladder 13, the output terminals OUTL and OUTR
Assuming that the multiplicand signal is output at the output terminal OUTL, as shown in Fig.
SR(t) is output to OUTR as a multiplicand signal.

As is clear from the figure, these multiplicand signals each have a frequency of 38KHz and are mutually exclusive.
It has a phase difference of 180 degrees. Furthermore, the waveforms of these multiplicand signals SL(t) and SR(t) are the same as those of the resistance ladder 13.
By appropriately determining the values of the resistors R ₁ to R ₇ that constitute the waveform, it is possible to set the waveform to any desired waveform.

FIG. 6 shows a case where the respective resistance values R ₁ to R ₇ are set as shown below, and the waveforms of the multiplicand signals SL(t) and SR(t) are made into sine wave shapes.

R ₁ = R ₇ = 1KΩ R ₂ = R ₆ = 2KΩ R ₃ = R ₅ = 3KΩ R ₄ = 4KΩ Figure 7 shows the demodulated output when a pseudo sine wave as shown in Figure 6 is used as the multiplicand signal. It is a graph showing each frequency component of (sensitivity). As is clear from Figure 7, if ω = 38KHz,
Compared to the ω component of the fundamental wave, the third harmonic 3ω component can be attenuated by 40 dB.

In this way, according to the stereo demodulation circuit shown in FIG. 4, unlike the conventional example that uses a non-linear performance element as a multiplication means, it is possible to accurately multiply a composite signal by a signal having an arbitrary waveform. Therefore, if the number of voltage division levels is increased to make the waveform of the pseudo sine field signal more similar to a sine wave, an ideal stereo demodulation operation can be performed.

Moreover, according to this demodulation circuit, as mentioned above, 3
Since low-order harmonic components such as the 5th and 5th harmonics can be significantly reduced, it is no longer necessary to provide a filter to remove these components from the composite signal before the demodulation circuit, and this makes stereo separation possible. Various advantages were obtained, such as being able to solve the frequency dependence of .

Furthermore, the present applicant has previously proposed in Japanese Patent Application No. 51994/1987 a novel FM stereo demodulation circuit that improves the positive/negative symmetry of the pseudo sine wave that is the multiplicand signal.

FIG. 8 shows an example of such an FM stereo demodulation circuit. In the same figure, 14 is
PD, 15 is buffer amplifier, 16 is VCO, 17
is a BCD/U/D counter, 18 is a BCD/DEC decoder, 19 is an RS flip-flop, 20,2
1 is a NAND circuit, 22 and 23 are inverters, 2
4 is an RS flip-flop, 25 and 26 are D-type flip-flops, 27 and 29 are operational amplifiers that operate as buffer circuits, 28 and 30 are operational amplifiers with a gain of 1/2, 31 to 34 are OR circuits, and 35 is a resistor.
Resistance ladder consisting of R ₁₁ ~ R ₄₄ , 36 is resistor R ₁₁ ′ ~
Resistance ladder consisting of R ₄₄ ′, SW ₁₁ to _{SW 44} ,
SW ₁₁ ' to SW ₄₄ ' are analog switches.

Further, FIG. 9 is a waveform diagram showing the signal states of each part of the circuit shown in FIG. 8.

According to the above configuration, the positive and negative half waves of SL(t) and SR(t), which are the multiplicand signals in FIG. The positive/negative symmetry was reliably maintained, and therefore the even-order harmonic components of the demodulated output (sensitivity) could be significantly reduced.

As described above, the FM stereo demodulation circuit using the pseudosine multiplicand method developed by the applicant has the effect of significantly reducing demodulation sensitivity to low-order harmonic components of subcarriers and improving separation. It was done.

Next, in addition to the series of applications related to pseudo-sine wave multiplication mentioned above, the present applicant has previously proposed in Japanese Patent Application No. 101729/1983 a direct current method as a method for improving stereo separation in a switching type FM stereo demodulation circuit. We propose a new FM stereo demodulation circuit that multiplies a shifted square wave and a composite signal.

The demodulated signal derived to the left output terminal L of this stereo demodulation circuit is C(t)·(1+2sinωct).

Also, the value of the composite signal C(t) is C
It is expressed as (t)=L+R+(L−R) sinωct.

Therefore, the above fL(t) becomes fL(t)={L+R+(L-R)sinωct} ×(1+2sinωct) =L(2+3sinωct−cos2ωct) +R(+cos2ωct−sinωct), and from this, the audio component is converted to LPF. If we extract it using

Similarly, if the composite signal C(t) is multiplied by (1-2sinωct), fR(t) = {L+R+(L-R)sinωct} × (1+2sinωct) = L(cos2ωct-sinωct) +R (2-3sinωct-cos2ωct) From this, if the audio signal is extracted using the LPF, fL(t)=2R, which proves that the crosstalk component from the right side system is completely removed.

Next, each multiplier signal (1+2sinωct) described above,
A specific method of multiplying the composite signal C(t) by (1-2 sin ωct) will be explained.

As shown in Figure a, when a rectangular wave with a positive level K2 and a negative level K1 is expressed as a Fourier series, as is well known, f(t) = (1/2) (-K1 + K2) + Σ (1 /πn)(K1+K2) (1−cosnπ)sinωct.

Here, in order for f(t) to have a component of (1+2sinωct), (2/π)(K1+K2)=-K1+K2, so K1/K2=(π-2)/(π+2)=0.222. Become. And in this case, f(t)=2・{K2/(π+2)}・{1+2s
inωct+(2/3)sin3ωct+...}.

Similarly, as shown in Figure b, the Fourier series of the waveform shifted by half a period from the above waveform is F(t)=2・{K2/(π+2)}・{1−2s
inωct - (2/3) sin3ωct...} Therefore, if the multiplier circuit is multiplied by a rectangular wave as shown in Figures a and b as a multiplier signal, and the audio component is extracted from the multiplication result, then the demodulation principle described above can be used. As shown, C(t)・(1+2sinωct), C
A demodulated output of (t)·(1-2 sinωct) can be obtained.

Furthermore, the present applicant previously proposed in Japanese Patent Application No. 124612/1983 that by making the above-mentioned DC-shifted rectangular wave into a pseudo-sine shape in the same manner as described above, the S/N and distortion rate were improved as well as separation. We have proposed a new FM stereo demodulation circuit that also achieves the following.

This invention was made against the technical background explained above, and its purpose is to create a novel method for multiplying a composite signal by a pseudo sine wave.
In an FM stereo demodulation circuit, the objective is to improve the accuracy, ease of configuration, and versatility of the multiplication circuit section in particular.

In other words, in the inventions filed earlier, a normal voltage division method has been used as a resistance ladder, but in order to make this pseudo-sine wave multiplication principle work correctly, and to reduce demodulation sensitivity to unnecessary signals and improve separation. It is necessary to form an accurate pseudo-sine wave (symmetry, etc.), and therefore the accuracy of the resistance ladder becomes an issue. Furthermore, this problem becomes more serious the more attempts are made to redivide the pseudo sine wave in order to approximate it as accurately as possible to a sine wave.

On the other hand, according to the present invention, since a D-A converter is used as the multiplication circuit, accuracy is improved by using the same resistor, and the IC
In addition, since the waveform can be arbitrarily set using digital codes rather than resistance values, it has the effect of facilitating design, adjustment, modification, etc.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 12 shows an embodiment of the stereo demodulation circuit according to the present invention (hereinafter referred to as the first embodiment).
FIG. In the figure, a composite signal C(t) includes at least a stereo main channel signal and a stereo subchannel signal, and this composite signal C(t) is input to the reference input terminal IN of the D-A converter 37. At the same time, the pilot signal extraction circuit 38
supplied to.

The pilot signal extraction circuit 38 extracts a 19 KHz pilot signal from the composite signal C(t) and supplies it to the PD 40 forming the PLL circuit 39.

In this example, the PLL circuit 39 includes a VCO 41, a 4-digit binary counter 42 which is step-controlled by the output of the VCO 41, and a binary counter 42.
a divider 43 that divides the MSB (Q ₃ ) of
LPF4 that extracts the low frequency components of the output of this PD40
It consists of VCO41.
is locked to 608KHz.

Outputs Q ₀ -Q ₃ of the counter 42 are supplied to address input terminals A ₀ -A ₃ of the ROM 45.

In the ROM 45, 16 consecutive addresses 0 to F specified by address signals A ₀ to A ₃ contain 8-bit data indicating the value of each instantaneous value obtained by dividing one period of the sine wave sinωct into 16 equal parts. _D0 to _D7 are stored.

Therefore, the sign input terminal of the D/A converter 37
Digital data corresponding to a 38KHz pseudo sine wave synchronized with the pilot signal in the composite signal C(t) is supplied to D0 _{to D7 .}

The D/A converter 37 is composed of an R-2R resistor ladder as shown in FIG. 13, and is configured to perform a so-called multiplication operation on the composite signal C(t), which is the reference input voltage. and its output OUT(L), OUT(R)
are complementary current outputs, and the sum of these two outputs is always a constant value.

Therefore, if the input sine wave of the D-A converter 37 is expressed as f (sinωct), the left output terminal OUT (L)
C(t)・f(sinωct) is output to the output terminal OUT(R), and C(t)・f(−
sinωct) will be output.

And these outputs are on the left and right
After removing unnecessary high frequencies (switching noise) via LPFs 46 and 47, necessary audio signals are extracted and output to left and right channel terminals Lch and Rch.

Thus, according to the first embodiment, the composite signal C(t) can be multiplied by an accurate pseudo sine wave that is symmetrical and free of distortion unlike an analog multiplier, and the D-A converter 37 uses an R-2R resistor ladder type converter, so the accuracy is good by using the same resistor, making it suitable for IC implementation, and the waveform setting is not a resistance value but a digital value. This has the advantage that it can be set arbitrarily, making design, adjustment, and modification easy.

Next, FIG. 14 is a block diagram showing the configuration of another embodiment (hereinafter referred to as the second embodiment) of the stereo demodulation circuit according to the present invention.

In this figure, the same components as those in the first embodiment are designated by the same reference numerals, and the explanation thereof will be omitted.

In addition to the effects of the first embodiment, the stereo demodulation circuit according to the second embodiment is characterized by adding (1±2sinωct) to the composite signal C(t) in order to improve the stereo separation. The reason is that it is multiplied.

In the figure, each address 0 to F of the ROM45
, 8-bit data _D0 to _D7 corresponding to each instantaneous value obtained by dividing the unipolar sine wave (1+sinωct) into 16 equal parts.
are stored in order, an example of which is shown in FIG.

Therefore, each output OUT of the D/A converter 37
(L) and OUT(R) have C(t) and (1+
sinωct) and C(t)·(1−sinωct) are output.

In addition, each output OUT of the D-A converter 37
(L) and OUT(R) are respectively supplied to left and right OP amplifiers 48 and 49 forming an adder.

Here, the output Vout ₁ of the left OP amplifier 48 is
It is added to the input of the right OP amplifier 49 via the resistor R ₂ , and the output Vout ₂ of the right OP amplifier 49 is
It is added to the input of the left OP amplifier 48 via the resistor _R1 .

Also, the value of the feedback resistor R of the left OP amplifier 48,
A relationship R ₁ =3R is set between the value of the resistor R ₁ and the value of the feedback resistor R of the right OP amplifier 49 and the value of the resistor R ₂ .
The relationship R ₂ =3R is set.

As a result, each output of OP amplifiers 48 and 49
The values of Vout ₁ and Vout ₂ are as follows.

Vout ₁ =-3・C(t)・(1+2sinωct)/4 Vout ₂ =−3・C(t)・(1−2sinωct)/4 Thus, in the stereo demodulation circuit according to the second embodiment, the above-mentioned In addition to the effect explained in the first embodiment, since the composite signal C(t) is multiplied by (1±2sinωct), the first
As explained in FIGS. 0 and 11, stereo separation can be significantly improved.

Next, FIG. 16 is a block diagram showing a more specific example (hereinafter referred to as the third embodiment) of the stereo demodulation circuit according to the present invention. Note that the numbers in parentheses attached to each circuit element in the figure indicate the number of each LSI.

In the figure, the oscillation frequency of the VCO 50 is locked to 608 KHz by a phase-locked loop that passes through a buffer amplifier 51, a waveform shaping circuit 52, a binary counter 53, a 1/2 divider 54, a PD 55, and a low-pass filter 56 in this order. ing.

On the other hand, the composite signal C(t)
A 19 KHz rectangular wave extracted from the filter 57 is supplied, and a 38 KHz rectangular wave synchronized with the pilot signal is output from the MSB ( _Q0 output) of the binary counter 53.

The 38KHz obtained from the Q ₀ output of the counter 53 is further frequency-divided via the 1/2 divider 54, and then converted to a 19KHz triangular wave via the waveform conversion circuit 60. In the adder 61 composed of an OP amplifier, the pilot signal in the composite signal C(t) is canceled.

The composite signal from which the pilot signal has been removed in the adder circuit 61 is supplied to the reference input Vref of the DA converter 62.

On the other hand, the count outputs Q ₀ to _{Q 3} of the counter 53 driven by 608KHz pulses are address signals as they are.
It is supplied to the ROM63 as A ₀ to _{A 3} , and this
At each address in the ROM 63, 8-bit digital data for each instantaneous value of a unipolar sine wave of (1+sinωct) is stored, as shown in FIG.

Each instantaneous value data read out from the ROM 63 is latched by a latch circuit 64 in response to a 608KHz pulse, and further inverted by an inverter 65, and then sent to a sign input terminal of a D-A converter 62.
It is supplied to _D0 to _D7 .

As a result, the left side output of the D-A converter 62
OUT ₁ has C(t) {1+f(sinωct)}, and right output OUT ₂ has C(t) {1-f
(sinωct)} are output respectively.

These left and right outputs OUT ₁ and OUT ₂ are
As explained in the second embodiment, K and C are
(t)・(1+2sinωct) and K・C(t)・(1−
2sinωct), the audio signals are further taken out via left and right de-emphasis circuits 68 and 69, and then sent to the left and right channel terminals via subcarrier removal circuits 70 and 71.
This means that L and R demodulated signals are output to Lch and Rch, respectively.

Thus, according to the third embodiment, it is possible to provide an FM stereo demodulation circuit in which the demodulation sensitivity to low-order harmonic components of the subcarrier is significantly reduced and the separation is significantly improved.

As is clear from the description of each of the embodiments above, the stereo demodulation circuit according to the present invention multiplies a composite signal including at least a stereo main channel signal and a subchannel signal by a switching signal having a subcarrier frequency. An FM stereo demodulation circuit comprising a multiplication means, the multiplication means including a D-A converter having a reference input terminal and a sign input terminal, and a frequency of the subcarrier with respect to the sign input terminal of the D-A converter. a code generating circuit that outputs a digital code corresponding to the instantaneous value of each step of a pseudo sine wave consisting of a staircase wave of three or more values with the fundamental wave as a fundamental wave, in synchronization with the sub-channel signal; The converter multiplies the composite signal supplied as a reference input voltage to a reference input terminal by the positive-phase component and negative-phase component of the pseudo sine wave supplied as a digital signal to a sign input terminal, respectively, and generates left and right channel signals. Therefore, the demodulation sensitivity to the lower harmonics of the subcarrier can be significantly reduced, and the separation can be significantly rotated.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the basic configuration of a conventional switching type FM stereo demodulation circuit, Figure 2 is a diagram showing the switching waveform of the circuit, Figure 3 is a graph showing the frequency characteristics of the demodulated output of the circuit, and Figure 3 is a graph showing the frequency characteristics of the demodulated output of the circuit. Figure 4 is a block diagram showing an example of the FM stereo demodulation circuit previously proposed by the applicant, Figure 5 is a waveform diagram showing the signal states of each part of the circuit in Figure 4, and Figure 6 shows an envelope shaped like a sine wave. FIG. 7 is a graph showing the frequency characteristics of the demodulated output when the pseudo sine wave and the composite signal are multiplied.
Fig. 8 is a block diagram showing an example of an FM stereo demodulation circuit previously proposed by the applicant, Fig. 9 is a waveform diagram showing signal states of each part in the circuit of Fig. 8, and Fig. 10 is a block diagram showing an example of an FM stereo demodulation circuit previously proposed by the applicant. A block diagram to explain the demodulation principle of the FM stereo demodulation circuit proposed by
11 is a waveform diagram showing left and right multiplicand signal waveforms in the circuit of FIG. 10, FIG. 12 is a block diagram showing a first embodiment of the stereo demodulation circuit according to the present invention, and FIG. Fig. 14 is a block diagram showing the second embodiment of the FM stereo demodulation circuit according to the present invention, and Fig. 15 corresponds to a unipolar pseudo sine wave of (1+sinωct). FIG. 16 is a circuit diagram showing a third embodiment of the stereo demodulation circuit according to the present invention. 37, 62...D-A converter, 38...Pilot signal extraction circuit, 39...PLL circuit, 4
0,55...Faze detector, 41,50
...VCO, 42, 53...Binary counter,
43,54...1/2 divider, 44,56...Low pass filter, 45,63...ROM, 48,
66... Adder, 49, 67... Adder.

Claims (1)

[Scope of Claims] 1. An FM stereo demodulation circuit comprising a multiplication means for multiplying a composite signal including at least a stereo main channel signal and a sub-channel signal by a switching signal having a subcarrier frequency, comprising: The multiplication means includes a D-type signal having a reference input terminal and a sign input terminal.
A digital code corresponding to the instantaneous value of each step of a pseudo sine wave consisting of a staircase wave of three or more values, with the frequency of the subcarrier as the fundamental wave, is input to the code input terminal of the A converter and the D-A converter.
a code generation circuit that outputs the signal in synchronization with the sub-channel signal, and the D-A converter outputs the composite signal supplied as a reference input voltage to a reference input terminal and the composite signal supplied as a digital code to a code input terminal. An FM stereo demodulation circuit characterized in that it is configured to multiply a positive phase component and a negative phase component of a pseudo sine wave to obtain left and right channel signals.