JPH027720A - Digital signal receiver - Google Patents

Abstract

PURPOSE:To prevent noise from being caused in a reproduced audio signal even in the transient state by providing a means muting a corrected digital audio signal for a prescribed period if missing of a preamble signal is consecutive. CONSTITUTION:The device is provided with a preamble signal detection circuit 1, a clock recovery circuit 2, a timing generating circuit 3, a preamble missing detection circuit 5, a counter 6 counting number of missing of preamble, a biphase demodulation circuit 8 and an audio signal correction circuit 9 and also a mute means 20 comprising a mute signal generating circuit 7 and an AND gate 10 for muting. If a preamble signal is missing, it is detected to apply the correction and if the missing is consecutive twice or over, the audio signal output is muted for a prescribed time. Thus, no noise is caused in the reproduced audio signal even in the transient state such as a change in the sampling frequency of a received signal or connection/disconnection of a reception signal input connector.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal receiving device that receives a digital signal provided by a digital interface or the like and demodulates a digital audio signal.

[Conventional technology]

Electronics Industries Association of Japan (EIAJ) CP-34Or as a transmission standard for interconnecting digital audio equipment
There is a digital audio interface. An overview of this standard will be explained below. FIG. 6 is a diagram showing the structure of a data unit called a subframe according to this standard. Each subframe consists of 32 bits, and its contents include the first 4-bit preamble PA which is a synchronization signal, the 4-bit AUX code AX for transmitting and receiving audio sub-information data, the 20-bit audio sample information DA, and the audio A 1-bit validity flag VF indicating whether the sample is correct, a 1-bit user data channel UD for transmitting and receiving additional information, a 1-bit channel status C8 for transmitting and receiving information regarding the content of audio data, and a It consists of a 1-bit parity pit PB for detecting data errors.

One sample of audio data on CD or DAT is 16
Since it is a bit, it is transmitted and received with the most significant bit (MSB) located at the right end in the latter 16 bits of the 20-bit DA area. Further, as channel status, information closely related to audio information, such as the number of channels of transmission data, sampling frequency, and dubbing prohibition code, are stored.

The 32-bit data shown in the figure is subjected to bi-phase mark modulation on the transmission path, making it easy to extract the self-clock.

By the way, based on these standards (DAT, digital amplifier, etc. can be considered as a device for receiving signals,
The following explanation will be given by taking as an example a so-called DA converter unit having a demodulation section and a DA conversion section, which has a simple configuration.

FIG. 7 shows an outline of the circuit configuration of the DA converter unit. In the figure, a signal supplied from a digital signal input terminal 31 is clock-extracted in a demodulating circuit 32, subjected to bi-phase demodulation, and audio data is separated and supplied to a DA converter 33 together with the reproduced clock signal. The signal is then converted into an analog audio signal by a DA converter 33, and outputted from an audio output terminal 35 through an amplifier 34 such as a low-pass filter or a line amplifier. In other configurations, for example, an oversampling digital filter is inserted between the demodulation circuit 32 and the DA converter 33 to reduce the order of the low-pass filter at the subsequent stage.

Although this figure only shows one channel of audio signal, since two channels of audio data are time-divisionally transmitted and received in each subframe in a digital interface for boat fishing, two channels of audio data are transmitted and received from the demodulation circuit 32. Channel digital audio signals are output alternately every 16 bits (or more), are separated into channels before or after the DA converter 33, and are output as L/H two-channel audio signals.

Incidentally, signals from various devices such as CDs, DATs, and BS tuners are supplied as input signals to the digital interface, and the sampling frequency Fs of the digital audio signals is at least 32 KHz.
There are three types: 44.1KHz and 48KHz.

In the digital interface format, the transmission rate changes according to F, and 1 bit in Fig. 6 is 64 times the frequency of F8, that is, 1 bit.
The subframe is F.

The frequency is twice that of .

[Problem to be solved by the invention]

Therefore, if the input signal F changes while a certain F signal is received and an audio signal is being reproduced, the clock extraction in the demodulation circuit 32 cannot immediately follow the change in F3 of the received signal. However, if the frequency or phase is unstable, the lock will be regenerated. Therefore, not only the digital audio signal is not separated correctly, but also the lock signal sent to the DA converter 33 is naturally disturbed. As a result, there is a problem in that noise occurs in the analog audio signal, and in extreme cases, the speaker may be damaged.

The present invention has been made in order to solve the problems of the conventional ones as described above, and it can be used when the F of the digital interface signal being received changes or when the connector supplying the received input signal is connected or disconnected. It is an object of the present invention to provide a digital signal receiving device that does not generate noise in an audio signal even in a transient state such as when the audio signal is moved.

[Means to solve the problem]

The digital signal receiving device according to the present invention includes: - means for detecting a dropout of a preamble signal that should be detected at regular intervals; and means for performing correction processing on a digital audio signal when the preamble signal is dropped. , and a means for detecting that the preamble signal is missing for a plurality of times, and generates a mute signal for a predetermined period when the preamble signal is missing for a plurality of times, and generates a corrected digital audio signal or a mute signal for a predetermined period. The system is configured to mute the output of the converted analog audio signal.

The present invention also includes means for detecting missing preamble signals that should be detected at regular intervals, means for detecting errors in the received signal using a parity check code generated and added to each subframe of the received signal, and The preamplifier includes means for performing correction processing on the received digital audio signal when an error is detected due to a loss or parity of the preamplifier signal, and a means for detecting that the loss or error state of the preamplifier signal continues for a plurality of subframes. When either a missing signal or an error condition occurs continuously over multiple subframes, a mute signal is generated for a predetermined period of time to mute the corrected digital audio signal or the analog audio signal converted from the corrected digital audio signal. It is composed of

[Effect]

Therefore, when continuous preamble signal loss occurs, such as when F of the received signal changes, or when preamble loss or an error state of the digital audio signal is detected, the present invention detects the preamble loss or preamplifier signal. In the initial state where a signal is missing or an error condition occurs in the digital audio signal, the audio signal is output as a corrected signal, then muted and becomes silent, and after the correct audio signal can be played, the mute is released. be done.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a block configuration of a digital signal receiving apparatus according to an embodiment of the present invention. In the figure, 1 is a preamble signal supply circuit, 2 is a clock regeneration circuit using a PLL or the like, 3 is a timing generation circuit, 4 is an AND gate, 5 is a preamble loss detection circuit, and 6 is a counter that counts the number of preamble loss times. , 7 is a mute signal generation circuit, 8 is a bi-phase demodulation circuit, 9 is an audio signal correction circuit, 10 is an AND gate for muting, and 20 is muting means, which is composed of the mute signal generation circuit 7 and the AND gate 10 for muting. 11 is an audio signal output terminal.

FIG. 2 is a diagram showing the operation timing of the apparatus of FIG. 1. The operation of this embodiment will be described below with reference to FIGS. 1 and 2. Digital interface signal reception input terminal 3
The signal RX supplied to the circuit 1 is input to the preamble detection circuit 1 and the biphase demodulation circuit 8. In the preamble detection circuit 1, a preamble signal shown as PA in FIG. 6 is detected and output as a PASG signal.

A preamble pattern that does not appear in the original biphase modulation is selected, and by finding this pattern, it is possible to perform preamble detection. P
The ASG signal is outputted as shown in FIG. 2(b) and applied to one input terminal of the clock regeneration circuit 2, the timing generation circuit 3, and the AND gate 4.

The configuration of the clock recovery circuit 2 is shown in FIG. In FIG. 3, the PASG multiplied signal is applied to an input terminal 201 and is applied as one input to a phase comparator circuit 202. The voltage-controlled keepsake VCO 204 oscillates at a preset free-run frequency, and the clock vcoo is divided by the counter 205 to output a REFK signal, which is applied to the other input of the phase comparator. In the phase comparator 202, PAS
G! : Compares the phase with REFK, generates a voltage according to the phase difference, and outputs V via the low-pass filter LPF203.
It feeds back to the CO 204 and changes the oscillation frequency so that the phase difference becomes smaller.

For example, set the free run frequency of VCO 204 to F.

The frequency division of the counter 205 is set to around 512 times
/256, and REF with a frequency close to twice that of F3.
Generates K signal and F in steady state.

The frequency and phase are synchronized with the PASG signal generated at twice the frequency. As the master clock PLCK, the counter 205 to VCoo (7
) A clock with a frequency of 1/4 F3X128 is taken out and output from the output terminal 206.

The timing generation circuit 3 receives the above-mentioned master crofter PLCK from the clock regeneration circuit 2, and also receives PASG as information indicating the start position of a subframe, thereby generating various timing signals required in other circuit blocks. It is for supplying.

The timing generation circuit 3 is composed of a counter that uses the PASG signal as a reset signal, a master clock PLCK signal as a clock, and a decoder that decodes the counter output and generates each timing signal.
Even if a signal is missing, a predetermined timing signal can be generated by counting the master clock from the previous subframe to which the PASG signal is applied and by allowing the counter to run freely. In addition, in reality, if the PASG signal is used as it is as a counter reset signal, if PASG occurs due to false detection in a place other than the preamble, the counter will be reset and an incorrect timing signal will be generated. PASG is always inputted as a reset signal until it is detected, and after a preamble is correctly detected, PASG gated by a protection window as described later is used as a reset signal to prevent malfunction. I can do it. The illustrated PAW signal is this protection window, and is a signal with a predetermined time width that is set near the point where the next preamble signal is to be detected by counting the master clock from the point where the correct preamble signal is detected. This is shown in FIG. 2(C). AND
Gate 4 gates PASG and PAW and outputs a highly reliable preamble detection signal GPA (see Figure 2).
d)) is generated and supplied to the preamble omission detection circuit 5 and the omission count counter 6.

The preamble missing detection circuit 5 detects that the GPA that should have been input has not been input, and generates a pulse for each subframe in which the preamble is missing. An example of its configuration is shown in FIG. Moreover, the detailed timing is shown in FIG. In FIG. 4, flip-flop 5
The GPA signal is input to the set input terminal 501 of 04, and the PAW signal is input to the clock input terminal 502, and data “0” is read at the falling point of the signal, so the Q output becomes “O” and the signal is within the protection window PAW. The preamble detection signal PA
When SG is present, it immediately becomes "1" as shown in FIG. 5 (+11). However, when the preamble is lost, the Q output becomes 0'' during that subframe, so the O
R3 from timing generation circuit 3 by R gate 505
By performing an OR with the T signal, a pulse PANG for the subframe in which the preamble is missing is obtained.

Output PANG (second
(e)) is supplied to the counter 6 and the correction circuit 9.

The counter 6 is for counting the number of consecutive subframes in which a preamble is missing, and uses the preamble detection signal GPA as a reset signal, and uses the preamble missing signal PA as a reset signal.
NG is used as a clock signal, and if, for example, the preamble is missing in two consecutive subframes, <5 PNG pulses are output as shown in FIG.

The mute signal generating circuit 7 receives the pulse from the counter 6 and generates a mute signal MUTE having a predetermined period Tm width shown in FIG. 2(h). The means for generating the mute signal here may be, for example, a one-shot multi-by-break that determines the mute time width using the time constant of a resistor and a capacitor, or a counter that digitally counts a reference clock. I don't mind.

On the other hand, the digital reception signal RX is sent to the biphase demodulation circuit 8.
and is demodulated using the clock supplied from the timing generation circuit 3. And 16 of the demodulated data
bit or more audio data bit DMD
T is extracted and input to the correction circuit 9. Correction circuit 9
Now, when there is a missing signal PANG which is the output of the preamble missing detection circuit 5, correction processing such as holding the previous value is performed on the audio data corresponding to the missing subframe of the preamble. FIG. 2(f) is a signal COMP indicating the period to be corrected upon receiving PANG. Second
In Figure TI), the data portion indicated as CPDT is the portion that has undergone correction processing by holding the previous value, and as shown in the figure, correction is performed independently for Lch and Rch. The corrected data DADT is input to one input terminal of the AND gate 10, and the mute signal MUTE from the mute signal generation circuit 7 is supplied to the other input terminal of the AND gate 10. In other words, the output of the digital audio signal output terminal 11 is as follows.
As shown in the figure, at the point where the received signal F3 is switched, correction processing is first performed, and then the data becomes muted. The period for generating the above-mentioned mute signal is set so that the clock regeneration circuit 2 follows the switched F, and is set longer than the time required for the clock phase and frequency to be synchronized, thereby outputting a stable digital audio signal. After that, muting is canceled and the audio signal corresponding to the switched F can be played back.

In this way, according to the present embodiment, when a preamble signal is missing, it is detected and correction processing such as holding the previous value is performed, and when the missing signal occurs two or more times in a row, muting is applied for a predetermined period of time. F of digital audio signal,
It is possible to obtain a speaker that does not generate noise and does not damage the speaker even in a transient state such as when the input signal changes or when a connector supplying a received input signal is connected or disconnected.

Note that in the above embodiment, audio muting is performed at the digital data stage, but as shown in FIG. Since a relay etc. for performing this is inserted, it is also possible to perform muting using this. Also, noise can be prevented by outputting the same value using pre-hold.

Further, in the description of the above embodiment, the number of preamble dropout detections is set to 2, but it is clear that this may be any other value.

Furthermore, the correction process is not limited to holding the previous value, and is not only performed when the preamble is missing, but also under other conditions, such as when an error is detected in the parity check result of the received signal. You can do it like this.

FIG. 8 is a block diagram of a digital signal receiving apparatus according to another embodiment of the present invention, which performs correction not only when a preamble is missing but also when an error is detected in the parity check result of the received signal. It is. In the figure, the same reference numerals as in FIG. 1 indicate the same parts. 201,20
2, 203° and 204 are a phase comparator, a low pass filter (LPF), a voltage controlled oscillator (VCO), and a frequency divider, which constitute the PLLUgJ path 2, respectively. Further, 12 is an error detection circuit, 13 is a second counter, and 14 is a correction control circuit.

Next, the operation of this embodiment will be explained using the operation timing diagrams of FIGS. 9 and 10. First, the signal RX supplied to the digital interface signal reception input terminal 31 is input to the preamble detection circuit 1 and the biphase demodulation circuit 8. In the preamble detection circuit 1, P in FIG.
A preamble signal added at regular intervals indicated as A is detected and output as a PASG signal. As the pattern of the preamble signal, a pattern that does not appear in the original pi-phase modulation is selected, and by finding this pattern, it is possible to perform preamble detection. P
The ASG signal is outputted as shown in FIG. 9(b) and applied to one input of the PLL circuit 2, the timing generation circuit 3, and the AND gate 4. In PLL circuit 2, V
The CO 203 oscillates at a preset free-run frequency, and its clock output is divided by a frequency divider 204 and input to one side of the phase comparator 201 . The PASG signal is input to the other input of the phase comparator 201, and the phases of the two are compared, a voltage corresponding to the phase difference is generated and fed back to the VCO 203 via the LPF 202, and the phase difference is small (
change the oscillation frequency in the direction of

For example, set the free run frequency of CO to around 512 times Fs, set the frequency divider's division ratio to 1/256,
A clock whose frequency is approximately twice Fs is generated, and the phase is compared with a PASG signal having a frequency twice Fs in a steady state, thereby extracting a clock whose frequency and phase are synchronized. At this time, the master clock PLCK is set to VC from the middle of the frequency division of the frequency divider 205.
The frequency of L28XFs with a frequency division ratio of 1/4 of the O output is extracted.

The timing generation circuit 3 receives the above-mentioned master crofter PLCK from the PLL circuit 2, and also receives the PASG signal as information indicating the start position of a subframe, thereby generating various timing signals necessary for other circuit blocks. It is for producing and supplying. The timing generation circuit 3 mainly includes a counter that uses the PASG signal as a reset signal and uses the master clock PLCK signal as a clock,
It consists of a decoder that decodes the counter output and generates each timing signal. Even if the PASG signal is missing, the master clock is counted from the previous subframe to which the PASG signal was applied and the counter is free-running to provide a predetermined timing signal. generates a timing signal. Also, actually P
If the ASG signal is used as a counter reset signal as it is, the PASG signal will be detected incorrectly in a place other than the preamplifier.
If a signal is generated, the counter will be reset and an incorrect timing signal will be generated. Therefore, until the preamble signal is detected, for example, always input the PASG signal as a reset signal as it is to ensure that the preamble is detected correctly. After that, the PASG signal gated by a protection window as described later is used as a reset signal to prevent malfunction. The PAW signal shown in FIG. 9(C) is this protection window, and the clocks are counted from the point where the correct preamble signal is detected, and then set near the point where the preamble signal is to be detected. It is a signal with a predetermined time width.

AND gate 4 gates the PASG signal and PAW signal and outputs a highly reliable preamble detection signal GP.
A (FIG. 9(d)) is generated and supplied to the preamble omission detection circuit 5 and the omission count counter 6.

The preamble missing detection circuit 5 detects that the GPA& symbol inputted at almost constant intervals is not inputted.
．． - One pulse PANG as shown in FIG. 10(C) is generated for each subframe in which the preamble is missing. 1st
The counter 6 is for counting the number of consecutive subframes in which a brilliance drop has occurred, and uses the preamble detection signal GPA as a reset signal and the preamble missing signal PANG as a clock signal. Figure 10 (
It outputs a pulse SPA like el and gives it to the mute signal generation circuit 7.

On the other hand, the digital input signal RX is input to the biphase demodulation circuit 8 and demodulated using the reference clock supplied from the timing generation circuit 3.

The demodulated data is given to the error detection circuit 12 and the correction circuit 9, and the error detection circuit 12 uses the parity check as shown in FIG. It is detected whether or not there is an error, and if an error is detected, a pulse PTNG is outputted as shown in FIG. 10(d) and supplied to the second counter 13 and the correction control circuit 14. The second counter 13 operates similarly to the first counter 6 and is for counting the number of consecutive subframes in an error state. For example, when two subframes are in an error state in a row, Figure 9 ('b)
The mute signal generation circuit 7 outputs a pulse as shown in
supply to.

In the correction circuit 9, 16 or more audio data bits are extracted from the demodulated data, and in response to a command from the correction control 11 circuit 10, the corresponding audio data is corrected by holding the previous value, etc. Process. The previous value hold is a process of holding the previous value as it is, and correction is performed independently for I, ch, and Rch.

The correction control circuit 14 receives the error detection pulse PTNG and the preamble loss detection pulse PANG, and sends a control signal CPCM (see FIG. 10 (1) ) and feed it to the correction circuit.

The mute signal generation circuit 7 includes a counter 6 and a counter 13.
mute signal MUT with a predetermined period width Tm.
E is generated, and muting is performed when either a preamble missing state or an error detection state occurs continuously over a plurality of subframes. For example, FIGS. 9(c) and 9(d) show a state in which PANG occurs continuously at the Fs switching point CHG, but it does not necessarily result in a continuous error, and there are some subframes in which PTNG is not output. There is. In the case of the data structure shown in Figure 4, error detection is performed using a 1-bit parity bit, so it is easy for errors to be overlooked (
, such a situation can easily occur. In such a case, the mute signal MUTE is generated by the pulse SPA (FIG. 10(e)) which is output upon detection of two consecutive PANGs, and is output as shown in FIG. 10(J). Also, FIG. 10(g).

In contrast, (h) shows a state in which PTNG occurs continuously, but there are some subframes in which it is not determined that the preamble signal is missing. In such a case, PTNG is 2
A MUTE signal is generated by a pulse (not shown) that is output upon detecting that the times are consecutive.
It is output as follows.

Here, specific means for generating a mute signal include, for example, a one-shot multivibrator that determines the mute time width using a time constant of a resistor and a capacitor, or a counter that digitally counts a reference clock. It doesn't matter which one.

The output MUTE signal of the mute signal generation circuit 14 is AND
is supplied to one input of gate 10, and to the other input:
Since the corrected audio data is supplied from the correction circuit 12, the output of the AND gate 10, that is, the signal DAOT of the digital audio signal output terminal 11 is as shown in FIG.
), after the Fs of the received signal is switched, the first Tc period becomes corrected data, and then muted "O" level data.

The period Tm for generating the above-mentioned mute signal is switched F.
Muting is canceled after the clock regeneration circuit 2 follows s, the clock phase and frequency are set longer than the time required to synchronize, and a stable digital audio signal can be output. is,
The audio signal corresponding to the switched Fs is reproduced.

In the above description, the counter 6 as a means for detecting the continuity of preamble omissions and the counter 13 as a means for detecting the continuity of error states are provided separately, However, by using a counter to count the number of subframes in which either a preamble dropout or an error state occurs, the above-mentioned small (
A configuration may also be adopted in which muting is performed when either one of the conditions continues.

In addition, in the other embodiments, audio muting is applied at the digital data stage, but
As shown in Fig. 4, in the A converter unit, digital input amplifier, etc., a relay for analog muting is inserted in the output of the DAC 33 or the output of the amplifier 34, so this can be used to mute the output. It is also possible to carry out

Furthermore, in the description of the other embodiments, the number of missing preambles and the number of consecutive error states are each set to 2 as conditions for generating a mute signal, but it is clear that these may be other values.

Furthermore, in the other embodiments described above, the digital data is
'' or by turning off the analog output using a relay, muting is applied, but previous value holding may be performed continuously, and the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the digital signal receiving device according to the present invention, when receiving a digital signal, it is possible to deal with the case where a preamble signal is missing, or when an error occurs in a missing preamble signal or a digital audio signal. In addition to correcting the audio signal, the system is configured to mute the audio signal output for a predetermined period of time when a preamble signal is missing, a preamble signal is missing, or an error occurs in the digital audio signal continuously, so that the received signal cannot be sampled. This has the effect of providing a device that does not generate noise in the reproduced audio signal even under transient conditions such as changes in frequency or disconnection of the received signal input connector.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a digital signal receiving device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the device shown in FIG. 1, and FIG. 3 is a block diagram showing the operation of the device shown in FIG. FIG. 4 is a block diagram showing the detailed configuration of the circuit; FIG. FIG. 6 is a data configuration diagram showing an example of the data configuration of a digital interface format to which the present invention is applied, FIG. 7 is a block configuration diagram of a DA converter unit that is an example of a device to which the present invention can be applied, and FIG. A block diagram showing another embodiment of the invention, and FIGS. 9 and 10 are timing diagrams showing the operation of the apparatus shown in FIG. 8. In the figure, 31 is a digital reception signal input terminal, 1 is a preamble detection circuit, 5 is a preamble missing detection circuit, 6 is a counter, 7 is a mute signal generation circuit, 9 is a correction circuit, 10 is a mute gate, and 12 is a error detection circuit,
13 is a counter, 14 is a correction control circuit, and 20 is a mute means. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A device for receiving a digital signal in a predetermined format, one unit of which is composed of at least a digital audio signal and a preamble signal as a synchronization signal, and means for detecting that the preamble signal is missing; means for correcting a unit of digital audio signal with a missing preamble; means for detecting a plurality of consecutive units of missing preambles; 1. A digital signal receiving device comprising: means for muting a converted analog audio signal for a predetermined period of time. (2) one unit is at least a digital audio signal;
A device for receiving a digital signal in a predetermined format consisting of an error detection code capable of detecting errors in the digital audio signal and a preamble signal as a synchronization signal, the device detecting that the preamble signal is missing. means for detecting an error in the digital audio signal using the error detection code; means for correcting the digital audio signal in a unit in which a missing preamble or error is detected; and means for muting the corrected digital audio signal or the analog audio signal obtained by converting the corrected digital audio signal for a predetermined period when a preamble dropout or an error state occurs continuously. A digital signal receiving device comprising: