JPS61198469A - Muting control system for acoustic signal - Google Patents

Abstract

PURPOSE:To prevent generation of a drift and to reduce the cost by outputting a mute signal when the count of an up-down counter reaches the predetermined 1st value and interrupting the mute signal when the count reaches the predetermined 2nd value corresponding to the synchronous period. CONSTITUTION:When the count of an up-down counter at an asynchronous period reaches N, a signal starting the muting is outputted from a flip-flop circuit 15. Then after the mute signal is outputted, the mute signal is outputted until the count content of the up-down counter 14 subjected to down-count at the synchronous period agrees with 0, and the mute signal is interrupted when the content is coincident with 0. Even when the synchronous/asynchronous state takes place respectively in a short time, the muting is not applied excessive ly, noises on the acoustic feeling are reduced, and when the circuit is integrated, for example, generation of drift is prevented and the cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an audio signal muting control system used for receiving and processing audio signals.

BACKGROUND ART For example, in a compact disc playback device, if there is a scratch on the surface of the compact disc, which is a recording medium, the synchronization signal recorded on the compact disc cannot be reliably read. A state in which synchronization cannot be achieved may occur due to the difference between a signal and a device that receives the signal and performs signal processing in synchronization. At this time, fi! of the signal read from the compact disc etc. Since iL is generated as noise when reproduced as an acoustic signal, it is necessary to apply so-called muting.

When such muting is applied, a circuit is used that detects the synchronous/asynchronous state as described above and outputs a signal indicating synchronous or asynchronous corresponding to each state. When muting is performed using a signal generated from such a circuit, the following method has been used.

■Use the signal indicating synchronous/asynchronous as described above and mute the asynchronous period.

(2) For example, using an analog integrator and a comparator, muting is applied when the integrated value of the signal representing synchronization/asynchronousness exceeds a reference value.

Here, the muting signal generation circuit 1, which was used in the miniting control method shown in (2) above, is replaced with a third one.
As shown in the figure.

The miniting signal generating circuit 1 basically includes an integrating circuit 2 and an upstream comparing circuit 3. In the integrating circuit 2, the output from the synchronous/asynchronous detection circuit 5 is applied to the inverting input terminal of the operational amplifier API via a resistor R1. Further, the non-inverting input terminal of the operational amplifier API is grounded. Further, the operational amplifier API is provided with a feedback circuit via a capacitor C1.

Further, the comparator circuit 3 is provided with an operational amplifier AP2, and the output from the integrating circuit 2 is applied to the inverting input terminal of the comparator circuit 3 via a resistor R2. Its non-inverting input terminal has a resistor R3
A reference voltage is applied via the . *Operational amplifier AP2
A return circuit is provided through a resistor R4.

The operating state of the mute signal generation circuit 1 shown in FIG. 3 will be explained using FIG. 3 and #S4. The synchronous/asynchronous detection circuit 5 outputs a signal as shown in FIG. 4(1) corresponding to the synchronous/asynchronous state as described above. In this signal, high level portions Wl, W2 . W3 corresponds to an asynchronous state, and the remaining low level portion corresponds to a synchronous state. Therefore, when such a signal is input to the integrating circuit 2, the output from the integrating circuit 2 has a waveform shown in #4 diagram (2). When this output is input to the comparator circuit 3, it is compared with the reference voltage indicated by line No. 1 in FIG. 4(2), and the comparator circuit 3 outputs a high-level signal in the section where the reference voltage is exceeded. This signal becomes a muting signal and starts muting.

Problems to be Solved by the Invention In the muting method shown in item (2) above, muting is applied in all non-same cycle periods, resulting in excessive minting and an increase in noise in the pitch sense. . In addition, in the miniting control method (2) explained with reference to Figures 3 and 4 above, since the circuit is configured with analog elements, so-called drift may occur and the circuit/circuit configuration may become complicated. There was a problem in that the cost would increase.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and provide a method for controlling an audio signal miniting 11i17 which can be realized by a circuit with a simplified configuration.

- Means for Solving the Problems The present invention generates a signal representing synchronization and asynchronousness with respect to an acoustic signal from a signal generation circuit, generates a constant periodic signal from a clock signal generation circuit, and combines the signal with the clock signal. is input to the 7-bit down counter, and either up-counting or down-counting is performed, and during the asynchronous period, either up-counting or down-counting is performed, and the count value of the up-down counter is A mute signal is output when a predetermined first value corresponding to the asynchronous period is reached, and the mute signal is cut off when a predetermined second value corresponding to the synchronous period is reached. This is an audio signal muting control method characterized by the following.

A signal from a circuit that generates signals representing synchronous and asynchronous operation and a clock signal from a clock signal generation circuit that generates a clock signal with a constant period are applied to a seven-way down counter. The up-down counter performs either up-counting or down-counting during the synchronous period, and performs either up-counting or down-counting during the asynchronous period. Corresponding to the output from this up/down counter, when the count value of the 7-bit down counter reaches a predetermined first value corresponding to the asynchronous period, a mute signal is output from this circuit. In addition, a predetermined second
When the value is reached, this circuit cuts off the mute signal. Therefore, the mute signal generated/blocked in this way allows for a good muting control in terms of pitch.

Embodiment FIG. 1 is a block diagram showing the electrical configuration of a mute signal generating circuit 10 that implements minting control according to an embodiment of the present invention. The mute signal generation circuit 10 is equipped with a synchronous/asynchronous detection circuit 11 that detects synchronous/asynchronous states as described in the description of the prior art and outputs signals corresponding to each state. The output from the synchronous/asynchronous detection circuit 11 is taken out on line 12. Line 12 is connected to the inverter INV, whose output is AND data) Gl
is given to one input side. On the other hand, a signal from line 12 via branch line 13 is applied to the other input side of AND gate G2.

The mute signal generation circuit 10 is equipped with an up/down counter 14, and a reference clock signal φ as shown in FIG. 2(1) is input thereto. up/down counter 14
The maximum count value is determined to be N, and the minimum count value is determined to be O. This up/down counter 14 is supplied with a signal from the synchronous/asynchronous detection circuit 11 via the line 12 and the branch line 13. The open counter 4 to which this signal is applied counts up every cycle with respect to the reference clock. The up/down counter 14 also includes an inverter rNV.
The open, up-down counter 14, which is given the output from the inverter INV, is given the output from the inverter INV. - count down the contents.

The outputs of such up/down counters 14 are given to comparators CPI and CP2, and their outputs are
D-day) G2. Gl is applied to each other input side. AN
D date G2. The output of Gl is R-87')-, respectively.
70 is applied to the set side and reset side of the tube circuit 15, respectively.

The high level output from this 7-rip 7a tube circuit 615 becomes a mute signal.

FIG. 2 is a timing chart illustrating the operating state of the mute signal generation circuit 10. The operating state of the mute signal generation circuit 1o shown in mi will be explained with reference to FIGS. 1 and 2. As mentioned above, the 7-step counter 14 receives the reference clock signal φ shown in FIG. 2 (1).
is given.

A state in which a signal having a waveform as shown in FIG. 2 (2) is output from the synchronous/asynchronous detection circuit 11 will be explained. In the synchronous/asynchronous state shown in FIG. 2(2), the high level portion corresponds to the asynchronous state, and the low level portion corresponds to the synchronous state. The synchronous/asynchronous signal shown in FIG. 2(2) is input to the mute signal generation circuit 1o from time tO, but at this time the contents of the 7-bit down counter 14 are cleared and set to 0. Therefore, during this time,
The content stored in the up/down counter 14 is 0. Therefore, the contents of this store are comparators CPI, CP
Output Z to 2, jk, #14 CP 21. j k
It is determined that the date and date match O, and therefore the comparator 5cP2 outputs, for example, a high level signal to the AND date G1. On the other hand, a signal from the synchronous/asynchronous detection circuit 11 is input to the AND data) Gl via the inverter TNV, and at this time, the signal inverted and output by the inverter INV is at a high level. Therefore, the AND date G1 outputs a signal to the reset side input terminal of the 7-lip 70-tub circuit 15, and therefore the 7-lip 70-tub circuit 15 outputs a signal to the reset side input terminal of the
The 0-tub circuit 15 does not output a mute signal.

Next, as shown in Fig. 2, when the synchronous/asynchronous signal at alarm 1 becomes the /
This high level signal is input to the up/down counter 14 via the reference clock signal φ, and the up/down counter 14 performs an up-counting operation corresponding to the reference clock signal φ.

At time t3, when the count content of the up/down counter 14 reaches N, the comparator CPI determines that the output matches the predetermined N, and the AN
D day) A high level signal is derived to G2. At this time, AND day) G2 has line 12 and branch line 1.
A high level signal is given through 3. Therefore, AND date G2 is 7 rip 7 of the high level signal.
It is led out to the set side input terminal of the 0 tube circuit 15.

Therefore, the 7-rip, 70-tub circuit 15 outputs a mute signal, which is a high-level signal, to perform muting. Here, the synchronous/asynchronous signal is at a high level from time t3 to t2, but as mentioned above, the upper limit value of the up/down counter 14 is set to N, so the up/down counter 14 cannot count any more. It never gets hot.

Next, when the synchronous/asynchronous signal becomes low level during the period from time 12 to t4, the signal that is inverted by the inverter INV and becomes high level is input to the up/down counter 14. Therefore, during this period, the up/down counter 14 counts down as shown in FIG. 2(3).

Next, at times t4 to t5 in FIG. 2, the synchronous/asynchronous signal becomes high level, and the 7-down counter 14 counts up as described above. Next, during the period from time L5 to time L6, when the synchronous/asynchronous signal is at a low level, the signal that is inverted by the inverter INV and becomes a high level is input to the up/down counter 14, and the up/down counter 14 counts down during this period. Do the following. At time t7, the count value of the 7-up down counter is O.
become.

At this time, the comparator CP2 determines that the count content of the up/down counter 14 is 0, and inputs a high level output to the AND data) Gl.

Furthermore, since the signal from the synchronous/asynchronous detection circuit 11 is inverted by the inverter INV and applied to this AND data) Gl, a high level signal is input. Therefore, the output of AND day) Gl becomes high level as shown in FIG. 2 (5). This signal is 7 lip 70 tube circuit 1
Therefore, the output of the 7-rip 70-tub circuit 15 becomes low level as shown in FIG. 2 (6), and the mute signal is cut off.

Next, between time 7 and t6, the synchronous/asynchronous signal is at a low level as shown in FIG.
The stored content of the FPG counter 14 is O. Therefore, during this period, the output of AND5'-)G1 maintains a high level as shown in Figure 2 (5), and at time 6, the synchronous/asynchronous signal goes to a high level as shown in Figure 2 (2). When this happens, the up/down counter 14 counts up in response to this rise. Also, at this time, a signal inverted by the inverter INV and set to a low level is applied to the AND date G1.

Therefore, the output of AND day) Gl reaches a low level at time t6, as shown in FIG. 2(3). As described above, according to the present invention, when the count value of the 77 pg down counter 14 during the asynchronous period reaches N, a signal for starting the minting operation is outputted from the 7 riff 1 fp 0 fp circuit 15. Therefore, after outputting the mute signal,
A mute signal is output until the count content of the up/down counter 14, which is counted down during the synchronization period, matches 0. Further, when the value matches 0, the mute signal is disconnected.

By doing so, even if the synchronous/asynchronous state repeatedly occurs in a short period of time, muting is not performed excessively, and it is possible to reduce the noise on the pitch. In addition, since the circuit shown in Figure 1, which implements such a mining control method, can be realized as a digital circuit, for example, by integrating it into an integrated circuit, it is possible to prevent the occurrence of so-called drift, and to reduce costs. You can try to bring it down.

Effects As described above, according to the present invention, a signal from a circuit that generates signals representing synchronous and asynchronous signals and a constant period clock signal from a clock signal generating circuit are applied to an up/down counter. The up/down counter performs either up-counting or down-counting during the synchronous period, and performs the other of up-counting or down-counting during the asynchronous period, in response to the signal. Also, a mute signal is output or cut off in accordance with the output from this up/down counter.

That is, when the count value of the up/down counter reaches a predetermined value of ml corresponding to the asynchronous period, a mute signal is generated, and when the count value reaches a predetermined second value corresponding to the synchronization period, the mute signal is muted. I tried to block the signal. Therefore, even if the same/non-synchronization occurs repeatedly in a short period of time, excessive muting operation/non-operation can be prevented, and it is possible to reduce the noise in the pitch sense. We were able to realize a circuit that achieves this effect using a simplified circuit configuration as a denotal circuit.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram explaining the electrical configuration of an embodiment of the present invention, FIG. tItJ2 is a timing chart explaining the operating state of the mute signal generation circuit 10, and FIG. 3 is a diagram explaining a typical prior art. FIG. 4 is an electric circuit diagram and a timing chart illustrating the operating state of the mute signal generating circuit 1 of the prior art. DESCRIPTION OF SYMBOLS 10... Mute signal generation circuit, 11... Synchronous/asynchronous detection circuit, 14... 77 program down counter, 15
...R-S 7 U tube float circuit, 16... Reference clock signal generation circuit, CPI, CF2... Comparison circuit, G 1, G 2... AND Date agent Patent attorney Number of strokes Keiichi (1) 2, Figure 2, Procedural amendment August 27, 1985 Patent application 1986-37822 2. Name of the invention Muting control method for acoustic signals 3. Relationship with the person making the amendment Applicant address Abeno, Osaka City Ward Nagaike-cho 22-22 Name (50
4) Sharp Corporation Representative: Saeki Asahi 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinko Sangyo Building Country Equipment EX 0525-5985 INTAPT
J International FAX GDI&GIl (06)538-
0247 Telephone (061538-0263 (Representative) 6, Drawing subject to amendment 7, Contents of amendment Figure 2 of the drawing will be corrected as shown in the attached sheet.

Claims (1)

[Scope of claims] An up/down counter that generates a signal representing synchronization and asynchrony with respect to an acoustic signal from a signal generation circuit, generates a clock signal of a constant period from the clock signal generation circuit, and receives the signal and the clock signal as input. Then, one of up-counting and down-counting is performed, and during the asynchronous period, the other of up-counting and down-counting is performed, and the count value of the up-down counter is determined in advance so as to correspond to the asynchronous period. muting of an acoustic signal, characterized in that a mute signal is output when a predetermined second value corresponding to a synchronization period is reached, and the mute signal is cut off when a predetermined second value corresponding to a synchronization period is reached. control method.