JPS6159668A - Muting controller - Google Patents

Abstract

PURPOSE:To improve the reliability of muting operation and to make it into an IC detecting an error part of a reproduced digital audio signal to correct it and muting the reproduced digital audio signal in accordance with the error counted output. CONSTITUTION:A data signal processing part 41 is provided with an EFM demodulating part 42, a RAM46, and an error detecting and correcting means 48. The demodulated output is applied to not only the control part 44 but also a CPU50. The means 48 detects and corrects the error part of the reproduced digital audio signal. If correction of the error is impossible, an error signal is outputted to the CPU50, and an error counter included in a RAM58 is counted up, and muting is performed by the control of a timer counter as a timing setting means included in the RAM58. Thus, the reliability of the muting operation is improved, and it is made into an IC.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a muting control device used in digital audio equipment that plays back compact discs (CDs) and the like.

BACKGROUND ART When playing a CD, it is difficult to completely eliminate the phenomenon of missing sound, that is, the skipping phenomenon, which occurs due to scratches on the CD or vibrations during playback. Therefore, a muting operation is necessary to accurately and effectively eliminate the noise caused by the skipping phenomenon.

FIG. 6 shows a conventional muting control device.

The error detection and correction means 2 receives a digital audio signal from a decoder (not shown) and detects errors such as skipping from the signal. Furthermore, the data control section 4 performs a muting operation on the digital audio signal when muting is necessary based on the error signal from the error detection and correction means 2.

The outputs C2F1 and C2F2 of the error detection and correction means 2 are N
The output of the NAND circuit 6 is applied to one input terminal of the NAND circuit 8. NAN
The other input terminal of D circuit 8 is maintained at 1A (H) level, and the output of NAND circuit 8 is applied to capacitor 12 via the anode and cathode of diode 10. A resistor 14 is connected in parallel to this capacitor 12, the resistor 14 forms a discharge circuit for the capacitor 12, and the terminal voltage of the capacitor 12 is applied to the NA via a resistor 16.
is applied to one terminal of the ND circuit 18, and the NAND circuit 1
The other terminal of 8 is maintained at H level.

The output of the NAND circuit 18 is connected to a resistor 20 and a diode 22.
The terminal voltage of the capacitor 26 is applied to one terminal of the NAND circuit 30 via the resistor 28. The other terminal of the NAND circuit 30 is maintained at H level, and the output of the NAND circuit 30 is applied to a filter consisting of a capacitor 34 and a resistor 36 via the anode and cathode of a diode 32, and is also applied to the muting control of the data controller 4. It is an input.

In such a muting control device, NAND
The error signal C2F1 of the error detection and correction means 2 is supplied to the circuit 6.
When C2F2 is input, the output of the NAND circuit 8 becomes H level. The output of the NAND circuit 18 is approximately 0.4 determined by the first time constant formed by the capacitor 12 and the resistor 14 after the output of the NAND circuit 8 shifts to low (L) level.
The output is held for a period of 5m5ec. During this time, NAND
When the output of the circuit 8 goes high, the NAND circuit 18 holds the output for the period of 0.45 m5ec from the time when the output goes to the low level.

Further, when the NAND circuit 18 holds the output for a period of about 14 m5ec determined by the second time constant of the resistor 24 and the capacitor 26, the NAND circuit 30 generates an H level output, which is used as a muting signal to the data control section. Added to 4.

Then, the state returns to normal, and the error signal C2F1,
When C2F2 is no longer generated and the NAND circuit 8 outputs an L level, the diode 22 turns on and the second time constant becomes approximately 0.7 m5ec determined by the resistor 20 and capacitor 26, which is approximately 1.2 m5ec. (
After 0.45 m5ec+0.7 m5ec), the NAND circuit 30 releases the muting signal.

7 and 8 show the operation explained above, and FIG.
In the figure, A is the output of the NAND circuit 8, and B is the output of the NAND circuit 8.
In the output of the N-D circuit 18, in FIG. 8, B is the NAND
The output of circuit 18, C, is the output of NAND circuit 30.

Here, Table 1 shows the relationship between the error signals C2F1 and C2F2 and the correction states.

In Table 1, when the C2 correction state is uncorrectable, a muting signal is generated as described above and applied to the data control section 4.

Problems to be solved by the invention According to this muting ml'+ wholesale packing device,
Although it is not necessary to use a complicated control device or control method such as a microcomputer, since the muting control device is configured individually, the decoder is externally connected to the circuit and has a time constant circuit with a capacitor. Because there are
There are drawbacks that make it unsuitable for semiconductor integrated circuits.

In addition, with such a control device, there is a risk that the muting control will operate when muting is not necessary.
Furthermore, there are drawbacks such as the inability to adjust the amount of muting attenuation.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a muting control device that improves the reliability of muting operations and that can be implemented as a semiconductor integrated circuit.

Means for Solving the Problems The present invention, as shown in FIG. 1, includes an error detection and correction means 48 that detects and corrects an error portion of a reproduced digital audio signal and generates an error signal when correction is not possible. , an error counting means 38 for counting error signals generated by the error detection and correction means; a timing setting means 39 for setting a counting time in the error counting means; The muting means 40 mutes the digital audio signal.

Effect: If the errors in Table 1 cannot be corrected within a predetermined period of time, the error counting means 38 generates an output, and muting is executed in accordance with the output.

Embodiments Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.

FIG. 2 shows an embodiment of the muting control device of the present invention.

In FIG. 2, a data signal processing unit 41 that processes data such as digital audio signals reproduced from a CD includes an E F M (Eight to Fourth
nModulation) demodulation section 42, data control section 4
4. A readable/writable memory element (RAM) 46 and an error detection/correction means 48 shown in FIG. 1 are installed, and these are interconnected by a data bus 49.

EFM data and a clock signal are applied to the EFMFM demodulator 2, and the demodulated output WFCK is applied to a data control unit 44, and the output WFCK is applied to a central processing unit (CPU) 50 as an input lNTl.

The data control section 44 outputs 16-bit acoustic data to a D/A converter or the like based on the demodulated data from the EFMFM demodulation section 2.

The RAM 46 temporarily stores the processing data of the data control unit 44 and sequentially updates the stored data at predetermined timing.

Further, the error detection and correction means 48 is a circuit that works in conjunction with the EFMFM demodulation section 2 and the RAM 46, detects data errors caused by sound skipping in the data, and corrects the errors. If this is not possible, error signals C2F1 and C2F2 are output and added to the AND circuit 52. The AND output obtained from this AND circuit 52 is CP
This is the input INT2 of U50.

The CPU 50 performs arithmetic processing according to a predetermined control program, and includes an input/output device (Ilo) 54 that inputs and outputs data, and a memory element (ROM) 56 that stores the control program and fixed data. ,
A storage element (RAM) 58 for temporarily storing read data and data undergoing arithmetic processing, a control bus 60, an address bus 62, and a data bus 64 are interconnected. The RAM 5B includes an error counter as the error counting means 38 and a timer counter as the timing setting means 39 shown in FIG. Further, the data control section 44 includes a muting means 40.

Note that the CPU 50 is linked to a control circuit such as a microcomputer (not shown) for display and manual key operation.

Muting control will be explained based on the above configuration.

In FIG. 2, when both the outputs C2F1 and C2F2 of the error detection and correction means 48 of the data signal processing section 41 become 1, that is, the H level, the interrupt program is executed, and the error counter included in the RAM 58 is incremented each time. muting is controlled according to the state of the error counter.

The system timer of the timer counter included in the RAM 58 is WFCK (Write Frame C1oc
k: Using 7.35Kt(z), approximately 1 m5e
Create the necessary timer c (8 clocks of W F CK). The error counter is then reset by a system timer of about 1 m5ec. Here, WFCK is a clock signal used to read time data 5UBQ (subcode). Note that the interrupt by WFCK is
It creates time data for display.

Error signals C2F1 and C2F2 are interrupt inputs,
When this input becomes H level, a count value of 1 is added to the error counter, and the count value of the counter is multiplied eight times.

In other words, if the error counter value is O or 1, the previous state is maintained, and if the value is 2 or 3, (a) the state before the error counter value shifts to 2 or 3 is maintained; When the playback status is normal, operate the -12 dB attenuator, or (bl) If the status before the error counter value shifts to 2 or 3 is the muting status, maintain that status. One of the states is selected.

Moreover, when the value of the error counter becomes 4 or more, muting starts.

When the error counter counts 8 clocks of WFCK, it is reset and starts counting again.

At the time of this reset, if the previous state was the muting state, the count value is checked. That is, when the count value of the counter is O or 1, it is in a normal state, and when it is 2 or 3, a -12 dB attenuator is operated, and
When it is 4 or more, muting operation is performed.

FIG. 3 shows determination of the muting state with respect to the count value of the error counter. In step (1), an error counter is incremented, and in step (2), it is determined whether the value of the error counter is 2 or more (ECUNT≧2). If it is determined in step (2) that the value of the error counter is less than 2, as in step (3), the previous muting state is shifted to the next muting state, that state is set, and an interrupt is generated. Stop program execution.

Further, if it is determined in step (2) that the value of the error counter is 2 or more, it is determined in step (4) whether the value is 4 or more.

If it is determined in step (4) that the value of the error counter is 4 or more, in step (5) a muting control start command is generated and execution of the interrupt program is stopped.

Also, if it is determined in step (4) that the value of the error counter is less than 4, the execution of the interrupt program is terminated.

Next, FIG. 4 shows counting of the timer counter and muting control. In step (1), it is determined whether or not normal playback operation is in progress. If it is determined in step (1) that normal playback operation is in progress, a timer counter is incremented in step (2).

In step (3), it is determined whether the count value of the timer counter is 8 or more. If it is determined that the count value of the timer counter is less than 8, time data is fetched in step (4) and the execution of this program is terminated.

If it is determined in step (3) that the count value of the timer counter is 8 or more, the count value of the timer counter is reset in step (5), and in step (6) the previous muting state and error counter are Using the count value as a determining factor, the next muting state is determined, and the error counter is reset in step (7).

If it is determined in step (1) that normal playback operation is not in progress, the timer counter is reset in step (8), the error counter is reset in step (9), and the process moves to step (4).

Figure 5 shows the operation timing of muting control,
A is the WFCK, B is the data control unit 4 from l1054.
4, C is the MUTG added from the l1054 to the data control unit 44, D is the count value of the error counter, and E is the muting control output, that is, the muting control state of the digital audio signal.

As described in detail, the present invention provides the following effects.

(11) Highly reliable muting control can be realized using the microcomputer installed in digital audio equipment, and can be realized using semiconductor integrated circuits without requiring any special external circuits.

(2) The amount of attenuation of the reproduced signal can be changed in accordance with the degree of error occurrence.

(3) It is possible to control fade-in and fade-out when starting and canceling muting, and smooth and natural sound reproduction can be achieved.

(4) Muting can be performed only on data for which a predetermined error signal has occurred.

[Brief explanation of drawings]

FIG. 1 is a professional diagram showing the configuration of the muting control device of the present invention, FIG. 2 is a block diagram showing an embodiment of the muting control device of the present invention, and FIGS. 3 and 4 show the control thereof. FIG. 5 is a flowchart showing the program, FIG. 5 is a timing chart showing its operation timing, FIG. 6 is a block circuit diagram showing a conventional muting control device, and FIGS. 7 and 8 are timing charts showing its operation timing. . 48... Error detection and correction means, 38... Error counting means, 39... Timing setting means, 40... Muting means. Figure 1

Claims (1)

[Claims] Error detection and correction means for detecting and correcting error portions of a reproduced digital audio signal and generating an error signal when correction is impossible; error counting means for counting error signals generated by the error detection and correction means; A muting control device comprising: timing setting means for setting a counting time in a counting means; and muting means for muting the reproduced digital audio signal in accordance with the counting output of the error counting means. .