JPH01170222A - Controller for error correction circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous erasure correction in case of the erasure correction through the use of a C1 pointer by applying error correction and erasure correction with respect to a 2nd error correction code series and inhibiting the erasure correction if discontinuous frame of an input signal. CONSTITUTION:The error correction and erasure correction is applied by using C2 decoding in a controller of an error correction circuit using the cross interleave reed Solomon code used for a reproducing circuit of a digital audio disk, and the erasure correction is inhibited for a prescribed period if the discontinuous frame of the input signal takes place. Thus, the quadruple erasure correction is applied to improve the error correction capability, and if discontinuous frame takes place and the C1 pointer becomes incredible, since the erasure correction is inhibited, the erroneous erasure correction can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control device for an error correction circuit applied to, for example, a playback circuit for digital audio discs (so-called compact discs).

[Summary of the invention]

In this invention, in a control device for an error correction circuit using a cross-interleaved Reed-Solomon code used in a writing/writing circuit of a digital audio disc, error correction and erasure correction are performed by C2 decoding, When frame discontinuity occurs,
By prohibiting erasure correction for a predetermined period, errors in erasure correction can be prevented.

[Prior art] Digital audio discs use cross-interleaved Reed-Solomon codes (
An error correction code called a CIRC code is used. This error correction code is 1 included in each of the PCM data series of multiple channels in the first arrangement state.
A first error correction code sequence (C2 code) consisting of a word and a first check word corresponding thereto is formed by interleaving the PCM data sequences of multiple channels and the first check word sequence with different time delays for each channel. a second arrangement state, and a second error correction comprising PCM data of a plurality of channels in the second arrangement state, l words included in each of the first check word series, and a second check word therefor; A code sequence (C2 code) is formed, and on the decoding side, the C1 code is decoded (C1 decoding) and the C2 code is decoded (C2 decoding), and C2 decoding is performed using the pointer information obtained by C1 decoding. .

As shown in FIG. 11, in the conventional CIRC code, C1
A code sequence (C1 sequence) is formed by 32 symbols alternately included in two adjacent frames (1 frame: 32 symbols), and a C2 code sequence (C2 sequence) is formed by a predetermined frame within 108 frames. It is formed by 28 symbols included in the .

During cue and review, track jumps occur continuously, and frame discontinuities occur in the reproduced RF signal from the digital audio disc. Since the interleave length of the C1 code is only l frames, the Cl pointer indicating the presence of an error is set only in 2 frames in ±1 frames before and after the discontinuous point. On the other hand, in the C2 series, the interleave length is 108 frames, so
The 108 frames after the discontinuity will have multiple errors.

In C2 decoding, if there are three or more errors and the number of C1 pointers is two or more, the Cl pointer is copied and used as a flag indicating whether data is valid or invalid. Therefore, in the case of multiple errors in the C2 series occurring at the discontinuous portion described above, a copy operation of the C1 pointer is performed. The reproduced data processed in this manner is output after error interpolation, but a reproduced sound (that is, noise) that is a mixture of sounds before and after the discontinuous portion is generated.

Similar noise occurs not only when the memory for cue and review but also when the memory for day interleaving overflows.

Conventionally, in order to make the above-mentioned noise less noticeable during cue and review, passive measures have been taken such as lowering the gain during playback by, for example, -12 dB or applying minting.

As a countermeasure to the above-mentioned problem, Japanese Patent Application Laid-Open No. 80672 or JAS Conference °86 Proceedings (Pages 90 to 9
3) has been proposed.

In addition, the applicant of the present application has developed a system that not only reproduces audio PCM signals but also improves the error correction ability when the disc is used as a CD-ROM (C1 decoding→C
2 decoding → C1 decoding → C2 decoding), C1 decoding and C2 decoding are performed twice, and in the first C2 decoding, the previous stage C
We have proposed an error correction method that performs quadruple erasure correction using the Cl pointer obtained in one decoding process.

[Problems to be Solved by the Invention] However, if quadruple erasure correction is performed in C2 decoding, a problem arises in that erroneous corrections and missed errors in the previous stage of C1 decoding cannot be checked during C2 decoding. That is, the quadruple erasure correction is performed with respect to the known error position indicated by the pointer obtained by C1 decoding, and if the error correction is incorrect in the C1 correction, the erasure correction will also be incorrect.

In C1 decoding, there are two cases where error correction is incorrect. One of them is a case where erroneous correction occurs due to multiple correction in C1 decoding. Second, even if C1 correction itself correctly corrects errors, C2
Looking at the series, this is a case where errors are included. The latter case occurs when frame discontinuity as described above occurs.

Therefore, an object of the present invention is to provide a control device for an error correction circuit that can prevent errors in erasure correction when performing erasure correction using a CI pointer in C2 decoding.

[Means for solving problems]

In the present invention, a first error correction code sequence is formed from the l word included in each of the PCM data sequences of the plurality of channels in the first arrangement state and a first check word for this, and the PCM data sequence of the plurality of channels is The data sequence and the first checkword sequence are delayed for different times for each channel to obtain a second arrangement state, and each of the PCM data and the first checkword sequence of the plurality of channels in this second arrangement state contains A second error correction code sequence is formed, which is made up of one word that is detected and a second check word for this, and when decoding, the pointer information obtained by decoding the first error correction code sequence is used to detect the second error. In a control device for an error correction circuit configured to decode a correction code series, error correction and erasure correction are performed for a second error correction code series, and when frame discontinuity of an input signal occurs, Erasure correction is prohibited for a predetermined period of time.

[Effect]

When frame discontinuity occurs, the C1 code sequence is only interleaved with two frames, so only the two frames of the C1 sequence in the discontinuous part are detected as errors.In the C2 sequence including the discontinuous part, multiple errors occur. is occurring. In this case, if erasure correction is performed while trusting the C1 pointer, the erasure correction will be incorrect. In this invention, erasure correction is prohibited for a predetermined period when frame discontinuity occurs, so that the above-mentioned erroneous erasure correction can be prevented.

〔Example〕

An embodiment of the present invention will be described below.

This description is given in the following order.

a. Digital audio disk playback circuit A. Synchronization signal detection and protection circuit C. Error correction circuit a. Digital audio disk playback circuit FIG. 1 shows a digital audio disk playback circuit to which the present invention can be applied. This is an example. In Figure 1,
l indicates a digital audio disc. An RF multiplied signal reproduced by an optical pickup 2 is supplied from this digital audio disk 1 to an RF amplifier 3.

FIG. 2 shows the RF multiplied signal frame structure reproduced from a digital audio disc.

At the beginning of one frame, a frame synchronization signal of 24 channel bits is located, followed by one symbol of a subcode for control and display. After this, audio PCM
signal (12 symbols), error correction code parity (
4 symbols), audio PCM signal (12 symbols)
and parity (4 symbols) are located sequentially. One symbol is 14 channel bits. An l frame has a length of 588 channel pits, as described below.

24x14 (audio signal) + 8x14 (parity 4
)+lX14 (subcode)+24(frame same
)H8l +34 x 3 (margin bit) = 58
The output signal of the 8-channel bit RF amplifier 3 is supplied to a clock extraction circuit 4 composed of a PLL. The reproduced RF signal and pit clock from the clock extraction circuit 4 are supplied to the frame synchronization detection and protection circuit 5.

The frame synchronization detection and protection circuit 5 detects a frame synchronization signal and protects the detected frame synchronization signal, as will be described later.

An EFM demodulation circuit 6 is provided at the output of the frame synchronization detection and protection circuit 5. For EFM modulation, a pattern of 8 pits per symbol is preferable (in the sense that the DC component can be reduced and the bit clock can be easily extracted)14
This is channel coding that converts bits into patterns. The EFM demodulation circuit 6 supplies reproduced data in which one symbol is returned to 8 bits to the decoding circuit 7.

The decoding circuit 7 decodes an error correction code (referred to as a cross-interleaved Reed-Solomon code (CIRC code)). A memory 8 in which reproduced data is written for deinterleaving and the like is provided in association with the decoding circuit 7.

A signal indicating that the frame synchronization has lost lock due to a track jump or the like is supplied from the frame synchronization detection and protection circuit 5 to the decoding circuit 7. Further, the decoding circuit 7 is supplied with a key from the system controller 14.
Track jump commands that occur during operations such as review are supplied.

The reproduced audio data output from the decoding circuit 7 is supplied to the data interpolation circuit 9. The data interpolation circuit 9 performs interpolation such as average value interpolation and previous value hold on the error data that could not be corrected by the decoding circuit 7. The output signal of the data interpolation circuit 9 is connected to the D/A converter 10L and IOR.
The audio PCM signal is converted back into an analog signal.

Output signals from these D/A converters 10L and 10R are taken out to output terminals 12L and 12R via low-pass filters IIL and IIR.

A subcode demodulation circuit 13 is provided on the output side of the frame synchronization detection and protection circuit 5. Subcode demodulation circuit 1
The subcode obtained from 3 is the system controller 14
is supplied to In connection with the system controller 14,
An operation section 15 and a display section 16 are provided.

Motor 1 that rotates digital audio disk 1
7 is driven by a spindle servo circuit 18 at CLV (constant linear velocity). In connection with the optical pickup 2, a feed servo circuit 19, a tracking servo circuit 20, and a focus servo circuit 21 are provided.

b. Synchronization signal detection and protection circuit FIG. 3 shows an example of the frame synchronization detection and protection circuit 5. In FIG.
58B), the counter 31 is connected to the terminal 33
The counter 32 counts the clock PLC from the terminal 34, and the counter 32 counts the clock FIC from the terminal 34. clock PLC
is a bit clock extracted from the reproduced RF signal by the clock extraction circuit 4. The clock FIC is a fixed stable lock formed, for example, by a crystal oscillator circuit (not shown). The frequency of the clock FIC is 4.3218M7, which is equal to the center frequency of the clock PLC.

The outputs of counters 31 and 32 are supplied to decoders 35 and 36, respectively. The decoder 35 generates an interpolation synchronization signal N5YNC every time the output of the counter 31 reaches 588, and the decoder 36 generates an interpolation synchronization signal N5YNC every time the output of the counter 32 reaches 588.
A window signal LMASK which becomes "1" with a width of (±8 clocks) is generated around the timing when .

Counters 31 and 32 are reset by detection synchronization signal MKDSY from AND gate 41.

37 indicates a shift register, and this shift register 3
At 7, the reproduced RF signal EFM is taken in by the clock PLC. The shift register 37 is a 23-bit one.
The output signal of the shift register 37 is supplied to a frame synchronization detection circuit 40.

A frame synchronization detection circuit 40 detects a frame synchronization signal having a predetermined bit pattern. Synchronization detection circuit 40
A playback synchronization signal 5YNC from 5YNC is supplied to an AND gate 41. As the other input signal of the AND gate 41, O
A window signal MASK from R gate 57 is supplied.

The detected synchronization signal MKI)SY from the AND gate 41 is supplied as a reset signal to the above-mentioned counters 31 and 32, and is also supplied to the AND gate 42 and the inverter 4.
3. The output signal of inverter 43 is supplied to AND gate 44 .

A decoder 35 is connected to these AND gates 42 and 44.
An interpolation synchronization signal N5YNC is supplied from. AND)
The signal GDSY is taken out from the gate 42, and the A
Signal NGSY is taken out from ND gate 44. Signal GDSY is a signal obtained when detection synchronization signal MKDSY and interpolation synchronization signal N5YNC are generated simultaneously.

The signal NGSY is a signal obtained when the interpolation synchronization signal N5YNC is generated but the detection synchronization signal MKDSY is not generated. In addition, these signals GDSY and signal NG
An RS flip-flop 45 is provided which is set and reset by SY, and a signal GFS is taken out from the RS flip-flop 45.

The above-mentioned interpolation synchronization signal N5YNC and detection synchronization signal MKDS
Y is supplied to an OR gate 46, and a reset (RESET) signal is taken out at an output terminal 47. This reset signal is an output signal that defines the timing corresponding to the frame synchronization signal in the reproduced RF signal. That is, each symbol of the reproduced RF signal is separated using a reset signal, which is a data clock, as a reference.

The signal GDSY from the AND gate 42 is sent to the N1 counter 4.
8 as a clock input. AND gate 44
A signal NGSY from NGSY is provided as a clock input to N2 counter 49. The carry output of the Nl counter 48 is used as its own reset input via the OR gate 50, and is also used as the reset input of the RS flip-flop 52.

The output signal GDF of the RS flip-flop 52 is supplied as the other input of the OR gate 50.

The carry output of the N2 counter 49 is used as its own reset input via an OR gate 51 and is also supplied to an OR gate 53. A detection synchronization signal MKDSY is supplied as the other input of the OR gate 51. The OR gate 53 receives the output signal of the AND gate 54 and the terminal 55.
The signal from AND gate 54 has R
Output signal GDF and signal NGS of S flip-flop 52
Y is supplied. The signal from the terminal 55 is a signal that becomes "1" when a tracking error or the like occurs. This signal is used to control the removal of forward protection after a track jump.

The output signal of the OR gate 53 is sent to the SR flip-flop 52.
and 56 as respective set inputs.

A detection synchronization signal MKDSY is supplied as a reset input of the RS flip-flop 56. The signal GTOP obtained at the output of the RS flip-flop 56 is output to the OR gate 57.
is supplied to

This OR gate 57 is supplied with a window signal LMASK.

The N1 counter 48 described above is used to detect that the signal GDSY has been generated N1 times, that is, that frame synchronization detection is locked! ! ! It is provided for (rear protection i). On the other hand, the N2 counter 49 indicates that the signal NGSY is N2.
This is provided for protection (front protection) to detect that the lock has been released, that is, that the lock has been released. -For example,
It is set as (N 1-2) (N2=3).

FIG. 4 is a timing chart showing the operation of the above-mentioned embodiment. FIG. 4A shows the reproduction synchronization signal 5YNC from the frame synchronization detection circuit 40.

4B indicates the window signal MASK supplied to the AND game) 41. Normally, the signal GTOP shown in FIG. 4J
Since is "0", the window signal LMASK from the decoder 36 becomes the window signal MASK. Therefore, the detected synchronization signal MKDSY shown in FIG. 4C is obtained.

The fourth diagram shows the interpolated synchronization signal N generated from the decoder 35.
Due to the disturbance of the clock PLC indicating 5YNC, the interpolated synchronization signal N5YNC contains bit slips or erasures whose period is different from the normal one. 4 from the detection synchronization signal MKDSY and the interpolation synchronization signal N5YNC shown in FIG. 4C.
Signal GDSY shown in Figure 4 and signal NGSY shown in Figure 4F
is formed.

The signal GDSY is supplied to the Nl counter 48, and the output of the Nl counter 48 changes as shown in FIG. 4G. (
Nl-2), when the Nl counter 48 counts up to 2, it generates a carry output, and this carry output resets the Nl counter 48 and the RS flip-flop 52. Therefore, the output signal GDF of the RS flip-flop 52 becomes “
Also, the signal NGSY is output to the N2 counter 49.
The output of the N2 counter 49 changes as shown in FIG. 4H. Since the N2 counter 49 is reset by the detection synchronization signal MKDSY, no carry output is generated from the N2 counter 49. Therefore, the signal GTOP from the RS flip-flop 56 becomes "0" as shown in FIG. 4J. ” is.

Since the OR gate 46 is supplied with the interpolation synchronization signal N5YNC and the detection synchronization signal MKDSY, the output terminal 47
Then, a reset signal shown in FIG. 4K is taken out. In this reset signal, when both the interpolation synchronization signal N5YNC and the detection synchronization signal MKDSY occur, the period between the interpolation synchronization signal N5YNC and the detection synchronization signal MKDSY becomes a burst error period. However, the period of this burst error is relatively short and can be corrected by the error correction code of the digital audio disc.

FIG. 5 is a timing chart showing the operation when the reproduction synchronization signal becomes erroneous, such as during a track jump. As shown in Figure 5A, the playback synchronization signal disappears,
An incorrect playback synchronization signal (marked with an x) is generated. When the signal GTOP (FIG. 5J) is "0", the window signal LMASK having a width of (±8 clocks) is generated from the decoder 36 in FIG. 5B. Therefore, the detected synchronization signal MKDSY shown in FIG. 5C is obtained. Since the counter 31 is reset by this detection synchronization signal MKDSY, the interpolation synchronization signal N5YNC shown in Fig. 5
occurs. Therefore, even when the playback synchronization signal disappears,
An interpolated synchronization signal N5YNC is obtained, and the fifth
A reset signal is obtained as shown in Figure K.

FIG. 5E and FIG. 5F represent signals GDSY and NC, respectively;
It shows SY. These signals GDSY and NGSY
are counted by the Nl counter 48 and the N2 counter 49, and their respective outputs change as shown in FIGS. 5G and 5H. When three signals NGSY are counted, the N2 counter 49
A carry output is generated from the RS flip-flop 52.
and 56 are set. Therefore, as shown in FIG. 51 and FIG. 5J, the signal GDF and the signal GTOP are "1 m
becomes. Since the RS flip-flop 56 is reset by the detection synchronization signal MKDSY, the signal GTOP shown in FIG. 5J is generated. Also, the signal GDF is “1”
The RS flip-flop 56 is set by the signal NGSY generated during the period .

Furthermore, when the N1 counter 48 counts the two signals GDSY, a carry output is generated from the N1 counter 48, and R
S flip-flop 52 is reset. Therefore, the signal GDF falls as shown in FIG. 5I.

A reset signal shown in FIG. 5K is taken out to the output terminal 47. A burst error occurs during a period when the signal GTOP is "L". This error period can be shortened.

As is clear from the above operation description, the Nl counter 48
performs a backward protection operation to detect that the frame synchronization detection operation has returned to normal. The N2 counter 49 performs a forward protection operation to detect an error in the frame synchronization detection operation.

By protecting both, it is possible to quickly detect that the frame synchronization detection operation has become abnormal and that the detection operation has returned to normal.

C. Error Correction Circuit The error correction circuit provided in the decoding circuit 7 and to which the present invention can be applied will be explained with reference to FIG. FIG. 6 is a block diagram showing the decoding order.

The playback signal from the digital audio disc is
It is supplied from the M demodulation circuit 6. Thirty-two symbols in one frame are supplied to the delay processing stage, and only even symbols are delayed by one frame, and the delay given by the encoder-side delay circuit is canceled.

The 32 symbols from the delay processing stage 61 are supplied to the C1 decoder 62, and the (32, 28) Reed-Solomon code is decoded by the Ct decoder 62. In the C1 decoder 62,
Up to two error symbols in the C1 sequence are corrected. In the C1 decoder 62, when triple or more errors are detected, a 01 pointer with an error is set for all symbols in the C1 sequence.

The data corrected by the C1 decoder 62 and the C1 pointer are processed in the deinterleave processing stage 63. The deinterleave processing stage 63 performs processing to restore the interleaving performed on the encoder side, and the output of the deinterleave processing stage 63 is supplied to the C2 decoder 64. C
The C1 pointer of each symbol generated by the 1 decoder 62 is
At the deinterleave processing stage 63, the data is subjected to the same deinterleaving process as the data. Delay processing and deinterleaving can be performed by controlling the address when reading data from the RAM. The Cl pointer is written in a partial memory area of the RAM and is subject to the same address control as data. The C2 decoder 64 uses the Cl pointer to
Correction of up to two symbol errors and erasure correction of triple and quadruple errors are performed.

The data from the C2 decoder 64 is sent to the interleave processing stage 6.
5. The interleaving processing stage 65 restores the data arrangement to the same arrangement as the arrangement at the time of reproduction. The output data of the interleaving processing stage 65 is supplied to the delay processing stage 66, and the data of one frame (32 symbols) is outputted from the delay processing stage 66. is obtained. In practice, C1 decoder 62 and C2
Since the data corrected by the decoder 64 is stored in the RAM, the processing of the interleave processing stage 65 and the delay processing stage 66 can be performed by controlling the read address of this data.

A second decoding process is performed from the interleave processing stage 65. The second decoding process is the same as the Reed-Solomon code decoding in the already known digital audio disc playback circuit.

Thirty-two symbols of data from delay processing stage 66 are supplied to C1 decoder 67. In the C1 decoder 67, (32, 2
8) Reed-Solomon code is decoded and up to double errors are corrected. In the C1 decoder 67, the Cl pointer is set not only when there are three or more errors, but also when double errors are corrected.

The output data from the C1 decoder 67 is supplied to a deinterleave processing stage 68, where it is deinterleaved. The 28 symbols of data from the deinterleave processing stage 68 are supplied to the C2 decoder 69, where the (28, 24) Reed-Solomon code is decoded. The C2 decoder 69 refers to the number and status of Cl pointers to correct up to double errors. The output data from the C2 decoder 69 is supplied to a descrambling stage 70, where it undergoes a process inverse to the scrambling process performed on the encoder side.

As mentioned above, the C1 pointer generated by the C1 decoder 62 is used to perform triple and quadruple erasure correction in the C2 decoder 64, which increases the number of error symbols that can be corrected and improves the error correction capability. can be achieved.

By performing C1 decoding and C2 decoding again, the possibility of erroneous correction can be reduced.

FIG. 7 is a flowchart showing the operation of the C1 decoder 62. In the case of 1 symbol error and 2 symbol error, error correction is performed. The Cl pointer is set when a two-symbol error is corrected and when there is an error of three or more symbols. The reason why the C1 pointer is set even when a 2-symbol error is corrected is because there is a high probability that CI correction will be incorrect. 01 pointer is required. If there is no error and if the l symbol error is corrected, it is determined whether the C1 pointer is forced to be set.

If the C1 pointer is forced to be set, the Cl pointer is set; otherwise, the C1 pointer is cleared. Whether or not to forcibly set the Cl pointer is determined according to the flowchart shown in FIG. As shown in FIG. 8, after a track jump command is input from the microcomputer, the signal GTO
When P becomes "1", the 01 pointer is forcibly set.

Or the signal R indicating that the RAM has overflowed.
When AOF becomes "1", the Cl pointer is forcibly set. The forced setting of the Cl pointer is done for the next 128 frames when the frame becomes discontinuous. Here, 128 frames is a value determined according to the following formula.

74+28+16-118-128 (frame) 74:
Mixed period of data before and after the discontinuity point determined by the interleaving relationship 28: When jitter margin of ±28 frames 16: Number of forward protection for frame synchronization (3 in the frame synchronization and protection circuit described above) N2
Example of value) As mentioned above, when frames become discontinuous due to track jump, etc., the period of 128 frames is forced.
By setting the Cl pointer, the C2 decoder 64
correction is no longer possible, and the sounds before and after the discontinuity point are prevented from mixing.

FIG. 9 is a flowchart showing the decoding operation of the C2 decoder 64. FIG. 9 shows the decoding process after it is determined that there is no error, 1 symbol error, 2 symbol error, 3 symbol error, 4 symbol error, or 5 or more symbol errors.

Furthermore, pointer processing is omitted.

Error correction is performed when there is no error, when there is a 1 symbol error, and when there is a 2 symbol error. In the case of a 3-symbol error and in the case of a 4-symbol error, it is determined whether erasure correction is prohibited. If not prohibited, triple erasure correction and quadruple erasure correction are performed. If erasure correction is prohibited or if there are errors of five or more symbols, erasure correction is not performed.

Erasure correction is prohibited when frame discontinuity occurs. The occurrence of this discontinuity is caused by the signal G T OP
It is detected because the signal RAOF becomes 1" or the signal RAOF becomes 11". From the detection of frame discontinuity, 180
Erasure correction is prohibited for the duration of the frame. 180
The period of the frame is determined by the condition of the following formula.

108+56+16-180 (frame) 108: Interleaving length 56: When jitter margin is ±28 frames 16: Number of forward protection for frame synchronization (an example of the value of N2 which was 3 in the frame synchronization and protection circuit described above) As described above , forces the Cl pointer to be set for a period of 128 frames, and in C2 decoding,
FIG. 10 shows an example of an error correction control circuit for inhibiting erasure correction over a period of 180 frames.

In FIG. 1O, the signal GTOP from the frame synchronization detection and protection circuit 5 is supplied to an input terminal indicated at 71.

As mentioned above, this signal GTOP is a signal that becomes "1m" after counting a predetermined number of signals NGSY, for example 16.The input terminal 72 has a memory 8 (RAM).
A signal RAOF which becomes "1" when overflow occurs is supplied. This signal RAOF is a signal that compares the output of the write address counter of the memory 8 with the output of its read address counter, and becomes "L" when the difference between the two becomes 28 (jitter margin). A track jump command (“1°”) for cueing, reviewing, etc. is supplied from the microcomputer to an input terminal 73. A track jump command (“1°”) for cueing, reviewing, etc. is supplied to an input terminal 74 from a read address generation circuit of the memory 8. A clock with a period of one frame is supplied.

A control signal for forcibly setting the Cl pointer is output to an output terminal 75, and a control signal for inhibiting erasure correction is output to an output terminal 76. The output terminal 75 is the RS flip-flop 7
The output terminal 76 is connected to the output of a D flip-flop 78.

79 indicates a 7-bit counter, and this counter 79
From the NAND gate 80, a counter 79 receives 128 clocks R.
When counting FCK, a falling output signal is generated.

81 indicates an 8-bit counter, and this counter 81
The output of is supplied to NAND gate 82. From the NAND gate 82, the counter 81 receives 180 clocks R.
When counting FCK, a falling output signal is generated.

The clock RFCK is supplied to AND gates 84 and 85 via a fall detection circuit 83.
The output signal of A 4 is used as the clock input of the counter 79,
The output signal of the ND gate 85 is used as the clock input of the counter 81.

A signal RAOF for detecting RAM overflow is supplied to a D flip-flop 86 and an OR gate 87.

A track jump command from terminal 73 is supplied as the other human input signal to OR gate 87 . OR gate 87
The output of is used as the set input of the RS flip-flop 88 and is also supplied to the OR gate 89. OR gate 8
The output signal of 9 is supplied to the load terminal of counter 79.

As the other input of OR gate 89, signal GTOP is provided.

The RS flip-flop 88 is set by the signal RAOF or the track jump command, and its output signal is
It is supplied to D gate 90. The output of AND gate 90 is supplied to RS flip-flop 77 as a set input. The output signal of OR gate 91 is supplied as the other input signal of AND gate 90 . The signal GTOP and the output signal of the D flip-flop 186 are supplied to the OR game 91. Therefore, the RS flip-flop 88
is set by signal RAOF or track jump command, signal GTOP or signal RAOF (
D flip-flop 86 output) is supplied, RS
Flip-flop 77 is activated and forced setting of the C1 pointer begins.

When counter 79 detects 128 frame periods after the forced setting of the C1 pointer begins, the NAND
The output signal of the gate 80 becomes "Om", and this fall is detected by the fall detection circuit 92.The output signal of the fall detection circuit 92 resets the RS flip-flops 77 and 88, and the Cl pointer is forcibly reset. The set operation is completed.

Also, the signal GTOP and the signal R are connected to the OR gate 93.
AOF is supplied, and the output of OR gate 93 is sent to counter 8.
1 load terminal. When the output of the OR gate 93 is supplied to the load terminal of the counter 81, all of its outputs are no longer 1 m, and the output signal of the NAND gate 82 becomes "1".

Therefore, the control signal taken out from the D flip-flop 78 to the output terminal 76 becomes "1", and prohibition of erasure correction is started.

When the counter 81 counts 180 clocks passed through the AND gate 85, the output signal of the NAND gate 82 becomes "0" and the control signal taken out to the output terminal 76 also becomes "θ". Therefore, the erasure correction prohibition operation is canceled.

The decoding circuit 7 receives a control signal for forcibly setting the C1 pointer obtained at the output terminal 75 and a control signal for prohibiting erasure correction obtained at the output terminal 76.
is supplied to the microcomputer that controls it.

〔Effect of the invention〕

According to this invention, error correction capability can be improved by performing quadruple erasure correction. Also,
According to the present invention, erasure correction is prohibited when frame discontinuity occurs and the C1 pointer becomes unreliable, so that erroneous erasure correction can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an example of a digital audio disc playback system to which the present invention can be applied;
Figure 2 is a route diagram used to explain the frame structure of the playback signal of a digital audio disc, Figure 3 is a block diagram of an example of a frame synchronization detection and protection circuit, and Figures 4 and 5 are frame synchronization detection and protection circuits. FIG. 6 is a block diagram used to explain an error correction circuit to which the present invention can be applied.
7 and 8 are flowcharts used to explain C1 decoding, FIG. 9 is a flowchart used to explain C2 decoding, and FIG. 10 is a block diagram of a control device for an error correction circuit.
FIG. 11 is a route map used to explain a cross-interleaved Reed-Solomon code to which the present invention can be applied. Explanation of main symbols in the drawings 1: Digital audio disk, 4: Clock extraction circuit, 5: Frame synchronization detection and protection circuit, 62.67: C1 decoder, 64.69: C2 decoder, 75: Force CI pointer 76: Output terminal of a control signal for prohibiting erasure correction. Figure 6, No. C14, Figure 7, Figure 9, Figure 11

Claims (1)

[Scope of Claims] A first error correction code sequence is formed consisting of one word included in each of the PCM data sequences of a plurality of channels in a first arrangement state and a first check word for this, and the plurality of A second arrangement state is obtained by delaying the PCM data series of the channel and the first checkword series by different times for each channel, and the PCM data of the plurality of channels and the first checkword series in this second arrangement state are A second error correction code series is formed from one word included in each word and a second check word for this, and at the time of decoding, pointer information obtained by decoding the first error correction code series is used. In the control device for the error correction circuit, which performs decoding of the second error correction code series, the control device performs error correction and erasure correction with respect to the second error correction code series, and performs frame error correction of the input signal. A control device for an error correction circuit, characterized in that the erasure correction is prohibited for a predetermined period when a continuity occurs.