JPH0252350B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is suitable for, for example, a digital recording (reproduction) system, and when performing digital-to-analog conversion with data correction, different types of data are generated at the moment reproduction data is switched from a plurality of recording systems. The present invention relates to a digital-to-analog conversion device that is improved so that an abnormal signal is not derived from an analog signal that has been incorrectly converted.

In conventional analog tape recorders, disk recorders, etc., changes in the amplitude of analog signals such as acoustic signals are interpreted as changes in the strength of magnetization or
This was converted into a change in the amplitude of the sound groove, and the temporal change was recorded in correspondence with the running direction of the tape or disk. Therefore, the performance of the head tape, needle, etc. affects the signal's dynamic range and distortion rate, and the performance of the drive system affects the signal's frequency characteristics, wow and flutter, spade deviation, modulation noise, etc. Furthermore, the analog recording (reproducing) system is currently a technically complete system, and it is technically difficult to make any significant performance improvements.

On the other hand, recently developed digital recording (playback) systems first process temporal changes in signals as discrete quantities (sampling), then convert the amplitude as a discrete quantity (quantization), and then digitally recorded on etc. Therefore, the logic level is "0" during playback.
If it can be determined whether the waveform is "1" or "1", it is possible to completely restore the original waveform. By digitizing and recording in this way, there are no speed deviations, wow/flutter, or level fluctuations, DC playback is possible, and there is no deterioration due to dubbing. It also has the advantage that the dynamic range, distortion rate, and frequency characteristics can be designed arbitrarily.

This digital recording (reproduction) system is performed by a pulse code modulation (PCM) recording (reproduction) device as shown in FIG. This PCM recording (playback)
The apparatus has a recording section 11 and a reproducing section 12, and a recording signal such as an audio signal digitally encoded by the recording section 11 is recorded by a video tape recorder 13. The recorded digital signal is then converted into the original analog signal by the reproducing section 12 and treated as a normal signal.

However, when each digitally recorded signal from a plurality of video tape recorders 13a and 13b is switched and played back by a switch S as shown in FIG.
In the reproducing section 12, each data is mixed with data of different types of acoustic signals as shown in FIG. 3, and is derived as an abnormal signal, which is a fatal drawback for so-called audio systems.

The present invention has been made in view of the above points, and an object of the present invention is to provide an improved digital-to-analog conversion device that does not derive abnormal signals to be reproduced, for example, when switching between multiple video tape recorders for reproduction. shall be.

Hereinafter, as an embodiment of the present invention, a case where the present invention is applied to a PCM recording (reproduction) device will be described in detail with reference to the drawings.

First, the order of explanation of this invention will be briefly explained.

(1) In Figure 4, the overall configuration of the PCM recording (playback) device; (2) in Figure 5, the peripheral circuit configuration including the interleave circuit in Figure 4; (3) in Figure 6, Regarding the operation of the digital-to-analog converter including the interleaving circuit in Figure 4, (4) In Figure 7, regarding the configuration of the error correction detection circuit and muting circuit in Figure 4, (5) In Figure 8, Regarding the clock signal, .

FIG. 4 shows the overall configuration of the coded modulation PCM device, and the analog audio signals of the A and B channels are input to the input terminals 14 and 15.
low-pass filters 16, 1 in the recording section 11 through
7, where unnecessary harmonic components are cut off, thereby making the cut-off characteristics of the acoustic signal steep. And the low-pass filter 16,1
The acoustic signal from 7 is sampled by a sampling pulse in sample-and-hold circuits 18 and 19, and then input to a multiplexer circuit 20, where it is converted into a quantum signal by one analog-to-digital converter for two channel inputs. We are trying to make it possible. That is, the sampled signals of channels A and B alternately output from the multiplexer circuit 20 are sequentially and alternately sent to the analog-to-digital converter 21 and quantized, and then sent to the demultiplexer circuit 22.
For example, six sets of sampled signal words A1,
It is used to generate B1, A2, B2, A3, and B3. These six sets of sampled signal words are sent to an interleave circuit 23 having a memory function and a correction check code generation circuit 24. This interleave circuit 23 is for preventing burst errors caused by magnetic recording, and the correction check code generation circuit 24 generates two error correction words P and Q. These two error correction words are supplied to the interleaving circuit 23. A delay circuit is provided in this interleaving circuit 23 for each sampling signal word and correction word, so that the sampling and correction words from this interleaving circuit 23 are in a temporally dispersed state. become.

Here, the correction words P and Q will be defined.
Now, it is assumed that n words of information data and a two-word correction word code are shown below (provided that one word is made up of m bits).

Here, the symbols P and Q are expressed as follows.

P= _o 〓 ⁱ⁼¹ Wi=W1W2…Wn ……(1) Q= _o 〓 ⁱ⁼¹ T ^(n+1-i) Wi =T ⁿ W1T ^n-1 W2…TWn ……(2) These The code correction word matrix is It is indicated by. Note that T is the generation matrix of the correction word Q, which is an individual non-zero element of the Galois field (2 ^b ) (b is the number of bits of the correction data Q),
For example, it is described in Japanese Patent Publication No. 52-15190. Moreover, the above I is a unit matrix.

In such a data arrangement, by adding the above-mentioned correction word, the data can be completely decoded in case of an error of up to 2 words.
To explain this point, first, rewriting equations (1) and (2) above, P _o 〓 ⁱ⁼¹ Wi=0 ...(3) Q _o 〓 ⁱ⁼¹ T ^(n+1-i) Wi= 0...(4)

Now, the jth and kth data (1≦j≦n, 1
≦k≦n) is lost, the solutions of equations (1) and (2) will not be "0" and will become S1 and S2 of equations (5) and (6) shown below, respectively. Here, the original data word is
Let W1, W2, ..., (Wj), (Wk), ..., Wn, j
Let W1′, W2′, . . . , (Wj′), (Wk′), . However, Wj'=Wj+Wje, Wk'=Wk+Wke, and Wje and Wke are the j-th and k-th error data, respectively.

P _o 〓 ⁱ⁼¹ Wi=S1 ……(5) Q _o 〓 ⁱ⁼¹ T ^(n+1-i) Wi=S2 ……(6) Also, P _o 〓 ⁱ⁼¹ Wi′=WjeWke=S1 ...(7) Q _o 〓 ⁱ⁼¹ T ^(n+1-i) Wi′ =T ^(n+1-j) WjeT ^(n+1-k) Wke =S2 ...(8) and this ( From equation 7), Wje=S1Wke...(9) From equations (8) and (9), S2=T ^(n+1-j) (S1Wke)T ^(n+1-k) Wke...(10) obtain. When this is transformed, T ^(jn-1) S2=S1WkeT ^jk Wke...(11) S1T ^(jn-1) S2WkeT ^jk Wke=(IT ^jk )Wke...(11'). Therefore, Wke=(IT ^jk ) ^-1・{S1T ^(jn-1) S2} ...(12) Wje=S1Wke ...(13) From these equations (12) and (13), using S1 and S2, Lost data Wje, Wke can be decrypted. That is, this correction means decodes Wj, which is the original j-th data, by adding both of them, since there is Wj+Wje at the time of decoding, and if only Wje can be decoded.

Then, each word distributed by the interleave circuit 23 is transferred to a parallel-to-serial converter circuit 25.
and is supplied to the error check code generation circuit 26. This error check code generation circuit 26 generates an error detection word (ECC) and sends it to the parallel-to-serial conversion circuit 25, which distributes each word including the error detection word to the A or B channel.The modulation circuit 27 synchronizes it from the synchronization signal generation circuit 28. It is modulated so that it can be recorded on the video tape recorder 13 along with the signal.

During playback, a quantized signal including a synchronization signal recorded in the video tape recorder 13 is first separated from the synchronization signal by a synchronization signal processing circuit 29. With this synchronization signal separated, sampling and correction words regarding the acoustic signal are extracted by the circuit 3.
The signal is removed as 0, passed through a demultiplexer circuit 31, and then sent to a deinterleave circuit 32 and an error detection circuit 33. The error detection circuit 31 performs error detection by modulo-2 addition, and the deinterleave circuit 32 is provided with information pointing out the error portion.

The amount of delay of each word deinterleaved by this deinterleaving circuit 32 becomes equal, and each word dispersed during the recording is returned to its original state. Then, the restored six sampled words are inputted to the error correction circuit 34 and subjected to error correction, and converted into analog signals by the digital-to-analog converter 36 via the delay circuit 35. This analog signal is divided into A or B channel signals by the demultiplexer circuit 37, and the A channel and B channel acoustic signals are derived from output terminals 42 and 43 via low-pass filters 38 and 39 and switches 40 and 41, respectively. Ru.

Also, the error signal from the error correction circuit 34 is sent to the muting circuit 44, and the low-pass filter 3
Switches 40 and 41 that control the output of the acoustic signals from switches 8 and 39 are configured to operate in conjunction with each other.

FIG. 5 shows the six sampled signal words A1, A1,
This shows a state in which B1, A2, B2, A3, and B3 are input to the interleave circuit 23 and output. That is, the following five sampled signal words excluding sampled signal word A1 are input to delay circuits 23a to 23e in interleaving circuit 23. Further, P and Q correction words generated from the check code generation circuit 24 are inputted to the delay circuits 23f and 23g in accordance with the sampling signal word inputted. For example, if the sampled signal word B1 is interleaved B1-3D, this output state becomes a state in which 3D=48 words are interleaved, and 3ND (N is 1, 2
…) will be delayed.

Note that D in the interleaving circuit 23 of this embodiment is D when one period of the horizontal synchronizing signal is 1H in an NTSC video tape recorder.
= means a delay state of 16H. That is, each output word is A1→A1, B1→B1-3D,
A2→A2-6D, B2→B2-9D, A3→A
3-12D, B3→B3-15D, P→P1-1
The signal words sequentially sampled as 8D, Q→Q1-21D are interleaved.

FIG. 6 shows in detail the configuration of the main parts of the digital-to-analog converter according to this embodiment.
That is, in the reproducing unit 12, the interleaved sampled signal words A1, B1-3D, A2-6D, B2-
9D, A3-12D, B3-15D and correction words P1-18D, Q1-21D except correction word Q1-21D, each word is connected to delay circuits 32a to 32 in deinterleave circuit 32, respectively.
g. Also, these eight words are
The error detection circuit 33 is supplied with an error detection word (ECC) generated and added by the error check code generation circuit 26 to detect the presence or absence of an error, and a 1-bit instruction indicating the detection result. Data Ep (error pointer) is added to each word and supplied to delay circuits 32a to 32g, respectively. Note that since the correction word Q1-21D is not delayed, the instruction data added to it
Ep will not be delayed either.

Then, each word and correction word Q1-21D output from the delay circuits 32a to 32g and the instruction data Ep added thereto are sent to a correction data detection circuit 45. This correction data detection circuit 45 detects sampled signal words A1-21D, B1-21D, A2 which have been subjected to deinterleaving processing and which are output from the delay circuits 32a to 32g, based on the input word and instruction data Ep.
-21D, B2-21D, A3-21D, B3-
Error data for 21D is generated and output to the error correction circuit 34. In other words, as mentioned earlier, data Wi′ when error data Wie is added to certain correct data Wi is Wi′=WiWie, so correct data Wi can be found by Wi=Wi′Wie. Can be done. In this case, the words A1-21D, which are supplied to the error correction circuit 34,
B1-21D, A2-21D, B2-21D, A
3-21D and B3-21D are data Wi' to which error data Wie has been added, and since the error data Wie is output from the correction data detection circuit 45, the error correction circuit 34 logically converts the input word and the error data. Error correction is performed by addition (actually exclusive OR operation).

The corrected data detection circuit 45 also controls the mutating circuit 44 by controlling the switches 40 and 4.
A mutating command signal, the details of which will be described later, for controlling 1 is generated and output.

In the digital-to-analog conversion device configured as described above, especially when reproducing audio signal information digitally recorded by the video tape recorder 13,
Synchronization processing circuit 2 from the quantized signal containing the synchronization signal
9 separates the synchronization signal, and further removes the signal from the circuit 30.
The sampling signal word and the correction word are extracted at , and converted into parallel signals by a demultiplexer circuit 31 . The sampled signal word and the correction word converted into parallel signals are in the interleaved state applied by the interleaving circuit 23 during recording mentioned above, and are changed to the interleaved state of the correction words Q1-21D by the deinterleaving circuit 32. Deinterleaving is also performed to make all the delay amounts equal. That is, for sampled signal word A1, A1-21
D, hereinafter referred to as B1-3D-B1-21D, A2
-6D→A2-21D, B2-9D→B2-21
D, A3-12D → A3-21D, B3-15D
→B3-21D, P1-18D→P1-21D. As a result, the signals are output during playback in the same order as the input signals during recording.

Further, the error detection circuit 33 detects errors caused by bursts, etc., and sends the detected data to the correction data detection circuit 45. This corrected data detection circuit 45 includes the error detection circuit 33
Based on instruction data Ep from , only error words are generated from correction words P and Q and sent to error correction circuit 34 .

Here, the correction words P and Q obtained by the check code generation circuit 24 are calculated using the above-mentioned equations (1) and (2).
According to the definition of P and Q by the formula, P=A1B1A2B2A3B3 Q=T ⁶ A1T ⁵ B1T ⁴ A2 T ³ B ² T ² A3TB3, then the following equation is P= ₆ 〓 ⁱ⁼¹ Wi Q= ₆ 〓 ⁱ⁼¹ T ^7-1 Wi. Therefore, if there are no errors, both S1 and S2 from the corrected data detection circuit 45 will be "0".

However, if the error detection circuit 33 does not generate error instruction data Ep for 8 words of data, there is a possibility that S1 and S2 will not become "0" due to (1) the detection capability limit of the error detection circuit 33; There are two possible cases: (2) a case where different types of data are mixed together as shown in Fig. 3; Among these, in case (1), if there is one error word, the position of the error word is detected and corrected using S1 and S2, but in case (2), the contents of the deinterleave circuit 32 are the same. Until it becomes a word, it is derived as an abnormal sound.

In other words, the instruction data Ep gives an error instruction to the words in the column shown in FIG. 3, that is, the words that have been subjected to interleaving processing. All the words in the columns in the figure are from the VTR 2, and if there is no error in the words in the columns, the instruction data Ep will not be generated. However, since S1 and S2 indicate errors in words after deinterleaving processing, that is, words in the diagonal direction in Figure 3, different types of data will naturally be mixed if you switch from VTR1 to VTR2. Therefore, a state other than "0" will occur.

Here, since the correction data detection circuit 45 detects that the content of the deinterleaving circuit 32 is erroneous, and there is no instruction data Ep, S1,
For example, the state where S2 is not "0" is within one block (a unit in which error detection and correction processing can be performed using a pair of correction words and error detection words for correction processing when an error occurs in word data for multiple information words). If there is even one of them, muting may be applied to prevent output.

However, it is never desirable to control the output terminal every time. That is, when such a condition occurs in one block, it is better to compensate by averaging the data before and after the block. It becomes a more convenient device especially as an audio system.
Therefore, the above-mentioned error due to different types of data is caused by the lack of instruction data Ep several times within several blocks in S1 and S2.
It is conceivable to control the output so that it does not output when the state in which both do not become "0" continues.

FIG. 7 shows a specific example of the mutating command signal generating portion of the corrected data detection circuit 45 and the mutating circuit 44. In FIG. That is,
The corrected data detection circuit 45 supplies the input 8-bit instruction data Ep and the syndromes S1 and S2 obtained through arithmetic processing to O detection circuits 46, 47, and 48, respectively. Of these, the O detection circuit 46 detects that when the instruction data Ep is all "0", that is, the instruction data Ep added to each word after deinterleaving processing is "0" (as a result of error detection by the error detection circuit 33). When there is no error detection result by the error detection circuit 33), "0" data is output, and when there is at least one "1" in the instruction data Ep (when there is an error detection result by the error detection circuit 33), "1" data is output. Further, the O detection circuits 47 and 48 output "0" data when the syndromes S1 and S2 are "0", and output "1" data when the syndromes S1 and S2 are not "0".

The outputs of the O detection circuits 47 and 48 are ANDed with the output of the O detection circuit 46 by AND circuits 49 and 50, and the outputs of the AND circuits 49 and 50 are ANDed by an AND circuit 51. By taking , a muting command signal is generated which becomes "1" in a state where there is no instruction data Ep and syndromes S1 and S2 are both not "0".

Here, the muting command signal output from the corrected data detection circuit 45 is supplied to the input terminal 70 of the muting circuit 44. This input terminal 7
0 is connected to one end of an 8-bit shift register 71 and an EX OR circuit 72. The output terminals A to H of this 8-bit shift register 71 are connected to the O detection circuit 7.
3 are connected to each other. The output terminal H of this shift register 71 is connected to the EX OR circuit 7.
2 and is connected to the other end of the NAND circuit 74.
connected to one end of the The output end of this EX-OR circuit 72 is connected to the other end of the NAND circuit 74, and is also connected to the input end T of an up-down counter 76 via an inverter 75. The input terminal L0 of this up-down counter ₇₆ is connected to the output terminal of the O detection circuit 73 via an inverter 77, and the output terminal of the NAND circuit 74 is connected to the input terminal U/D. . The output terminal CA of this up-down counter 76 is connected to the input terminal P via an inverter 78, and the output terminals Q _A and Q _B of this up-down counter 76 are each connected to an AND circuit 79, and the output terminal Q _C is connected to one end of the NOR circuit 80. The output end of the AND circuit 79 is connected to the other end of the NOR circuit 80, and a muting signal is derived from the NOR circuit 80.

Note that a clock signal as shown in FIG. 8a is supplied to the clock input terminal CK of the shift register 71 via the inverter 81. Further, the clock signal and the bit clock signal are each input to a NAND circuit 82, and from the output terminal of this NAND circuit 82, the up-down counter 7 is inputted.
A clock signal as shown in FIG. 8b is supplied to the clock input terminal CK of 6.

Muting circuit 44 configured in this way
generates a muting signal when there is no instruction data Ep and S1 and S2 are not "0" three times within the range of 8H (8 periods of the horizontal synchronizing signal).

That is, when the muting command signal output from the correction data detection circuit 45 is "0", that is, when there is no abnormality due to mixing of different types of data, all outputs of the shift register 71 are "0",
When the output of the EX OR circuit 72 is "0", the inverter 7
The output of 5 becomes "1". The up-down counter 76 performs a counting operation when both input terminals T and P are "0", and no counting operation is performed in this state. Also, in this state,
When the output of the O detection circuit 73 is "1", the inverter 77
Since the output of the up-down counter 76 becomes "0", the output terminals Q _A , Q B , Q C become "0", and the output terminals Q A , Q _B , Q _C become "0".
It is preset to the value of c. In other words, input terminal a,
Since b and c are at the ground level "0", the input terminal Q _A ,
Q _B and E _C are also all "0".

In this state, when an abnormality due to mixing of different data is detected and the muting command signal becomes "1" as shown in FIG. 8c, the input terminal 70
becomes "1" and the output terminal H of the shift register 71 is "0", so the output of the EX OR circuit 72 becomes "1" and the output of the inverter 75 is inverted to "0". Also, at this time, since the output of the EX OR circuit 72 is "1" and the output terminal H of the shift register 71 is "0", the output of the NAND circuit 74 is "1".
becomes. Then, the up-down counter 76 is
The output terminal CA is the output terminal Q _A , Q _B , Q _C and the input terminal U/
When D is both "0" and "1", it becomes "0", and when the input terminal U/D is "0", it counts down, and when it is "1", it counts up, so in this case Since the output terminal CA becomes "1" and the output of the inverter 78 becomes "0", the up-down counter 76 is controlled by the NAND circuit 8.
Count "+1" at the rising edge of output 2. Note that while "1" is output from the output terminal A of the shift register 71, the output of the O detection circuit 73 is inverted to "0", and the output of the inverter 77 becomes "1".
Therefore, the up-down counter 76 is no longer preset.

Thereafter, if the muting command signal becomes "1" two more times before the data "1" reaches the output end A of the shift register 71 and the output end H, the output will go up and down in the same manner as above. The counter 76 performs an up count, and when the count value reaches "3", the NOR circuit 80 outputs the switch 4.
Muting signals are generated for 0 and 41.

Further, if the data of "1" reaches the output terminal H of the shift register 71 and the input terminal 70 is "0" before the count value of the up-down counter 76 reaches "3", EX OR circuit 7
2 is "1" and the output terminal H of the shift register 71 is "1", so the output of the NAND circuit 74 is "0" and the up-down counter 76 is "1".
Count down. That is, the up-down counter 76 counts up by "1" when the muting command signal supplied to the input terminal 70 and the output terminal of the shift register 71 are "1" and "0", respectively, and counts up "1" and "0" and "1" respectively. ”, count down,
When it is "0", "0" or "1", "1", no counting operation is performed.

Therefore, when the muting command signal becomes "1" three times during 8H, a muting signal is generated from the NOR circuit 80, and a command is given to turn off the switches 40 and 41 provided at the output end. .

Although the above embodiment has been explained using a video tape recorder, the effects can be certainly obtained in other transmission systems other than PCM recording and reproducing devices. In this way, no abnormal signal is output from the output terminals 42 and 43.

As detailed above, according to the present invention, it is possible to provide a digital-to-analog conversion device which prevents the reproduction of abnormal signals from being derived when a plurality of video recorders are switched and reproduced, and which has a simple configuration and high reliability. be able to.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an overview of a PCM recording and reproducing device, and FIG. 2 is a block configuration diagram showing data switching means from a plurality of video tape recorders.
FIG. 3 is a diagram showing the relationship between different types of data when a signal that switches between two types of recording media is input during deinterleaving operation, and FIG. The block configuration diagram showing the device, Figure 5 is the same.
A block configuration diagram showing the details of the interleave circuit in the PCM recording and reproducing device, FIG. 6 is a block configuration diagram showing the specific configuration of the digital-to-analog converter, and FIG. 7 is a specific block diagram of the muting circuit of the digital-to-analog converter. FIG. 8 is a block diagram showing the configuration and a timing diagram for explaining the operation of the muting circuit. 12... Reproducing section, 24... Correction check code generation circuit, 32... Deinterleaving circuit, 3
3...Error detection circuit, 40, 41...Switch,
44... Muting circuit, 45... Correction data detection circuit.

Claims (1)

[Claims] 1 A plurality of sampled signal words and a correction word generated by performing an operation on the sampled signal words are generated from a signal obtained by interleaving processing, and the interleaved sampled signal words and correction words. an error detection circuit that receives an error detection word and generates instruction data indicating an error portion of the sampled signal word based on the interleaved signal and the error detection word; In the digital-to-analog conversion device, the digital-to-analog converter performs deinterleaving processing on the signal, performs data correction based on the instruction data, and converts the sampled signal word into an analog signal. Syndrome generated after interleaving processing is "0"
means for detecting a state in which the muting is not performed several times within several blocks; means for generating a muting signal by this means; and means for controlling the output of an analog signal to be non-deriving or deriving depending on the presence or absence of a muting signal from the muting generating means. A digital-to-analog conversion device characterized by comprising a muting circuit.