JP3653315B2 - Error correction method and error correction apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is suitable for application when, for example, digital data such as audio data reproduced from a recording medium or transmitted by a predetermined transmission system is error-corrected based on an error correction code added to the data. Error correction method And error correction device About.
[0002]
[Prior art]
Conventionally, when digital data such as digital audio data is recorded using an optical disk or a magneto-optical disk as a recording medium, an error correction code is added to the recorded data for recording. When reproducing the recording data of these recording media, an error in the reproduction data is corrected using an error correction code included in the reproduction data.
[0003]
7 and 8 are diagrams showing an example of a conventional error correction process. FIG. 7 shows an error correction code generation process, and FIG. 8 shows a decoding process using the error correction code. The process shown in FIGS. 7 and 8 is a process to which an error correction method called an ACIRC (Advanced Cross Interleave Reed-Solomon Code) method is applied. The ACIRC method is an error correction method improved from the CIRC method applied to an optical disk called a compact disk (CD). For example, audio data to a magneto-optical disk or an optical disk called a mini disk (MD) is used. This is a method applied to recording.
[0004]
First, FIG. 7 explains the error correction code generation process. For example, left and right (L, R) 2-channel digital audio data is input as 6 samples for each channel, that is, 16 bits × 2 × 6 for 192 bits ( 24 bytes) is input as one unit. In this input data string, if one sample is 2 words and 1 word is 16 bits, each word is divided into 2 symbols (1 symbol is 8 bits) of an upper symbol A and a lower symbol B. Converted.
[0005]
Then, the 24 symbol data is supplied to the even symbol delay circuit 11, and only the even-numbered symbol (that is, the lower symbol B) is delayed by one symbol. Then, the data of each symbol delayed by one symbol every other symbol is supplied to the scramble delay circuit 12. In the scramble delay circuit 12, the input data is scrambled to give different delay amounts, and delays successive symbols by four frames apart. However, there is a 20 frame interval between the 12th symbol data and the 13th symbol data. Note that D in the figure indicates 4 and indicates that scrambling over a maximum of 27 × 4 frames (that is, 108 frames) is performed (hereinafter, D in this specification has the same meaning).
[0006]
Then, the scrambled data of each symbol is supplied to the C2 parity generation circuit 13. The C2 parity generation circuit 13 encodes the error correction code C2, and generates a parity Q of the Reed-Solomon code with m = 8, n = 28, k = 24, and d = 5. Here, m is the number of bits of one symbol, n is the number of all symbols after parity generation, k is the number of symbols of input data, and d is the minimum distance of the code.
[0007]
Then, a total of 28 symbols of data of the 4-symbol parity Q generated by the C2 parity generation circuit 13 and the 24-symbol data supplied to the C2 parity generation circuit 13 are supplied to the interleaving delay circuit 14. . The interleaving delay circuit 14 delays consecutive symbols by separating them by four frames. However, the delay in the scramble delay circuit 12 is separated in the opposite direction (that is, in the scramble delay circuit 12, the first symbol data is delayed by a maximum of 108 frames, whereas the interleave delay circuit 12 14, the data of the last symbol is delayed by a maximum of 108 frames), and the data array scrambled for 108 frames by the scramble delay circuit 12 is almost restored. The parity Q of 4 symbols is arranged between the data of the 12th symbol and the data of the 13th symbol, and for the parity Q of 4 symbols, consecutive symbols are separated by 4 frames.
[0008]
Then, the data of each interleaved symbol is supplied to the C1 parity generation circuit 15. The C1 parity generation circuit 15 encodes the error correction code C1 and generates a parity P of a Reed-Solomon code with m = 8, n = 32, k = 28, and d = 5.
[0009]
Then, the 28-symbol data output from the interleaving delay circuit 14 and the 4-symbol parity P output from the C1 parity generation circuit 15 are supplied to the odd-symbol delay circuit 16, and only the odd-numbered symbols are delayed by one symbol. Thus, a data string to which an error correction code is added is obtained.
[0010]
Here, 32-symbol data output in parallel from the odd symbol delay circuit 16 is transmitted as data of one frame. The symbols of parity P and Q are inverted by the inverter gate 17 and output. The inversion processing by the inverter gate 17 is for making it possible to detect an error even when data and parity are all “0” data due to some malfunction or the like.
[0011]
For example, when this data is recorded on a recording medium such as a magneto-optical disk, 8-bit data of each symbol constituting one frame is referred to as EFM (Eight to Fourteen Modulation: 8 · 14 conversion). Modulation is performed to convert the bit data into 14-bit data, and the modulated data is recorded on the recording medium. Actually, the data of each frame is recorded with the synchronization data and the subcode added thereto.
[0012]
Next, when reproducing the data recorded on the recording medium in this way, the reproduced data is supplied to the EFM demodulating circuit, and the 14-bit data is converted into 8 bits. Is supplied to the decoding circuit shown in FIG. 8 in units of 32 symbols. This decoding circuit first supplies 32-symbol data to the even-numbered symbol delay circuit 21 and performs a process of delaying only even-numbered symbols by one symbol. Then, the data of 32 symbols delayed by one symbol every other symbol is supplied to the C1 error correction circuit 23. However, of the 32 symbol data, the parity Q of 4 symbols and the parity P of 4 symbols are respectively inverted by the inverter gate 22 and then supplied to the C1 error correction circuit 23.
[0013]
In the C1 error correction circuit 23, error correction processing is performed by calculation based on a location equation using the parity P. Here, correction is performed up to two symbol errors. However, in the case of two-symbol error correction and inability to correct, an error flag (hereinafter referred to as a pointer) is set for each symbol after decoding.
[0014]
Then, the decoded symbol data output from the C1 error correction circuit 23 is supplied to the deinterleave delay circuit 24, and the consecutive symbols are delayed by four frames. The direction in which the delay amount is changed here is a direction in which processing for returning the interleaving caused by the delay in the interleaving delay circuit 14 in the encoding circuit shown in FIG. 7 (ie, de-interleaving processing) is performed. is there.
[0015]
Then, the data of each symbol deinterleaved by the deinterleave delay circuit 24 is supplied to the C2 error correction circuit 26. In the C2 error correction circuit 26, error correction processing is performed by calculation based on a location equation using the parity Q. The correction processing here is performed in consideration of the state (number and position) of pointers assigned to each symbol.
[0016]
That is, the pointer data output from the C1 error correction circuit 23 is supplied to the C2 error correction circuit 26 via the delay circuit 25, and erasure correction processing using this pointer is performed. Here, as delay processing in the delay circuit 25, the 1-bit pointer data output from the C1 error correction circuit 23 is sequentially changed from 0 frame (that is, no delay state) to 108 frames at intervals of 4 frames in 28 steps. The data is delayed to 28-bit data, and the delayed pointer data is supplied to the C2 error correction circuit 26 in order. Therefore, when viewed from the C2 error correction circuit 26 side, the pointer generation state in the C1 error correction circuit 23 up to 108 frames before at intervals of 4 frames can be known. The correction processing in the C2 error correction circuit 26 taking into account the pointer information will be described later in the description based on the flowchart (FIG. 9).
[0017]
Then, the data of each symbol corrected and decoded by the C2 error correction circuit 26 is supplied to a descrambling delay circuit 27, and consecutive symbols are delayed by four frames. The direction in which the delay amount is changed here is the direction in which the process of returning the scramble caused by the delay in the scramble delay circuit 12 in the encoding circuit shown in FIG. 7 (ie, the descrambling process) is performed. is there.
[0018]
Then, the data of each symbol descrambled by the descrambling delay circuit 27 is supplied to the odd symbol delay circuit 28, and only the odd symbol is delayed by one symbol. The data of each symbol output from the odd symbol delay circuit 28 is output as decoded left and right two-channel digital audio data.
[0019]
Next, correction processing by the C1 error correction circuit 23 and the C2 error correction circuit 26 in this decoding circuit will be described based on the flowchart of FIG.
[0020]
First, correction processing is performed by the C1 error correction circuit 23 (step 101). Here, an operation is performed by a location equation using the parity P (step 102). As a result of this calculation, four states are determined: no error (step 103), 1 symbol error (step 104), 2 symbol error (step 105), and other states (step 106).
[0021]
As processing based on the determination of the four states, the pointer is cleared when there is no error (step 107), and when there is a one-symbol error, the corresponding one symbol is corrected (step 108), and then the pointer is cleared (step 108). Step 107). When there is a two-symbol error, the corresponding two symbols are corrected (step 109), and then the pointer is set (step 110). Furthermore, the pointer is set also in other states (step 110). Thus far, the correction process in the C1 error correction circuit 23 is completed (step 111).
[0022]
Next, correction processing is performed by the C2 error correction circuit 26 (step 121). Here, an operation is performed using a location equation using the parity Q (step 122). In the following description, i and j indicate error locations, respectively, and i <j. Np indicates the number of raised pointers, and Pi and Pj indicate pointers i and j, respectively.
[0023]
As a result of the calculation at step 122, determination is made of four states: no error (step 123), one symbol error (step 124), two symbol errors (step 125), and three symbols or more errors (step 126). I do.
[0024]
If it is determined in step 123 that there is no error, all pointers are cleared (step 131). If it is determined in step 124 that there is an error in one symbol, the error location i value of the symbol Si having the error is determined. When i exceeds 27 (step 132), i is equal to or less than 27 (step 133). The two states are determined.
[0025]
When it is determined in step 132 that i exceeds 27, when Np is 5 or more (step 134), Np is 4 (step 135), and Np is When the number is 0 to 3 (step 136), the three states are determined.
[0026]
When it is determined in step 134 that the number of pointers Np is 5 or more, the pointers are copied (step 157). If it is determined in step 135 that the number of pointers Np is 4, erasure correction of 4 symbols is performed (step 160). When it is determined in step 136 that the number of pointers Np is 0 to 3, all pointers are set (step 159).
[0027]
When it is determined in step 133 that i is 27 or less, one symbol correction is performed (step 137).
[0028]
When it is determined in step 125 that there is a two-symbol error, the value of the error location j of the symbol Sj out of the symbols Si and Sj with this error is determined. When j exceeds 27 (step 138), j is When the number is 27 or less (step 139), the two states are determined.
[0029]
When it is determined in step 138 that j exceeds 27, when Np is 0 to 2 (step 140) and Np is 5 or more (step 141) with respect to the number Np of the pointers set at that time, The four states are discriminated when Np is 3 (step 142) and when Np is 4 (step 143).
[0030]
When it is determined in step 140 that the number of pointers Np is 0 to 2, all pointers are set (step 159). If it is determined in step 141 that the number of pointers Np is 5 or more, the pointers are copied (step 157). If it is determined in step 142 that the number of pointers Np is 3, erasure correction of 3 symbols is performed (step 146). Further, when it is determined in step 143 that the number Np of pointers is 4, erasure correction of 4 symbols is performed (step 160).
[0031]
If it is determined in step 139 that the error location j is 27 or less, the number of pointers Np set at that time is Np is 5 or less (step 144), or Np exceeds 5 (step 145). The two states are determined.
[0032]
When it is determined in step 144 that the number of pointers Np is 5 or less, the values of the pointers Pi and Pj of the symbols Si and Sj with errors are determined. When Pi = Pj = 0 (step 147), Pi is determined. The three states are discriminated when = Pj = 1 (step 148) and Pi + Pj = 1 (step 149).
[0033]
When it is determined in step 147 that Pi = Pj = 0, with respect to the number of pointers Np set at that time, Np is 1 to 5 (step 150), and Np is 0 (step 151). The two states are discriminated.
[0034]
When it is determined in step 150 that Np is 1 to 5, when Np is 0 to 2 (step 140) and Np is 5 or more (step 141), the number Np of the pointers set at that time is determined. ), Np is 3 (step 142), and when Np is 4 (step 143), the four states are determined, and the above-described processing based on the determined state (all pointer sets in step 159, step 157 Pointer copy, 3-symbol erasure correction in step 146 or 4-symbol erasure correction in step 160) is performed. If Np is 0 in step 151, two symbol correction is performed (step 156).
[0035]
When it is determined in step 148 that Pi = Pj = 1, two symbol correction is performed (step 156).
[0036]
When it is determined in step 149 that Pi + Pj = 1, with respect to the number Np of the pointers set at that time, when Np is 1 (step 152), when Np is 2 or 3 (step 153), Np 4 is discriminated (step 154) and Np is 5 (step 155).
[0037]
When it is determined in step 152 that the number of pointers Np is 1, two symbol correction is performed (step 156). If it is determined in step 153 that the number of pointers Np is 2 or 3, all pointers are set (step 159). If it is determined in step 154 that the number of pointers Np is 4, 4-symbol erasure correction is performed (step 160). Further, when it is determined in step 155 that the number of pointers Np is 5, pointer copy is performed (step 157).
[0038]
By performing the processing so far, the C2 error correction is completed, and the C1 error correction and the C2 error correction are performed (step 161). After C1 error correction is performed in this way, error correction is performed efficiently by performing C2 error correction using the pointer information, and high error correction capability is obtained.
[0039]
[Problems to be solved by the invention]
By the way, in the case of the ACIRC method, since it is scrambled over a large number of frames, there may be a case where error correction cannot be performed finally in a long section extending over a plurality of frames depending on an error occurrence state.
[0040]
That is, for example, as shown in FIG. 10, when a burst error occurs in a certain section x (that is, a state in which errors continue in the section x), the C1 error correction circuit 23 performs data processing with a solid line arrow in FIG. As shown, the error processing is performed in the direction that coincides with the direction of reading data from the recording medium. Therefore, the range in which error correction by the C1 error correction circuit 23 is impossible is the range where the waveform shown as C1 in FIG. 10 rises, matches the burst error range x, and error correction is not possible even if there is a burst error. The range that is possible never expands.
[0041]
On the other hand, the C2 error correction circuit 26 processes the data interleaved over 108 frames, as shown in FIG. For this reason, the range in which the error correction cannot be performed by the C2 error correction circuit 26 is a range in which the waveform shown as C2 in FIG. 10 rises, and widens before and after the burst error range x, and is the maximum interleaved period. There is a possibility that error correction becomes impossible over 108 frames.
Further, when data after error correction is read, data that cannot be error-corrected is spread over 108 × 2 frames.
[0042]
In such a state, it becomes impossible to correct a much wider range than the damage of the original data. It is not preferable that the range in which error correction cannot be performed in this way is widened.
[0043]
In view of the above, the present invention provides an error correction method capable of improving error correction capability. And error correction device The purpose is to provide.
[0044]
[Means for Solving the Problems]
In order to solve this problem, according to the present invention, in the error correction method for data provided with correction codes generated in the order of the first check word and the second check word, In this example, error correction is performed on the second data series using two check words.
[0045]
According to this method, the final error correction direction can be the direction of the arrangement of the second data series.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
[0047]
In this example, the present invention is applied to a decoding circuit of an error correction method called an ACIRC method. As a conventional example, data encoded with an error correction code is decoded by the encoding circuit shown in FIG. Is.
[0048]
First, digital audio data reproduced from a recording medium (or transmitted through some transmission path) is supplied to a demodulation circuit for processing such as an EFM demodulation circuit to obtain 8-bit data. Data is supplied to the decoding circuit shown in FIG. 1 in units of 32 symbols. In this case, one sample of digital audio data is composed of 16 bits, and this one sample of 16 bits of data is composed of upper 8 bits of symbol A and lower 8 bits of symbol B, and 24 of 32 symbols. The symbols are audio data, and the remaining 8 symbols are the parity P (4 symbols) generated by the C1 parity generation circuit and the parity Q (4 symbols) generated by the C2 parity component circuit.
[0049]
The configuration of the decoding circuit of FIG. 1 will be described. First, 32 symbols of data are supplied to the even-numbered symbol delay circuit 31, and only even-numbered symbols are delayed by one symbol. Of the 32 symbol data delayed by one symbol every other symbol, the parity Q of 4 symbols and the parity P of 4 symbols are inverted by the inverter gate 32, respectively.
[0050]
The output of the even symbol delay circuit 31 (data symbol) and the output of the inverter gate 32 (parity symbol) are supplied to the descrambling delay circuit 33. However, the P parity is not supplied to the delay circuit 33. The delay circuit 33 delays consecutive symbols by separating them by 4 frames. That is, by changing the delay amount by 4 frames for each adjacent symbol (D in the figure is 4), a state from a minimum no delay state to a maximum 27 × D frame = 108 frame delays is set. De-scramble processing is performed. In this processing, the maximum delay amount is set for the first symbol data, and the delay amount is changed so that the last symbol data has no delay.
[0051]
Then, the data descrambled by the delay circuit 33 and the Q parity symbol are supplied to the C2 error correction circuit 34. In the C2 error correction circuit 34, error correction processing is performed by calculation based on a location equation using the parity Q. As the error correction processing here, correction up to two symbol errors is performed. When error correction of 2 symbols is performed and when there is an error exceeding 2 symbols and correction cannot be performed, a pointer is set to the corresponding symbol.
[0052]
Then, the data output from the C2 error correction circuit 34 is supplied to the deinterleave delay circuit 35. In this case, in this example, the 4-symbol parity Q supplied to the C2 error correction circuit 34 is also output as it is and supplied to the deinterleaving delay circuit 35. The 4-symbol parity P inverted by the inverter gate 32 is also supplied to the deinterleave delay circuit 35.
[0053]
The de-interleaving delay circuit 35 performs de-interleaving processing that gives different delay amounts to the 24 symbols of the 32 symbols supplied and the parity Q of 4 symbols. That is, de-interleave processing is performed by changing the delay amount by 4 frames for each adjacent symbol and setting a state from a minimum no delay state to a maximum 27 × D frame = 108 frame delay state. . The processing here is opposite to the direction in which the delay amount is changed by the descrambling delay circuit 35, that is, the first symbol data is set to have no delay, and the maximum delay amount is set to the last symbol data. To do. Further, the descrambling delay circuit 35 delays 108 frames each for the parity P of 4 symbols.
[0054]
Then, the data of each symbol deinterleaved by the deinterleaving delay circuit 35 is supplied to the C1 error correction circuit 37. In the C1 error correction circuit 37, error correction processing is performed by calculation based on a location equation using the parity P. The correction processing here is performed in consideration of the state (number and position) of pointers assigned to each symbol.
[0055]
That is, the pointer data output from the C2 error correction circuit 34 is supplied to the C1 error correction circuit 37 via the delay circuit 36, and correction processing using this pointer is performed. Here, as delay processing in the delay circuit 36, the 1-bit pointer data output from the C2 error correction circuit 34 is sequentially changed from 0 frame (that is, no delay state) to 108 frames at intervals of 4 frames in 28 steps. The data is delayed to 28-bit data, and the delayed pointer data is supplied to the C1 error correction circuit 37 in order. Accordingly, when viewed from the C1 error correction circuit 37 side, the pointer generation state in the C2 error correction circuit 34 up to 108 frames before at an interval of 4 frames can be known. The correction processing in the C1 error correction circuit 37 in consideration of the pointer information will be described later in the description based on the flowchart (FIG. 2).
[0056]
Then, the data of each symbol corrected and decoded by the C1 error correction circuit 37 is supplied to the odd symbol delay circuit 38, and only the odd symbol is delayed by one symbol. The data of each symbol output by the odd symbol delay circuit 38 is output as decoded left and right channel digital audio data.
[0057]
Next, correction processing in the C2 error correction circuit 34 and the C1 error correction circuit 37 in the decoding circuit of this example will be described based on the flowchart of FIG.
[0058]
First, correction processing is performed by the C2 error correction circuit 34 (step 201). Here, an operation is performed by a location equation using the parity Q (step 202). As a result of this calculation, four states are determined: no error (step 203), 1 symbol error (step 204), 2 symbol error (step 205), and other states (step 206).
[0059]
As processing based on the discrimination of the four states, the pointer is cleared when there is no error (step 207), and when there is one symbol error, the corresponding one symbol is corrected (step 208), and then the pointer is cleared (step 207). Step 207). When there is a two-symbol error, the corresponding two symbols are corrected (step 209), and then a pointer is set (step 210). Further, the pointer is set also in other states (step 210). Up to this point, the correction process in the C2 error correction circuit 34 is completed (step 211).
[0060]
Next, correction processing is performed by the C1 error correction circuit 37 (step 221). Here, an operation is performed using a location equation using the parity P (step 222). In the following description, i and j indicate error locations, respectively, and i <j. Np indicates the number of raised pointers, and Pi and Pj indicate pointers i and j, respectively.
[0061]
Then, as a result of the calculation at step 222, discrimination of four states of no error (step 223), 1 symbol error (step 224), 2 symbol error (step 225), 3 symbols or more error (step 226). I do.
[0062]
If it is determined in step 223 that there is no error, all pointers are cleared (step 231). When it is determined in step 224 that there is a one symbol error, the value of the error location i of the symbol Si having the error is determined. When i exceeds 31 (step 232), i is equal to or less than 31 (step 233). The two states are determined.
[0063]
When it is determined in step 232 that i exceeds 31, when the number Np of the pointers set at that time is Np is 4 or more (step 234), or when Np is 0 to 3 (step 235). Two states are discriminated.
[0064]
When it is determined in step 234 that the number of pointers Np is 4 or more, the pointer is copied (step 257). When it is determined in step 235 that the number of pointers Np is 0 to 3, all pointers are set (step 258).
[0065]
When it is determined in step 233 that i is 31 or less, one symbol correction is performed (step 236).
[0066]
When it is determined in step 225 that there is a two-symbol error, the error location j of the symbol Sj out of the symbols Si and Sj having the error is determined. When j exceeds 31 (step 237), j When the number is 31 or less (step 238), the two states are discriminated.
[0067]
When it is determined in step 237 that j exceeds 31, when the number Np of the pointers set at that time is Np from 0 to 2 (step 239), when Np is 3 or more (step 240). Two states are discriminated.
[0068]
When it is determined in step 239 that the number of pointers Np is 0 to 2, all pointers are set (step 258). If it is determined in step 240 that the number of pointers Np is 3 or more, the pointer is copied (step 257).
[0069]
If it is determined in step 238 that the error location j is 31 or less, the number Np of pointers set at that time is Np is 5 or less (step 241), or Np exceeds 5 (step 242). The two states are determined.
[0070]
When it is determined in step 241 that the number of pointers Np is 5 or less, the values of error locations i and j of symbols Si and Sj are determined. When i exceeds 27 (step 243), i is 27 or less. The three states are discriminated when j exceeds 27 (step 244) and when j is 27 or less (step 245). When it is determined in step 243 that i exceeds 27, the number of pointers Np set at that time is 2 when Np is 1 to 5 (step 251) and when Np is 0 (step 252). The state is determined, and when Np is 1 to 5 in step 251, the process proceeds to the determination processing in steps 239 and 240 already described. When Np is 0 in step 252, two symbol correction is performed (step 156).
[0071]
When it is determined in step 244 that i is 27 or less and j exceeds 27, two states are determined when the pointer Pi is 0 (step 246) and when the pointer Pi is 1 (step 247). When it is determined in step 246 that the pointer Pi is 0, the process proceeds to the determination processing in steps 251 and 252 already described. If it is determined in step 247 that the pointer Pi is 1, two symbol correction is performed (step 256).
[0072]
When it is determined in step 245 that j is 27 or less, the values of the pointers Pi and Pj of the erroneous symbols Si and Sj are determined. When Pi = Pj = 0 (step 246), Pi = Pj = The three states are discriminated when 1 (step 249) and when Pi + Pj = 1 (step 250).
[0073]
When it is determined in step 248 that Pi = Pj = 0, the process proceeds to the determination processing in steps 251 and 252 already described. If it is determined in step 249 that Pi = Pj = 1, two-symbol correction is performed (step 256). Further, when it is determined in step 250 that Pi + Pj = 1, for the number Np of pointers set at that time, when Np is 1 (step 253), when Np is 2 or 3 (step 254), Np 3 is discriminated when 4 is 5 or 5 (step 255), 2 symbols are corrected when Np is 1 at step 253 (step 256), and all pointers are set when Np is 2 or 3 at step 254 (Step 258). When Np is 4 or 5 in step 255, all pointers are copied (step 257).
[0074]
By performing the processing so far, C1 error correction is completed, and both error corrections are performed in the order of C2 error correction and C1 error correction (step 259). After C2 error correction is performed in this way, efficient error correction using two types of error correction codes can be performed as in the conventional case by performing C1 error correction using the pointer information. In this example, the C2 error correction is performed first and then the C1 error correction is performed last. Therefore, when a burst error that cannot be corrected occurs, the spread of the influence can be suppressed.
[0075]
That is, in the case of this example, the data corrected by the C1 error correction circuit 37 is output after being delayed only for odd symbols, and finally after error correction is performed, This is a case where there is no need for processing such as descrambling that significantly changes the symbol arrangement, and the data output direction matches the error correction direction, resulting in an uncorrectable burst error. However, the range in which errors cannot be corrected does not spread.
[0076]
In the case of the circuit of this example, the capacity of the storage element used for delaying the symbol data is almost the same as that of the conventional circuit, and the circuit scale does not increase due to the configuration of this example.
[0077]
FIG. 3 is a diagram showing an occurrence state of an error flag (a flag indicating that correction is not possible) when there is a burst error in a predetermined section in the reproduction data that has been encoded according to the ACIRC system. Assume that A has a burst error in section a. At this time, in the processing by the decoding circuit of the first embodiment (that is, the circuit that performs C1 correction after C2 correction), as shown in FIG. Although an error flag is generated at the timing, the length of the period during which the error flag is generated can be suppressed to be substantially the same as the burst error section a. On the other hand, in the processing by the conventional decoding circuit that performs C2 correction after C1 correction, as shown in C of FIG. 3, the error flag is continuously displayed for a very long period (for example, about 108 × 2 = 216 frames). Will occur.
[0078]
Next, a second embodiment of the present invention will be described with reference to FIGS.
[0079]
This example is also applied to a decoding circuit of an error correction method called an ACIRC method. As a conventional example, data encoded with an error correction code is decoded by the encoding circuit shown in FIG. Therefore, in this example, error correction is performed in the order of C1 error correction and C2 error correction as in the conventional case, and then C1 error correction is performed again.
[0080]
First, digital audio data reproduced from a recording medium (or transmitted through some transmission path) is supplied to a demodulation circuit for processing such as an EFM demodulation circuit to obtain 8-bit data. Data is supplied to the decoding circuit shown in FIG. 4 in units of 32 symbols. In this case, one sample of digital audio data is composed of 16 bits, and this one sample of 16 bits of data is composed of upper 8 bits of symbol A and lower 8 bits of symbol B, and 24 of 32 symbols. The symbols are audio data, and the remaining 8 symbols are the parity P (4 symbols) generated by the C1 parity generation circuit and the parity Q (4 symbols) generated by the C2 parity component circuit.
[0081]
The configuration of the decoding circuit of FIG. 4 will be described. First, 32 symbols of data are supplied to the even-numbered symbol delay circuit 41, and processing for delaying only even-numbered symbols by one symbol is performed. Of the 32 symbols of data delayed by one symbol every other symbol, the parity Q of 4 symbols and the parity P of 4 symbols are inverted by the inverter gate 42, respectively.
[0082]
Then, the 24 data output from the even symbol delay circuit 41 and the 4-symbol parity Q and 4-symbol parity P output from the inverter gate 42 are supplied to the first C1 error correction circuit 43.
[0083]
In the first C1 error correction circuit 43, error correction processing is performed by calculation based on a location equation using the parity P. Here, correction is performed up to two symbol errors. However, in the case of two-symbol error correction and inability to correct, an error flag (hereinafter referred to as a pointer) is set for each symbol after decoding.
[0084]
Then, the decoded symbol data output from the first C1 error correction circuit 43 is supplied to the deinterleaving delay circuit 44, and successive symbols are delayed by four frames. Here, the direction in which the delay amount is changed is a direction in which processing for returning the interleaving processing in the encoding circuit (ie, de-interleaving processing) is performed.
[0085]
Then, the data of each symbol deinterleaved by the deinterleave delay circuit 44 is supplied to the C2 error correction circuit 45. In the C2 error correction circuit 45, error correction processing is performed by calculation based on a location equation using the parity Q. The correction processing here is performed in consideration of the state (number and position) of pointers assigned to each symbol.
[0086]
That is, the pointer data output from the first C1 error correction circuit 43 is supplied to the C2 error correction circuit 45 via the delay circuit 46, and erasure correction processing using this pointer is performed. Here, as delay processing in the delay circuit 46, the data of the 1-bit pointer output from the first C1 error correction circuit 43 is changed from 0 frame (that is, no delay state) to 108 frames at intervals of 4 frames. The data is sequentially delayed to 28-bit data, and the delayed pointer data is supplied to the C2 error correction circuit 45 in sequence. Accordingly, when viewed from the C2 error correction circuit 45 side, the pointer generation state in the first C1 error correction circuit 43 up to 108 frames before at an interval of 4 frames can be known.
[0087]
Then, the data of each symbol corrected and decoded by the C2 error correction circuit 45 is supplied to the descrambling delay circuit 47, and the consecutive symbols are delayed by 4 frames. The direction in which the delay amount is changed here is a direction in which processing for returning the scramble processing in the encoding circuit (ie, descramble processing) is performed. In this example, the 4-symbol parity Q supplied to the C2 error correction circuit 45 and the 4-symbol parity P supplied to the first C1 error correction circuit 43 are also transmitted to the descrambling delay circuit 47. It is supplied and delayed. However, with respect to the parity Q, processing is performed between the data of the 12th symbol and the data of the 13th symbol, and delayed by 4 frames continuously from the data symbol. Processing for delaying all four symbols by 108 frames is performed.
[0088]
Then, the data of each symbol descrambled by the descrambling delay circuit 47 is supplied to the second C1 error correction circuit 48. In the second C1 error correction circuit 48, error correction processing is performed by calculation based on a location equation using the parity P. The correction processing here is performed in consideration of the state (number and position) of pointers assigned to each symbol.
[0089]
That is, the pointer data output from the first C1 error correction circuit 43 is supplied to the second C1 error correction circuit 48 via the delay circuit 49, and the pointer data output from the C2 error correction circuit 45 is The data is supplied to the C2 error correction circuit 48 via the delay circuit 50, and erasure correction processing using each pointer is performed. Here, as delay processing of the pointer by C1 correction in the delay circuit 49, 108 frame periods corresponding to the delay amount of the symbol data of the signal from the first C1 error correction circuit 43 to the second C1 error correction circuit 48 In the delay circuit, the 1-bit pointer data output from the first C1 error correction circuit 43 is supplied after being delayed by 108 frames. As a pointer delay process by C2 correction in the delay circuit 25, 1-bit pointer data output from the C2 error correction circuit 45 is changed from 0 frame (that is, no delay state) to 108 frames at intervals of 4 frames. The data is sequentially delayed in 28 steps to be 28-bit data, and the delayed pointer data is supplied to the C1 error correction circuit 48 in sequence. The correction processing in the second C1 error correction circuit 48 taking into account the pointer information will be described later in the description based on the flowchart (FIG. 5).
[0090]
Then, the data of each symbol corrected and decoded by the second C1 error correction circuit 48 is supplied to the odd symbol delay circuit 51, and only the odd symbol is delayed by one symbol. The data of each symbol output from the odd symbol delay circuit 51 is output as decoded left and right channel digital audio data.
[0091]
Next, error correction processing in the second C1 error correction circuit 48 in the decoding circuit of this example will be described based on the flowchart of FIG. The correction processing in the first C1 error correction circuit 43 and the correction processing in the C2 error correction circuit 45 of this example are the same as the processing shown in the flowchart of FIG. 9 in the conventional example. Then, after step 161 of the flowchart of FIG. 9, the process of step 301 of the flowchart of FIG. 5 is performed. That is, after the C1 error correction and the C2 error correction shown in the flowchart of FIG. 9 are performed, the process proceeds to step 301 in FIG. 5 and the error correction processing in the second error correction circuit 48 is started. At this time, first, an operation is performed by a location equation using the parity P (step 302). In the following description, i and j indicate error locations, respectively, and i <j. Np indicates the number of raised pointers, and Pi and Pj indicate pointers i and j, respectively.
[0092]
As a result of the calculation in step 302, four states are discriminated: no error (step 303), 1 symbol error (step 304), 2 symbol error (step 305), and 3 symbols or more error (step 306). I do.
[0093]
If it is determined in step 303 that there is no error, all pointers are cleared (step 307). Further, when it is determined in step 304 that there is a one symbol error, the value of error location i of the symbol Si having the error is determined. When i exceeds 31 (step 308), i is equal to or less than 31 (step 309). The two states are determined.
[0094]
When it is determined in step 308 that i exceeds 31, when the number of pointers Np set at that time is Np is 5 or more (step 310), Np is 4 (step 311), and Np is When 0-3 (step 312), the three states are determined.
[0095]
When it is determined in step 310 that the number of pointers Np is 5 or more, the pointers are copied (step 332). When it is determined in step 311 that the number of pointers Np is 4, four symbols are erased (step 335). Further, when it is determined in step 312 that the number of pointers Np is 0 to 3, all pointers are set (step 335).
[0096]
When it is determined in step 309 that i is 31 or less, one symbol correction is performed (step 313).
[0097]
When it is determined in step 305 that there is a two-symbol error, the error location j of the symbol Sj out of the symbols Si and Sj having the error is determined. When j exceeds 31 (step 314), j is When the number is 31 or less (step 315), the two states are determined.
[0098]
When it is determined in step 314 that j exceeds 31, when Np is 0 to 2 (step 316) and Np is 5 or more (step 317), the number Np of pointers set at that time is determined. The four states are discriminated when Np is 3 (step 318) and when Np is 4 (step 319).
[0099]
When it is determined in step 316 that the number of pointers Np is 0 to 2, all pointers are set (step 334). If it is determined in step 317 that the number of pointers Np is 5 or more, the pointer is copied (step 332). If it is determined in step 318 that the number of pointers Np is 3, erasure correction of 3 symbols is performed (step 332). Further, when it is determined in step 319 that the number of pointers Np is 4, four symbol erasure correction is performed (step 335).
[0100]
If it is determined in step 315 that the error location j is 31 or less, the number Np of the pointers set at that time is Np is 5 or less (step 320), and Np is more than 5 (step 321). The two states are determined.
[0101]
When it is determined in step 320 that the number of pointers Np is 5 or less, the values of pointers Pi and Pj of the erroneous symbols Si and Sj are determined. When Pi = Pj = 0 (step 323), Pi is determined. The three states are discriminated when = Pj = 1 (step 324) and Pi + Pj = 1 (step 325).
[0102]
If it is determined in step 323 that Pi = Pj = 0, the number Np of the pointers set at that time is 1 to 5 (step 326), and Np is 0 (step 327). The two states are discriminated.
[0103]
When it is determined in step 326 that Np is 1 to 5, when Np is 0 to 2 (step 316) and Np is 5 or more (step 317) with respect to the number Np of pointers set at that time. ), When Np is 3 (step 318), when Np is 4 (step 319), the four states are determined, and the above-described processing based on the determined state (all pointer sets in step 334, step 332) Pointer copy, 3-symbol erasure correction in step 322 or 4-symbol erasure correction in step 335) is performed. If Np is 0 in step 327, two symbol correction is performed (step 333).
[0104]
When it is determined in step 324 that Pi = Pj = 1, two symbol correction is performed (step 333).
[0105]
When it is determined in step 325 that Pi + Pj = 1, regarding the number of pointers Np set at that time, when Np is 1 (step 328), when Np is 2 or 3 (step 329), Np 4 is discriminated (step 330), and Np is 5 (step 331).
[0106]
When it is determined in step 328 that the number of pointers Np is 1, two symbol correction is performed (step 333). If it is determined in step 329 that the number of pointers Np is 2 or 3, all pointers are set (step 334). If it is determined in step 330 that the number of pointers Np is 4, 4-symbol erasure correction is performed (step 335). Further, when it is determined in step 331 that the number of pointers Np is 5, pointer copy is performed (step 332).
[0107]
By performing the processing so far, the error correction is performed in the order of the first C1 error correction, the C2 error correction, and the second C1 error correction (step 336). After the C1 error correction and the C2 error correction are performed in this way, the C1 error correction is performed again, so that the finally output data becomes the C1 error corrected data and is finally error corrected. Even when a burst error that cannot be corrected by an error occurs when the direction of the data matches the direction in which the data is output, the error uncorrectable range does not expand, and the error range of the data due to the burst error is appropriately reflected. Error correction results can be obtained.
[0108]
In this example, the erasure correction based on the results of the first C1 error correction and the C2 error correction can be performed by the second C1 error correction, and the error correction capability is improved as compared with the case of the first embodiment. Can do.
[0109]
In the case of the second embodiment, two sets of C1 error correction circuits are required as the error correction circuit, but the capacity of the storage element used for delaying the symbol data is the same as that of the conventional circuit. It is almost the same.
[0110]
In the second embodiment, erasure correction is performed by the second C1 error correction. However, the second C1 error correction circuit 48 may perform error correction without erasure correction. The flowchart in FIG. 6 shows an example of this case, and only the processing in the second C1 error correction circuit 48 is shown as in the flowchart in FIG.
[0111]
An example in which the erasure correction is not performed will be described based on the flowchart of FIG. 6. After the C1 error correction and the C2 error correction shown in the flowchart of FIG. 9 are performed, the process proceeds to step 401 in FIG. Error correction processing in the correction circuit 48 is started. At this time, first, an operation is performed by a location equation using the parity P (step 402).
[0112]
Then, as a result of the calculation in step 402, discrimination of four states, that is, no error (step 403), 1 symbol error (step 404), 2 symbol error (step 405), and 3 or more errors (step 406). I do.
[0113]
If it is determined in step 403 that there is no error, all pointers are cleared (step 407). Further, when it is determined in step 404 that there is an error of one symbol, the value of error location i of the symbol Si having this error is determined. When i exceeds 31 (step 408), i is not more than 31 (step 409). The two states are determined.
[0114]
When it is determined in step 408 that i exceeds 31, when Np is 4 or more (step 410) and Np is 0 to 3 (step 411), the number of pointers Np set at that time is np. Two states are discriminated.
[0115]
When it is determined in step 410 that the number of pointers Np is 4 or more, the pointers are copied (step 427). When it is determined in step 411 that the number of pointers Np is 0 to 3, all pointers are set (step 429).
[0116]
When it is determined in step 409 that i is 31 or less, one symbol correction is performed (step 412).
[0117]
When it is determined in step 405 that there is a two-symbol error, the error location j of the symbol Sj out of the erroneous symbols Si and Sj is determined. When j exceeds 31 (step 413), When the number is 31 or less (step 414), the two states are determined.
[0118]
When it is determined in step 413 that j exceeds 31, when the number Np of the pointers set at that time is Np from 0 to 2 (step 415), Np is 3 or more (step 416). Two states are discriminated.
[0119]
When it is determined in step 415 that the number of pointers Np is 0 to 2, all pointers are set (step 429). When the number of pointers Np is determined to be 3 or more at step 416, the pointer is copied (step 427).
[0120]
If it is determined in step 414 that the error location j is 31 or less, the number Np of the pointers set at that time is Np is 5 or less (step 417), or Np exceeds 5 (step 418). The two states are determined.
[0121]
When it is determined in step 417 that the number of pointers Np is 5 or less, the values of pointers Pi and Pj of symbols Si and Sj with errors are determined. When Pi = Pj = 0 (step 419), Pi is determined. The three states are discriminated when = Pj = 1 (step 420) and Pi + Pj = 1 (step 421).
[0122]
When it is determined in step 419 that Pi = Pj = 0, the number of pointers Np set at that time is 1 to 5 (step 422), and Np is 0 (step 423). The two states are discriminated.
[0123]
When it is determined in step 422 that Np is 1 to 5, when Np is 0 to 2 (step 415) and Np is 3 or more (step 416), the number Np of the pointers set at that time is determined. ), And the above-described processing based on the determined state (set all pointers in step 429 or pointer copy in step 427) is performed. If Np is 0 in step 423, two symbol correction is performed (step 428).
[0124]
When it is determined in step 420 that Pi = Pj = 1, two symbol correction is performed (step 428).
[0125]
When it is determined in step 421 that Pi + Pj = 1, with respect to the number of pointers Np set at that time, when Np is 1 (step 424), when Np is 2 or 3 (step 425), Np When 4 is 5 or 5 (step 426), the four states are discriminated.
[0126]
If it is determined in step 424 that the number of pointers Np is 1, two symbol correction is performed (step 428). If it is determined in step 425 that the number of pointers Np is 2 or 3, all pointers are set (step 429). If it is determined in step 426 that the number of pointers Np is 4 or 5, pointer copy is performed (step 427).
[0127]
By performing the processing so far, the error correction is performed in the order of the first C1 error correction, the C2 error correction, and the second C1 error correction (step 430). Thus, even when erasure correction is not performed in the second C1 error correction, the error correction capability can be improved as compared with the case where C1 error correction and C2 error correction are performed once.
[0128]
In each of the above-described embodiments, the example is applied to error correction of digital audio data encoded by the ACIRC method. However, other methods of error correction that perform error correction based on two series of error correction codes. Of course, the present invention can also be applied. The present invention can also be applied to error correction of various digital data other than digital audio data.
[0129]
【The invention's effect】
Correction codes are generated and assigned in the order of the first check word (parity Q for C2 error correction in the embodiment described above) and the second check word (parity P for C1 error correction in the embodiment described above). In the present invention, when the error correction is performed on the data that has been originally set to correct the error in the order of the second check word and the first check word, in the present invention, the final error correction is performed by the second check word. Since the error correction based on the second check word based on the arrangement of the data series is performed, there is an effect that the error correction can be performed with the influence of the burst error minimized depending on the data arrangement. For example, in the case of an error correction method called the ACIRC method, the final error correction direction is the same as the data reading direction, and an error correction result appropriately reflecting the error range of data due to a burst error is obtained. Has the effect.
[0130]
In this case, after performing the error correction process based on the first check word and then performing the error correction process based on the second check word, a simple configuration that only changes the order in which the correction process is performed as compared with the prior art. Thus, good error correction becomes possible.
[0131]
In addition, after processing in the order of error correction processing based on the second check word and error correction processing based on the first check word, error correction processing based on the second check word is further performed, so that error The correction ability can be effectively increased.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a decoding circuit to which a correction method according to a first embodiment of the present invention is applied.
FIG. 2 is a flowchart showing a correction process according to the first embodiment.
FIG. 3 is a waveform diagram comparing the state of error flag generation according to the first embodiment with that of the prior art.
FIG. 4 is a configuration diagram of a decoding circuit to which a correction method according to a second embodiment of the present invention is applied.
FIG. 5 is a flowchart showing correction processing (when erasure correction is performed) according to the second embodiment;
FIG. 6 is a flowchart showing correction processing (in the case of no erasure correction) according to the second embodiment.
FIG. 7 is a configuration diagram illustrating an example of an encoding process of an error correction code.
FIG. 8 is a configuration diagram of a conventional decoding circuit that decodes data encoded with the configuration of FIG. 7;
FIG. 9 is a flowchart showing correction processing by the circuit of the example of FIG.
FIG. 10 is a timing chart showing an example of a conventional burst error occurrence state.
[Explanation of symbols]
31 Even symbol delay circuit
32 Inverter gate
33 Descramble delay circuit
34 C2 error correction circuit
35 De-interleaving delay circuit
36 Delay circuit for pointer
37 C1 error correction circuit
38 Odd symbol delay circuit
41 Even symbol delay circuit
42 Inverter gate
43 First C1 error correction circuit
44 Delay circuit for descrambling
45 C2 error correction circuit
46 Delay circuit for pointer
47 Delay circuit for de-interleaving
48 Second C1 error correction circuit
49, 50 Pointer delay circuit
51 Odd symbol delay circuit

Claims (6)

The input data string is divided into symbols each having a predetermined number of words, and a first check word is generated for the first data series arranged in a direction inclined with respect to the reading direction from the recording medium for each symbol. Then, a second check word for the second data series arranged in the same direction as the reading direction from the recording medium is generated with respect to each symbol and the first check word, and each symbol and the first check word are generated. An error correction method for decoding an input data string composed of the check word and the second check word is as follows:
A first de-scramble processing step of applying a different time delay to each of the words and the first check word, and performing a descrambling process in a direction inclined with respect to a reading direction of data from the recording medium; ,
A first calculation step of calculating a location equation using the first check word for each of the words subjected to the first descrambling process;
A first determination step of determining the presence or absence of an error and the number of error symbols according to the calculation result calculated in the first calculation step;
A first control step of performing error correction and / or pointer setting according to the determination result of the first determination step;
After the first control step, the first check word, each word, and the second check word are time-delayed and descrambled in the same direction as the data reading direction from the recording medium. A second de-scramble processing step,
A second calculation step of calculating a location equation using the second check word for each word subjected to the second descrambling process;
A second determination step of determining the number of error symbols and the error location according to the calculation result calculated in the second calculation step;
An error correction method comprising: a second control step that performs error correction or pointer setting according to the determination result of the second determination step. The input data string is divided into symbols each having a predetermined number of words, and a first check word is generated for the first data series arranged in a direction inclined with respect to the reading direction from the recording medium for each symbol. Then, a second check word for the second data series arranged in the same direction as the reading direction from the recording medium is generated with respect to each symbol and the first check word, and each symbol and the first check word are generated. An error correction method for decoding an input data string composed of the check word and the second check word is as follows:
A first calculation step of calculating a location equation using the second check word for each of the words and the first check word;
A first determination step of determining the presence or absence of an error and the number of error symbols according to the calculation result calculated in the first calculation step;
A first control step of performing error correction and / or pointer setting according to the determination result of the first determination step;
Each word after the first control step, the first check word, and the second check word are time-delayed and descrambled in a direction inclined with respect to the data reading direction from the recording medium. A first de-scramble processing step,
A second calculation step of calculating a location equation using the first check word for each of the words subjected to the first descrambling process;
A second determination step of determining the presence or absence of an error and the number of error symbols according to the calculation result calculated in the second calculation step;
A second control step of performing error correction and / or pointer setting according to the determination result of the second determination step;
A second time delay is applied to each of the first check word and each word after the second control step, and a descrambling process is performed in the same direction as the data reading direction from the recording medium. A descrambling process;
A third calculation step of calculating a location equation using the second check word for each of the words subjected to the second descrambling process;
A third determination step of determining the number of error symbols and the error location according to the calculation result calculated in the third calculation step;
An error correction method comprising: a third control step of performing error correction or pointer setting according to the determination result of the third determination step. 3. The error correction method according to claim 2, wherein the third control step further performs erasure correction. The input data string is divided into symbols each having a predetermined number of words, and a first check word is generated for the first data series arranged in a direction inclined with respect to the reading direction from the recording medium for each symbol. Then, a second check word for the second data series arranged in the same direction as the reading direction from the recording medium is generated with respect to each symbol and the first check word, and each symbol and the first check word are generated. An error correction device that decodes an input data string composed of the check word and the second check word,
First de-scramble processing means for applying a different time delay to each of the words and the first check word, and performing a descrambling process in a direction inclined with respect to a reading direction of data from the recording medium; ,
First computing means for computing a location equation using the first check word for each of the words subjected to the first descrambling process;
First determination means for determining the presence or absence of an error and the number of error symbols according to the calculation result calculated by the first calculation means;
First control means for performing error correction and / or pointer setting according to the determination result of the first determination means;
A time delay is applied to each of the first check word, each word, and each second check word output from the first control means, and the same direction as the data reading direction from the recording medium. A second descrambling means for applying a descrambling process to
Second computing means for computing a location equation using the second check word for each word subjected to the second descrambling process;
Second discriminating means for discriminating the number of error symbols and the error location according to the computation result computed by the second computing means;
An error correction apparatus comprising: a second control unit that performs error correction or pointer setting according to a determination result of the second determination unit. The input data string is divided into symbols each having a predetermined number of words, and a first check word is generated for the first data series arranged in a direction inclined with respect to the reading direction from the recording medium for each symbol. Then, a second check word for the second data series arranged in the same direction as the reading direction from the recording medium is generated with respect to each symbol and the first check word, and each symbol and the first check word are generated. An error correction device that decodes an input data string composed of the check word and the second check word,
First computing means for computing a location equation for each word and the first check word using the second check word;
First determination means for determining the presence or absence of an error and the number of error symbols according to the calculation result calculated by the first calculation means;
First control means for performing error correction and / or pointer setting according to the determination result of the first determination means;
A direction inclined with respect to the reading direction of data from the recording medium by applying a time delay to each of the first check word and the first check word output from the first control means and the second check word. First descramble processing means for performing descrambling processing on
Second computing means for computing a location equation using the first check word for each of the words subjected to the first descrambling process;
Second discriminating means for discriminating the presence or absence of an error and the number of error symbols according to the computation result computed by the second computation means;
Second control means for performing error correction and / or pointer setting according to the determination result of the second determination means;
The first check word output from the second control means and each word are subjected to different time delays, and descramble processing is performed in the same direction with respect to the reading direction of data from the recording medium. Two descrambling means;
Third computing means for computing a location equation using the second check word for each word subjected to the second descrambling process;
Third discriminating means for discriminating the number of error symbols and the error location according to the computation result computed by the third computing means;
An error correction apparatus comprising: third control means for performing error correction or pointer setting according to the determination result of the third determination means. 6. The error correction apparatus according to claim 5, wherein the third control means further performs erasure correction.

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