KR930010355B1 - Data error correcting & decoding method and apparatus - Google Patents

Abstract

The data error correcting decoding method in a data error correcting apparatus having data word columns, first check word columns and second check word columns for decoding data columns interleaved in respective words by Reed-Solomon code includes the steps of: receiving the data columns in parallel every time; generating the data word columns and first check word columns every time by a first syndrome; rearranging the data word columns and first check word columns by different delay times; generating the data word columns by a second syndrome every time; restoring the data word columns and first and second check word columns; generating data word columns and first check word columns every time by a third syndrome; rearranging the data words columns and first check word columns by different delay times; repeating the generating step of the data word columns by a fourth syndrome; and supplying the data word columns to plural parallel channels.

Description

Data error correction decoding method and apparatus

1 is a schematic diagram of a conventional CIRC decoder.

FIG. 2 is a diagram showing memory usage positions of C1 and C2 series in the CIRC decoder of FIG.

3 is a schematic diagram of a CIRC decoder according to the present invention.

4 is a diagram showing memory usage positions of a 1C ₁ , 1C ₂ , 2C _1, and 2C ₂ series in the CIRC decoder of FIG. 3.

The present invention relates to an error correction method and apparatus for digital signal processing apparatus, and more particularly, to an improved method for decoding CIRC (Circular Interleave Reed-solomon Code) and apparatus.

Digital signal processing devices, such as CDP (Compact Disc Player) or DAT (Digital Audio Tape Player), can be used to detect errors due to scratches beyond the acceptable range during the manufacturing or use of recording media such as optical discs or magnetic tapes. CIRC is used as an error correction method to correct. The CD-based CIRC combines a Reed-Solomen code, which is an error correction code with a high random error correction capability, and a cyclic interleaving method, which converts burst errors into random errors by interleaving. That is, in the CD method, six samples of L and R two channels, that is, 12 samples of audio signals represented by 16 bits are formed in one unit, and each 16 bit data is divided into the 8 bits and the lower 8 bits, and each 8 bit data is divided into one. Treated as a symbol (or word). Therefore, 12 samples are formed of 24 symbols. Such 24 symbol data is delayed by two words for even-numbered sample-time data, and the 24-symbol data are crossed so that adjacent data are separated from each other by a predetermined interval. The first error correction code C ₂ is formed from the 24 symbol data arranged in such a manner as to intersect. This C ₂ is a Reed Solomon code with redundancy of 4 with n = 28 and k = 24 with a minimum distance of 5. Mark the parity of C ₂ Q. The first checkword sequence, i.e., Q parity, which is four symbol data, is disposed at the center of the 24 symbol data.

Subsequently, a total of 28 symbols data of 4 symbols of Q parity and 24 symbols are interleaved with a different amount of delay for each symbol. The differential delay is a 1D, 2D, 3D, 4D ... momentarily from the second symbol data except the first symbol data based on the constant delay amount (D) of 4 words. Differential delays are delayed by 26D and 27D, where D is the unit delay amount. The second error correction code (C ₁ ) is formed from the 28 delayed data. C ₁ is Reed Solomon's code with n = 32, k = 28 with redundancy of 4. Minimum distance is 5. The parity of C ₁ is called P. The second checkword sequence, i.e., P parity, which is four symbol data, is placed after the last symbol data of 28 symbol data. Next, encoding is completed by delaying the even-numbered symbol data by one word to generate a total of 32 symbol data. The 32-symbol data encoded by CIRC is corrected and restored by correcting errors detected by P and Q parity while processing the symbol data in the reverse order of encoding in the CIRC decoder. Therefore, in the conventional CIRC decoder, only errors within the error correction capability of the C ₁ and C ₂ series are corrected. That is, the correction ability of the C ₁ series with a minimum distance of 5 can be corrected up to 2 symbols, and the correction capability of the C ₂ series with a minimum distance of 5 can be corrected up to 4 symbols by using the error detection and correction results of the C ₁ series. Can be. However, when a large number of error data exist on the optical disc, error data that cannot be corrected by the C ₁ and C ₂ error correction capabilities exist. Thus, uncorrected error data results in significantly different data from the original data, and noise is generated in the audio signal reproduced from the obtained data. SUMMARY OF THE INVENTION An object of the present invention is to provide a data error correction method and apparatus for which the error correction capability is remarkably improved in order to solve the problems of the prior art.

The error correction decoding method of the present invention for achieving the above object is generated from a data word string corresponding to a plurality of parallel channels, a first check word string generated from the data word string, and the data word string and the first check word string. An error correcting method of a data error correcting apparatus comprising a second checkword string and a data string interleaved with each word in a Reed-Solomon code, for error correction. Receiving the data string each time; Generating a first decoded and error-corrected dataword sequence and a first checkword sequence each time by a first syndrome generated by the received second checkword sequence; Rearranging the first decoded and error corrected dataword sequence and the first checkword sequence with different delay times; Generating a second decoded and error-corrected dataword sequence each time by a second syndrome caused by the rearranged first checkword sequence; Restoring the second decoded and error-corrected dataword sequence and the first and second checkword sequences to an arrangement state prior to the rearrangement, again by a third syndrome caused by the restored rearranged second checkword sequence Generating a first decoded and error corrected dataword sequence and a first checkword sequence each time; rearranging the generated dataword sequence and the first checkword sequence again with the different delay times; Repeating a process of generating a second decoded and error-corrected dataword string each time again by the fourth syndrome caused by one checkword string; And outputting the second decoded and error-corrected dataword string each time on a plurality of parallel channels again at least once or more.

The error correction decoding apparatus of the present invention comprises a dataword sequence corresponding to a parallel channel, a first checkword sequence generated from the dataword sequence, and a second checkword sequence generated from the dataword sequence and the first checkword sequence. A data error correcting apparatus for decoding a data string inserted between each word and intersecting each word into a Reed Solomon code, comprising: input means for inputting the data string each time in parallel on a plurality of channels equivalent to the data string; A first decoder that decodes the dataword sequence input through the input means and generates a first decoded and error-corrected dataword sequence and a first checkword sequence each time by a first syndrome generated by the second checkword sequence ; First delay means for rearranging the dataword sequence and the first checkword sequence output from the first decoder with different delay times; Generating a second decoded and error-corrected dataword sequence each time by a second syndrome caused by the first checkword sequence by encoding the dataword sequence and the first checkword sequence rearranged by the first delay means. A second decoder; A second word for restoring the data word sequence and the first checkword sequence output from the second decoder and the second checkword sequence output from the first decoder to an arrangement state before being rearranged by the first delay means; 2 delay means; A first decoded and error-corrected dataword sequence decoded again by the third syndrome generated by the second checkword sequence by decoding the dataword sequence and the first and second checkword sequences restored and arranged by the second delay means; A third decoder for generating a first checkword string each time; Third delay means for rearranging the dataword sequence and the second checkword sequence output from the third decoder with the different delay times; Decode the dataword sequence and the first checkword sequence rearranged by the third delay means to generate a second decoded and error-corrected dataword sequence each time by a fourth syndrome caused by the first checkword sequence. A fourth decoder; And output means for outputting a data word string output from the fourth decoder on a plurality of parallel channels each time.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, a conventional CIRC decoding method will be described with reference to FIGS. 1 and 2 to help understand the present invention.

1 is a system diagram showing a conventional decoding device of CIRC.

The 32 symbol data, i.e., data strings, denoted by W, P, and Q in FIG. 1 are signals picked up and demodulated from the optical disc. The 24 symbol data denoted by W, i.e., the dataword strings are audio data, and P and Q are parity data for error detection and correction, i.e., the first and second checkword strings. 32 symbol data are supplied to the CIRC decoder. The CIRC decoder comprises an input means 11, i.e., a descramble means 11a and an inverter means 11b, a first decoder, i.e. a C ₁ decoding means 12, and a first delay means, i.e. a deinterleaving means 13 and the second consists of a decoder, that is, C ₂ decoder 14 and an output means, i.e., inverse cross time delay (15). The descrambling means 11a is composed of 16 single word delay lines and delays the scrambled 32 symbol data by one word from the head to even numbered symbol data. That is, since the size of the groove formed on the optical disk in the CD system is less than 8 bits, the signal processing means is 8 bit = 1 symbol data, so the error caused by the groove of the optical disk is one symbol unit. However, if there is a flaw between symbols, it is an error of two symbols. Therefore, a symbol unit delay is performed to inject this continuous error, which is called a scramble process, and during reproduction, a descramble process is performed to release the scramble process. The inverter means 11b inverts 0 and 1 of the 4 symbol data of the Q parity and the 4 symbol data of the P parity. This is to restore the inverted 0 and 1 of the 8 symbol data of P and Q as part of countermeasures against fixed patterns and burst errors during encoding.

The C ₁ decoding means 12 detects the burst error of the remaining 28 symbol data using 4 symbol data of P parity among the 32 symbol data, and also corrects the random error slightly. In this case, the error correction generates four syndromes according to a parity check matrix, that is, a Reed Solomon code, and has only a correction capability for one symbol by this syndrome. If two or more symbol errors occur, the data block is determined to be error correctable, and 28 symbol data are transmitted to the next stage without correction. In this case, a mark (at least 1 bit) is added to every word of the data string to indicate the presence or absence of an error.

The deinterleaving means 13 releases interleaving by differentially delaying the 28 symbol data transmitted from the C ₁ decoding means 12. That is, most of the errors that occur during the reproduction of the optical disc can be regarded as scratches, dust and dirt, so that once a defect occurs, several adjacent symbols are damaged at once. If many symbols are damaged in the same data block, error detection or correction becomes impossible. Therefore, during recording, the symbols in the same data block are distributed to other data blocks, and during reproduction, the distributed symbols are restored to the original data block position. The recovery process is deinterleaved.

The deinterleaving means 13 is provided with 27D, 26D, 25D,... For delaying 28 symbol data on a basis of a constant delay amount of 4 words. Delay lines having different delay times of 2D and 1D are composed of the first to 27th transmission channels.

The C ₂ decoding means 14 uses the 4 symbol data of Q parity among the 28 symbol data restored to the original data block position because interleaving is released, that is, 28 data words are all delayed by the same 27D delay time. Four syndromes are generated from the sign and input 28 words, correcting up to four symbol errors. In this case, the mark on the error corrected word is erased, but the mark on the error word that cannot be corrected is not erased.

The reverse crossing time delay means 15 crosses each other to restore the 24 symbol data supplied from the C ₂ decoding means 14 to their original positions in the data block, and delays two words of symbol data adjacent to the time axis during encoding. In order to restore the scattered data to the original position, the two-word delay processing is performed. Such delay processing is for avoiding outputting uncorrectable error data continuously during reproduction.

A memory such as RAM is used to perform such a conventional CIRC decoder. 2 shows memory locations of C ₁ and C ₂ series for CIRC decoding. The memory has a size in which symbol addresses are 0 to 31 and block addresses are n to n-108. The C ₁ decoding means 12 takes the symbol data at the memory location shown in Table 1 below to take the descrambled 32 symbol data from the scrambled 32 symbol data. Then, the C ₂ decoding means 14 takes the symbol data at the memory location shown in Table 2 below to take the deinterleaved 28 symbol data from the interleaved 28 symbol data. In addition, the 24 symbol data at the memory locations shown in Table 3 are provided as the final decoating output of the cross-delayed CIRC.

TABLE 1

TABLE 2

TABLE 3

However, since the conventional CIRC decoding process performs error correction once for each of the C ₁ series and the C ₂ series, the error is corrected when a large number of error data are generated beyond the error correction capability of the C ₁ and C ₂ series. Instead of being played as audio. Therefore, there is a problem in that the quality of the reproduced audio signal deteriorates due to noise generated by an uncorrected error.

The present invention is to improve the error correction capability by improving the CIRC decoding method to solve the problems of the prior art by performing the error correction of the C ₁ and C ₂ series two or more times. In other words, after performing the first error correction of the C ₁ and C ₂ series, interleaving the 28 symbol data of the C ₂ series error correction result again, and delaying the interleaved 28 symbol data, the second C ₁ is the 4 symbol data of P parity. Perform error correction of the series. After deinterleaving 28 symbol data of the second C ₁ series error correction result again, the second C ₂ series error correction is performed with 4 symbol data of Q parity. Therefore, in the first two symbol series C _1, C _2, the first series in the 4 symbols, 4 symbols, and the second series in the second C ₂ C ₁ sequence can correct the error of the fourth symbol.

As shown in FIG. 3, the CIRC decoding system of the present invention comprises an input means 11, that is, a descrambling means 11a and an inverter means 11b, a first decoder, that is, a 1C ₁ decoding means 12, The first delay means, i.e., the first deinterleaving means 13, the second decoder, i.e. the 1C ₂ decoding means 14, the second delay means, i.e. the interleaving means 16, and the third decoder, i.e. the 2C ₁ decoding means 17 and the third delay means, that the second de-interleaving means 18 and a fourth decoder that is the 2C _second decoding means 19, output means that is cross delay processing means 15 Consists of. The same parts as in FIG. 1 are denoted by the same reference numerals. The input unit 11 includes a plurality of delay lines for delaying word data received through an odd number channel among the plurality of channels with a delay time of one word, and a plurality of inverting first and second checkword strings. The inverter is provided. That is, the improved CIRC decoder of the present invention performs error correction by the C ₁ and C ₂ decoding means 12 and 14, and then performs 24 symbol data of the 1 C ₂ decoding means 14, The two check word strings are input to the second delay means 16 for restoring the arrangement state of the data strings input to the first delay means 13. In the second delay means 16, 1D, 2D, 3D... From the second transport channel except the first transport channel to interleave 28 symbol data again. 29th to 32nd channel as a delay line having a delay amount of 27D for delaying four one-check word strings supplied from the 1C ₂ decoding means 14 and configured with a delay property having a delay amount of 26D and 27D. Configure

The 32 data strings interleaved by the second delay means 16 are subjected to the same error correction process as the method of decoding and error correcting the 1C ₁ decoding means 12 described above in the 2C ₁ decoding means 17. Correction is made and an error mark is performed for all words. 2C the output data string of the _first decoding means 17 is again de-interleaved by a third delay means (18). The output data string of the deinterleaved third delay means 18 is supplied to the _second C ₂ decoding means 19. The second C ₂ decoding means 19 performs error correction on the input data string and outputs the same by the same procedure as the above-described first C ₂ decoding means 14. The output data string of the 2C ₂ decoding means 19 is outputted as the final error corrected data word string through the output means and the reverse crossover delay means 15.

The output means 15 crosses a plurality of output channels with each other in order to rearrange the data word sequence output from the fourth decoder from an array of 6 channels and 4 cycles to an array of 8 channels and 3 cycles. And a plurality of delay lines for delaying the fifth through eighth channels and the delay time of two words, respectively. The input means, the first, second and third delay means and the output means are made by allocating a predetermined area to one RAM, respectively.

In the decoding system of CIRC according to the present invention of FIG. 3, the capacity of the C ₁ and C ₂ series is increased by doubling the capacity of the buffer memory as shown in FIG. Error correction can be repeated twice.

TABLE 4

Therefore, the additional memory required by the CIRC decoding system according to the present invention is capable of reproducing 32 symbol data × 27D = 3456 symbol data, resulting in 3456 × 8bit = 27648 bits. Here, D = 4 words means a certain amount of delay. Therefore, the capacity of the buffer memory can be used by using 55296 (= 27648 x 2) bits, that is, 64K RAM, for two times of decoding of the C ₁ and C ₂ series. In the present embodiment, two repetitions are described as an example, but three repetitions, four repetitions,... Etc., it is expandable by providing additional memory. When repeated twice or more C ₁ and C ₂ of the error correction sequence as compared with the case for the error correction of the one-time C ₁ and C _2, the sequence can be seen that the error correcting capability is improved in proportion to the number of iterations.

Claims (5)

A dataword sequence corresponding to a plurality of parallel channels, a first checkword sequence generated from the dataword sequence, and a second checkword sequence generated from the dataword sequence and the first checkword sequence, and the words cross each other. An error correction method of a data error correction apparatus for decoding an intermediately inserted data string by a Reed Solomon code, the method comprising: inputting the data string each time in parallel on a plurality of channels equivalent to the data string; Generating a first decoded and error-corrected dataword sequence and a first checkword sequence each time by a first syndrome generated by the received second checkword sequence; Rearranging the first decoded and error corrected dataword sequence and the first checkword sequence with different delay times; Generating a second decoded and error-corrected dataword sequence each time by a second syndrome caused by the rearranged first checkword sequence; Restoring the second decoded and error-corrected dataword sequence and the first and second checkword sequences to an arrangement state before the rearrangement, again by a third syndrome caused by the restored rearranged second checkword sequence Generating a first decoded and error corrected dataword sequence and a first checkword sequence each time; rearranging the generated dataword sequence and the first checkword sequence again with the different delay times; Repeating a process of generating a second decoded and error-corrected dataword string each time again by the fourth syndrome caused by one checkword string; And outputting the second decoded and error-corrected dataword string each time on a plurality of parallel channels again at least once more. A dataword sequence corresponding to a plurality of parallel channels, a first checkword sequence generated from the dataword sequence, and a second checkword sequence generated from the dataword sequence and the first checkword sequence, and the words cross each other. A data error correcting apparatus for decoding an interpolated data string into a Reed Solomon code and correcting the error, comprising: input means for inputting the data string each time in parallel on a plurality of channels equivalent to the data string; A first decoder which decodes the data string input through the input means and generates a first decoded and error corrected dataword string and a first checkword string each time by a first syndrome generated by the second checkword string; First delay means for rearranging the dataword sequence and the first checkword sequence output from the first decoder with different delay times; Generating a second decoded and error-corrected dataword sequence each time by a second syndrome caused by the first checkword sequence by encoding the dataword sequence and the first checkword sequence rearranged by the first delay means. A second decoder; A second word for restoring the data word sequence and the first checkword sequence output from the second decoder and the second checkword sequence output from the first decoder to an arrangement state before being rearranged by the first delay means; 2 delay means; A first decoded and error-corrected dataword sequence decoded again by the third syndrome generated by the second checkword sequence by decoding the dataword sequence and the first and second checkword sequences restored and arranged by the second delay means; A third decoder for generating a first checkword string each time; Third delay means for rearranging the dataword sequence and the second checkword sequence output from the third decoder with the different delay times; Decode the dataword sequence and the first checkword sequence rearranged by the third delay means to generate a second decoded and error-corrected dataword sequence each time by the fourth syndrome generated by the first checkword sequence. A fourth decoder; And output means for outputting a data word string output from the fourth decoder on a plurality of parallel channels each time. 3. The apparatus of claim 2, wherein the input unit inverts a plurality of delay lines for delaying word data received through an odd-numbered channel of the plurality of channels with a delay time of one word, and the first and second check word strings. And a plurality of inverters for transmitting the data error correction decoding apparatus. The method of claim 3, wherein the output means crosses a plurality of output channels to each other and rearranges the data word sequence output from the fourth decoder into an array of eight channels and three cycles in an array of six channels and four cycles. And a plurality of delay lines for respectively delaying the fifth to eighth channels of the eight channels of the second channel with a delay time of two words. 3. The error correcting decoding apparatus according to claim 2, wherein the input means, the first, second and third delay means and the output means are allocated by assigning predetermined regions to one RAM, respectively.